1*2557Swnj struct device { 2*2557Swnj u_short tmer; 3*2557Swnj u_short tmcs; 4*2557Swnj short tmbc; 5*2557Swnj u_short tmba; 6*2557Swnj short tmdb; 7*2557Swnj short tmrd; 8*2557Swnj }; 9*2557Swnj 10*2557Swnj #define b_repcnt b_bcount 11*2557Swnj #define b_command b_resid 12*2557Swnj 13*2557Swnj /* bits in tmcs */ 14*2557Swnj #define GO 01 15*2557Swnj #define OFFL 0 16*2557Swnj #define RCOM 02 17*2557Swnj #define WCOM 04 18*2557Swnj #define WEOF 06 19*2557Swnj #define SFORW 010 20*2557Swnj #define SREV 012 21*2557Swnj #define WIRG 014 22*2557Swnj #define REW 016 23*2557Swnj #define IENABLE 0100 24*2557Swnj #define CUR 0200 25*2557Swnj #define NOP IENABLE 26*2557Swnj #define DCLR 010000 27*2557Swnj #define D800 060000 28*2557Swnj #define ERROR 0100000 29*2557Swnj 30*2557Swnj /* bits in tmer */ 31*2557Swnj #define TUR 1 32*2557Swnj #define RWS 02 33*2557Swnj #define WRL 04 34*2557Swnj #define SDWN 010 35*2557Swnj #define BOT 040 36*2557Swnj #define SELR 0100 37*2557Swnj #define NXM 0200 38*2557Swnj #define TMBTE 0400 39*2557Swnj #define RLE 01000 40*2557Swnj #define EOT 02000 41*2557Swnj #define BGL 04000 42*2557Swnj #define PAE 010000 43*2557Swnj #define CRE 020000 44*2557Swnj #define EOF 040000 45*2557Swnj #define ILC 0100000 46*2557Swnj 47*2557Swnj #define HARD (ILC|EOT) 48*2557Swnj #define SOFT (CRE|PAE|BGL|RLE|TMBTE|NXM) 49*2557Swnj 50