xref: /csrg-svn/sys/vax/uba/tmreg.h (revision 29243)
123347Smckusick /*
2*29243Smckusick  * Copyright (c) 1982, 1986 Regents of the University of California.
323347Smckusick  * All rights reserved.  The Berkeley software License Agreement
423347Smckusick  * specifies the terms and conditions for redistribution.
523347Smckusick  *
6*29243Smckusick  *	@(#)tmreg.h	7.1 (Berkeley) 06/05/86
723347Smckusick  */
82562Swnj 
92612Swnj /*
102612Swnj  * TM11 controller registers
112612Swnj  */
125689Sroot struct tmdevice {
132612Swnj 	u_short	tmer;		/* error register, per drive */
142612Swnj 	u_short	tmcs;		/* control-status register */
152612Swnj 	short	tmbc;		/* byte/frame count */
162612Swnj 	u_short tmba;		/* address */
172612Swnj 	short	tmdb;		/* data buffer */
182612Swnj 	short	tmrd;		/* read lines */
192612Swnj 	short	tmmr;		/* maintenance register */
2024978Smckusick #ifdef	AVIV
2124978Smckusick 	short	tmfsr;		/* formatter status reading */
2224978Smckusick #endif
232557Swnj };
242557Swnj 
252557Swnj #define	b_repcnt  b_bcount
262557Swnj #define	b_command b_resid
272557Swnj 
282557Swnj /* bits in tmcs */
292612Swnj #define	TM_GO		0000001
302612Swnj #define	TM_OFFL		0000000		/* offline */
312612Swnj #define	TM_RCOM		0000002		/* read */
322612Swnj #define	TM_WCOM		0000004		/* write */
332612Swnj #define	TM_WEOF		0000006		/* write-eof */
342612Swnj #define	TM_SFORW	0000010		/* space forward */
352612Swnj #define	TM_SREV		0000012		/* space backwards */
362612Swnj #define	TM_WIRG		0000014		/* write with xtra interrecord gap */
372612Swnj #define	TM_REW		0000016		/* rewind */
382612Swnj #define	TM_SENSE	TM_IE		/* sense (internal to driver) */
392688Swnj 
402688Swnj #define	tmreverseop(cmd)		((cmd)==TM_SREV || (cmd)==TM_REW)
412688Swnj 
422612Swnj /* TM_SNS is a pseudo-op used to get tape status */
432612Swnj #define	TM_IE		0000100		/* interrupt enable */
442612Swnj #define	TM_CUR		0000200		/* control unit is ready */
452612Swnj #define	TM_DCLR		0010000		/* drive clear */
462612Swnj #define	TM_D800		0060000		/* select 800 bpi density */
472612Swnj #define	TM_ERR		0100000		/* drive error summary */
482557Swnj 
492557Swnj /* bits in tmer */
503097Swnj #define	TMER_ILC	0100000		/* illegal command */
513097Swnj #define	TMER_EOF	0040000		/* end of file */
523097Swnj #define	TMER_CRE	0020000		/* cyclic redundancy error */
533097Swnj #define	TMER_PAE	0010000		/* parity error */
543097Swnj #define	TMER_BGL	0004000		/* bus grant late */
553097Swnj #define	TMER_EOT	0002000		/* at end of tape */
563097Swnj #define	TMER_RLE	0001000		/* record length error */
573097Swnj #define	TMER_BTE	0000400		/* bad tape error */
583097Swnj #define	TMER_NXM	0000200		/* non-existant memory */
593097Swnj #define	TMER_SELR	0000100		/* tape unit properly selected */
603097Swnj #define	TMER_BOT	0000040		/* at beginning of tape */
613097Swnj #define	TMER_CH7	0000020		/* 7 channel tape */
623097Swnj #define	TMER_SDWN	0000010		/* gap settling down */
633097Swnj #define	TMER_WRL	0000004		/* tape unit write protected */
643097Swnj #define	TMER_RWS	0000002		/* tape unit rewinding */
653097Swnj #define	TMER_TUR	0000001		/* tape unit ready */
662557Swnj 
673097Swnj #define	TMER_BITS	\
682688Swnj "\10\20ILC\17EOF\16CRE\15PAE\14BGL\13EOT\12RLE\11BTE\10NXM\
692688Swnj \7SELR\6BOT\5CH7\4SDWN\3WRL\2RWS\1TUR"
702688Swnj 
713097Swnj #define	TMER_HARD	(TMER_ILC|TMER_EOT)
723097Swnj #define	TMER_SOFT	(TMER_CRE|TMER_PAE|TMER_BGL|TMER_RLE|TMER_BTE|TMER_NXM)
7324978Smckusick 
7424978Smckusick #ifdef	AVIV
7524978Smckusick /* bits in tmmr (formatter diagnostic reading) */
7624978Smckusick #define	DTS		000000		/* select dead track status */
7724978Smckusick #   define	DTS_MASK	0xff
7824978Smckusick 
7924978Smckusick #define	DAB		010000		/* select diagnostic aid bits */
8024978Smckusick #   define  DAB_MASK		037	/* reject code only */
8124978Smckusick 
8224978Smckusick #define	RWERR		020000		/* select read-write errors */
8324978Smckusick #    define RWERR_MASK		01777	/* include bit 9 (MAI) */
8424978Smckusick #    define RWERR_BITS \
8524978Smckusick "\10\12MAI\11CRC ERR\10WTMCHK\7UCE\6PART REC\5MTE\3END DATA CHK\
8624978Smckusick \2VEL ERR\1DIAG MODE"
8724978Smckusick 
8824978Smckusick #define	DRSENSE		030000		/* select drive sense */
8924978Smckusick #    define DRSENSE_MASK	0777
9024978Smckusick #    define DRSENSE_BITS \
9124978Smckusick "\10\11WRTS\10EOTS\7BOTS\6WNHB\5PROS\4BWDS\3HDNG\2RDYS\1ON LINE"
9224978Smckusick 
9324978Smckusick #define	CRCF		040000		/* CRC-F Generator */
9424978Smckusick 
9524978Smckusick #define	FSR_BITS \
9624978Smckusick "\10\20REJ\17TMS\16OVRN\15DATACHK\14SSC\13EOTS\12WRTS\11ROMPS\10CRERR\
9724978Smckusick \7ONLS\6BOTS\5HDENS\4BUPER\3FPTS\2REWS\1RDYS"
9824978Smckusick #endif	AVIV
99