1*2928Swnj /* tm.c 4.22 03/06/81 */ 21919Swnj 32709Swnj #include "te.h" 42630Swnj #if NTM > 0 52670Swnj int tmgapsdcnt; /* DEBUG */ 61919Swnj /* 72630Swnj * TM11/TE10 tape driver 82471Swnj * 9*2928Swnj * Todo: 10*2928Swnj * Test driver with more than one slave 11*2928Swnj * Test reset code 12*2928Swnj * Do rewinds without hanging in driver 131919Swnj */ 142471Swnj #define DELAY(N) { register int d = N; while (--d > 0); } 151919Swnj #include "../h/param.h" 161919Swnj #include "../h/buf.h" 171919Swnj #include "../h/dir.h" 181919Swnj #include "../h/conf.h" 191919Swnj #include "../h/user.h" 201919Swnj #include "../h/file.h" 211919Swnj #include "../h/map.h" 221919Swnj #include "../h/pte.h" 232574Swnj #include "../h/vm.h" 241919Swnj #include "../h/uba.h" 251919Swnj #include "../h/mtio.h" 261919Swnj #include "../h/ioctl.h" 272363Swnj #include "../h/cmap.h" 282396Swnj #include "../h/cpu.h" 291919Swnj 302396Swnj #include "../h/tmreg.h" 311919Swnj 322630Swnj struct buf ctmbuf[NTE]; 332630Swnj struct buf rtmbuf[NTE]; 341919Swnj 352608Swnj int tmprobe(), tmslave(), tmattach(), tmdgo(), tmintr(); 362630Swnj struct uba_minfo *tmminfo[NTM]; 372630Swnj struct uba_dinfo *tmdinfo[NTE]; 382630Swnj struct buf tmutab[NTE]; 392608Swnj #ifdef notyet 402630Swnj struct uba_dinfo *tmip[NTM][4]; 412608Swnj #endif 422458Swnj u_short tmstd[] = { 0772520, 0 }; 432396Swnj struct uba_driver tmdriver = 442630Swnj { tmprobe, tmslave, tmattach, tmdgo, tmstd, "te", tmdinfo, "tm", tmminfo, 0 }; 451919Swnj 461919Swnj /* bits in minor device */ 472608Swnj #define TMUNIT(dev) (minor(dev)&03) 481919Swnj #define T_NOREWIND 04 491919Swnj #define T_1600BPI 08 501919Swnj 511919Swnj #define INF (daddr_t)1000000L 521919Swnj 532608Swnj /* 542608Swnj * Software state per tape transport. 552608Swnj */ 562471Swnj struct tm_softc { 572608Swnj char sc_openf; /* lock against multiple opens */ 582608Swnj char sc_lastiow; /* last op was a write */ 592608Swnj daddr_t sc_blkno; /* block number, for block device tape */ 602608Swnj daddr_t sc_nxrec; /* desired block position */ 612608Swnj u_short sc_erreg; /* copy of last erreg */ 622608Swnj u_short sc_dsreg; /* copy of last dsreg */ 632608Swnj short sc_resid; /* copy of last bc */ 64*2928Swnj #ifdef notdef 652670Swnj short sc_lastcmd; /* last command to handle direction changes */ 66*2928Swnj #endif 672630Swnj } tm_softc[NTM]; 681919Swnj 692608Swnj /* 702608Swnj * States for um->um_tab.b_active, the 712608Swnj * per controller state flag. 722608Swnj */ 731919Swnj #define SSEEK 1 /* seeking */ 741919Swnj #define SIO 2 /* doing seq i/o */ 751919Swnj #define SCOM 3 /* sending control command */ 762608Swnj #define SREW 4 /* sending a drive rewind */ 771919Swnj 782608Swnj /* WE CURRENTLY HANDLE REWINDS PRIMITIVELY, BUSYING OUT THE CONTROLLER */ 792608Swnj /* DURING THE REWIND... IF WE EVER GET TWO TRANSPORTS, WE CAN DEBUG MORE */ 802608Swnj /* SOPHISTICATED LOGIC... THIS SIMPLE CODE AT LEAST MAY WORK. */ 811919Swnj 822426Skre /* 832426Skre * Determine if there is a controller for 842426Skre * a tm at address reg. Our goal is to make the 852426Skre * device interrupt. 862426Skre */ 872608Swnj tmprobe(reg) 882396Swnj caddr_t reg; 892396Swnj { 902458Swnj register int br, cvec; 912426Skre 922608Swnj #ifdef lint 932608Swnj br = 0; br = cvec; cvec = br; 942608Swnj #endif 952608Swnj ((struct device *)reg)->tmcs = TM_IE; 962396Swnj /* 972630Swnj * If this is a tm11, it ought to have interrupted 982396Swnj * by now, if it isn't (ie: it is a ts04) then we just 992458Swnj * hope that it didn't interrupt, so autoconf will ignore it. 1002458Swnj * Just in case, we will reference one 1012396Swnj * of the more distant registers, and hope for a machine 1022458Swnj * check, or similar disaster if this is a ts. 1032471Swnj * 1042471Swnj * Note: on an 11/780, badaddr will just generate 1052471Swnj * a uba error for a ts; but our caller will notice that 1062471Swnj * so we won't check for it. 1072396Swnj */ 1082396Swnj if (badaddr(&((struct device *)reg)->tmrd, 2)) 1092458Swnj return (0); 1102458Swnj return (1); 1112396Swnj } 1122396Swnj 1132608Swnj /* 1142608Swnj * Due to a design flaw, we cannot ascertain if the tape 1152608Swnj * exists or not unless it is on line - ie: unless a tape is 1162608Swnj * mounted. This is too servere a restriction to bear, 1172608Swnj * so all units are assumed to exist. 1182608Swnj */ 1192608Swnj /*ARGSUSED*/ 1202574Swnj tmslave(ui, reg) 1212396Swnj struct uba_dinfo *ui; 1222396Swnj caddr_t reg; 1232396Swnj { 1242458Swnj 1252458Swnj return (1); 1262396Swnj } 1272396Swnj 1282608Swnj /* 1292608Swnj * Record attachment of the unit to the controller port. 1302608Swnj */ 1312608Swnj /*ARGSUSED*/ 1322608Swnj tmattach(ui) 1332608Swnj struct uba_dinfo *ui; 1342608Swnj { 1352608Swnj 1362608Swnj #ifdef notyet 1372608Swnj tmip[ui->ui_ctlr][ui->ui_slave] = ui; 1382608Swnj #endif 1392608Swnj } 1402608Swnj 1412608Swnj /* 1422608Swnj * Open the device. Tapes are unique open 1432608Swnj * devices, so we refuse if it is already open. 1442608Swnj * We also check that a tape is available, and 1452608Swnj * don't block waiting here. 1462608Swnj */ 1471919Swnj tmopen(dev, flag) 1481919Swnj dev_t dev; 1491919Swnj int flag; 1501919Swnj { 1512608Swnj register int unit; 1522396Swnj register struct uba_dinfo *ui; 1532608Swnj register struct tm_softc *sc; 1541919Swnj 1552608Swnj unit = TMUNIT(dev); 1562630Swnj if (unit>=NTE || (sc = &tm_softc[unit])->sc_openf || 1572608Swnj (ui = tmdinfo[unit]) == 0 || ui->ui_alive == 0) { 1582608Swnj u.u_error = ENXIO; 1591919Swnj return; 1601919Swnj } 1612608Swnj tmcommand(dev, TM_SENSE, 1); 162*2928Swnj if ((sc->sc_erreg&(TM_SELR|TM_TUR)) != (TM_SELR|TM_TUR) || 163*2928Swnj (flag&(FREAD|FWRITE)) == FWRITE && sc->sc_erreg&TM_WRL) { 1642471Swnj u.u_error = EIO; 1652608Swnj return; 1661919Swnj } 1672608Swnj sc->sc_openf = 1; 1682471Swnj sc->sc_blkno = (daddr_t)0; 1692471Swnj sc->sc_nxrec = INF; 1702608Swnj sc->sc_lastiow = 0; 1711919Swnj } 1721919Swnj 1732608Swnj /* 1742608Swnj * Close tape device. 1752608Swnj * 1762608Swnj * If tape was open for writing or last operation was 1772608Swnj * a write, then write two EOF's and backspace over the last one. 1782608Swnj * Unless this is a non-rewinding special file, rewind the tape. 1792608Swnj * Make the tape available to others. 1802608Swnj */ 1811919Swnj tmclose(dev, flag) 1821919Swnj register dev_t dev; 1831919Swnj register flag; 1841919Swnj { 1852608Swnj register struct tm_softc *sc = &tm_softc[TMUNIT(dev)]; 1861919Swnj 1872608Swnj if (flag == FWRITE || (flag&FWRITE) && sc->sc_lastiow) { 1882608Swnj tmcommand(dev, TM_WEOF, 1); 1892608Swnj tmcommand(dev, TM_WEOF, 1); 1902608Swnj tmcommand(dev, TM_SREV, 1); 1911919Swnj } 1921919Swnj if ((minor(dev)&T_NOREWIND) == 0) 1932608Swnj tmcommand(dev, TM_REW, 1); 1942471Swnj sc->sc_openf = 0; 1951919Swnj } 1961919Swnj 1972608Swnj /* 1982608Swnj * Execute a command on the tape drive 1992608Swnj * a specified number of times. 2002608Swnj */ 2012574Swnj tmcommand(dev, com, count) 2021919Swnj dev_t dev; 2031919Swnj int com, count; 2041919Swnj { 2051919Swnj register struct buf *bp; 2061919Swnj 2072608Swnj bp = &ctmbuf[TMUNIT(dev)]; 2081919Swnj (void) spl5(); 2091919Swnj while (bp->b_flags&B_BUSY) { 2101919Swnj bp->b_flags |= B_WANTED; 2111919Swnj sleep((caddr_t)bp, PRIBIO); 2121919Swnj } 2131919Swnj bp->b_flags = B_BUSY|B_READ; 2141919Swnj (void) spl0(); 2151919Swnj bp->b_dev = dev; 2161919Swnj bp->b_repcnt = -count; 2171919Swnj bp->b_command = com; 2181919Swnj bp->b_blkno = 0; 2191919Swnj tmstrategy(bp); 2201919Swnj iowait(bp); 2211919Swnj if (bp->b_flags&B_WANTED) 2221919Swnj wakeup((caddr_t)bp); 2231919Swnj bp->b_flags &= B_ERROR; 2241919Swnj } 2251919Swnj 2262608Swnj /* 2272608Swnj * Decipher a tape operation and do what is needed 2282608Swnj * to see that it happens. 2292608Swnj */ 2301919Swnj tmstrategy(bp) 2311919Swnj register struct buf *bp; 2321919Swnj { 2332608Swnj int unit = TMUNIT(bp->b_dev); 2342608Swnj register struct uba_minfo *um; 2352608Swnj register struct buf *dp; 2362608Swnj register struct tm_softc *sc = &tm_softc[unit]; 2371919Swnj 2382608Swnj /* 2392608Swnj * Put transfer at end of unit queue 2402608Swnj */ 2412608Swnj dp = &tmutab[unit]; 2421919Swnj bp->av_forw = NULL; 2431919Swnj (void) spl5(); 2442608Swnj if (dp->b_actf == NULL) { 2452608Swnj dp->b_actf = bp; 2462608Swnj /* 2472608Swnj * Transport not already active... 2482608Swnj * put at end of controller queue. 2492608Swnj */ 2502608Swnj dp->b_forw = NULL; 2512608Swnj um = tmdinfo[unit]->ui_mi; 2522608Swnj if (um->um_tab.b_actf == NULL) 2532608Swnj um->um_tab.b_actf = dp; 2542608Swnj else 2552608Swnj um->um_tab.b_actl->b_forw = dp; 2562608Swnj um->um_tab.b_actl = dp; 2572608Swnj } else 2582608Swnj dp->b_actl->av_forw = bp; 2592608Swnj dp->b_actl = bp; 2602608Swnj /* 2612608Swnj * If the controller is not busy, get 2622608Swnj * it going. 2632608Swnj */ 2642608Swnj if (um->um_tab.b_active == 0) 2652608Swnj tmstart(um); 2661919Swnj (void) spl0(); 2671919Swnj } 2681919Swnj 2692608Swnj /* 2702608Swnj * Start activity on a tm controller. 2712608Swnj */ 2722608Swnj tmstart(um) 2732608Swnj register struct uba_minfo *um; 2741919Swnj { 2752608Swnj register struct buf *bp, *dp; 2762608Swnj register struct device *addr = (struct device *)um->um_addr; 2772608Swnj register struct tm_softc *sc; 2782396Swnj register struct uba_dinfo *ui; 2792608Swnj int unit, cmd; 2802471Swnj daddr_t blkno; 2811919Swnj 2822608Swnj /* 2832608Swnj * Look for an idle transport on the controller. 2842608Swnj */ 2851919Swnj loop: 2862608Swnj if ((dp = um->um_tab.b_actf) == NULL) 2871919Swnj return; 2882608Swnj if ((bp = dp->b_actf) == NULL) { 2892608Swnj um->um_tab.b_actf = dp->b_forw; 2902608Swnj goto loop; 2912608Swnj } 2922608Swnj unit = TMUNIT(bp->b_dev); 2932608Swnj ui = tmdinfo[unit]; 2942608Swnj /* 2952608Swnj * Record pre-transfer status (e.g. for TM_SENSE) 2962608Swnj */ 2972608Swnj sc = &tm_softc[unit]; 2982608Swnj addr = (struct device *)um->um_addr; 2992608Swnj addr->tmcs = (ui->ui_slave << 8); 3002471Swnj sc->sc_dsreg = addr->tmcs; 3012471Swnj sc->sc_erreg = addr->tmer; 3022471Swnj sc->sc_resid = addr->tmbc; 3032608Swnj /* 3042608Swnj * Default is that last command was NOT a write command; 3052608Swnj * if we do a write command we will notice this in tmintr(). 3062608Swnj */ 3072608Swnj sc->sc_lastiow = 1; 3082608Swnj if (sc->sc_openf < 0 || (addr->tmcs&TM_CUR) == 0) { 3092608Swnj /* 3102608Swnj * Have had a hard error on this (non-raw) tape, 3112608Swnj * or the tape unit is now unavailable (e.g. taken off 3122608Swnj * line). 3132608Swnj */ 3142608Swnj bp->b_flags |= B_ERROR; 3151919Swnj goto next; 3161919Swnj } 3172608Swnj /* 3182608Swnj * If operation is not a control operation, 3192608Swnj * check for boundary conditions. 3202608Swnj */ 3212608Swnj if (bp != &ctmbuf[unit]) { 3222608Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3232608Swnj bp->b_flags |= B_ERROR; 3242608Swnj bp->b_error = ENXIO; /* past EOF */ 3252608Swnj goto next; 3261919Swnj } 3272608Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 3282608Swnj bp->b_flags&B_READ) { 3292608Swnj bp->b_resid = bp->b_bcount; 3302608Swnj clrbuf(bp); /* at EOF */ 3312608Swnj goto next; 3322608Swnj } 3332608Swnj if ((bp->b_flags&B_READ) == 0) 3342608Swnj /* write sets EOF */ 3352608Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 3361919Swnj } 3372608Swnj /* 3382608Swnj * Set up the command, and then if this is a mt ioctl, 3392608Swnj * do the operation using, for TM_SFORW and TM_SREV, the specified 3402608Swnj * operation count. 3412608Swnj */ 3422608Swnj cmd = TM_IE | TM_GO | (ui->ui_slave << 8); 3432608Swnj if ((minor(bp->b_dev) & T_1600BPI) == 0) 3442608Swnj cmd |= TM_D800; 3452608Swnj if (bp == &ctmbuf[unit]) { 3462608Swnj if (bp->b_command == TM_SENSE) 3472608Swnj goto next; 3482608Swnj um->um_tab.b_active = 3492608Swnj bp->b_command == TM_REW ? SREW : SCOM; 3502608Swnj if (bp->b_command == TM_SFORW || bp->b_command == TM_SREV) 3512608Swnj addr->tmbc = bp->b_repcnt; 3522670Swnj goto dobpcmd; 3532608Swnj } 3542608Swnj /* 3552608Swnj * If the data transfer command is in the correct place, 3562608Swnj * set up all the registers except the csr, and give 3572608Swnj * control over to the UNIBUS adapter routines, to 3582608Swnj * wait for resources to start the i/o. 3592608Swnj */ 3602471Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 3612396Swnj addr->tmbc = -bp->b_bcount; 3621919Swnj if ((bp->b_flags&B_READ) == 0) { 3632471Swnj if (um->um_tab.b_errcnt) 3642608Swnj cmd |= TM_WIRG; 3651919Swnj else 3662608Swnj cmd |= TM_WCOM; 3671919Swnj } else 3682608Swnj cmd |= TM_RCOM; 3692471Swnj um->um_tab.b_active = SIO; 3702574Swnj um->um_cmd = cmd; 371*2928Swnj #ifdef notdef 3722670Swnj if (tmreverseop(sc->sc_lastcmd)) 3732670Swnj while (addr->tmer & TM_SDWN) 3742670Swnj tmgapsdcnt++; 3752670Swnj sc->sc_lastcmd = TM_RCOM; /* will serve */ 376*2928Swnj #endif 3772574Swnj ubago(ui); 3781919Swnj return; 3791919Swnj } 3802608Swnj /* 3812608Swnj * Block tape positioned incorrectly; 3822608Swnj * seek forwards or backwards to the correct spot. 3832608Swnj */ 3842471Swnj um->um_tab.b_active = SSEEK; 3851919Swnj if (blkno < dbtofsb(bp->b_blkno)) { 3862670Swnj bp->b_command = TM_SFORW; 3872396Swnj addr->tmbc = blkno - dbtofsb(bp->b_blkno); 3881919Swnj } else { 3892670Swnj bp->b_command = TM_SREV; 3902396Swnj addr->tmbc = dbtofsb(bp->b_blkno) - blkno; 3911919Swnj } 3922670Swnj dobpcmd: 393*2928Swnj #ifdef notdef 3942670Swnj if (tmreverseop(sc->sc_lastcmd) != tmreverseop(bp->b_command)) 3952670Swnj while (addr->tmer & TM_SDWN) 3962670Swnj tmgapsdcnt++; 3972670Swnj sc->sc_lastcmd = bp->b_command; 398*2928Swnj #endif 3992670Swnj addr->tmcs = (cmd | bp->b_command); 4001919Swnj return; 4011919Swnj 4021919Swnj next: 4032608Swnj /* 4042608Swnj * Done with this operation due to error or 4052608Swnj * the fact that it doesn't do anything. 4062608Swnj * Release UBA resources (if any), dequeue 4072608Swnj * the transfer and continue processing this slave. 4082608Swnj */ 4092608Swnj if (um->um_ubinfo) 4102617Swnj ubadone(um); 4112608Swnj um->um_tab.b_errcnt = 0; 4122608Swnj dp->b_actf = bp->av_forw; 4131919Swnj iodone(bp); 4141919Swnj goto loop; 4151919Swnj } 4161919Swnj 4172608Swnj /* 4182608Swnj * The UNIBUS resources we needed have been 4192608Swnj * allocated to us; start the device. 4202608Swnj */ 4212574Swnj tmdgo(um) 4222574Swnj register struct uba_minfo *um; 4231919Swnj { 4242574Swnj register struct device *addr = (struct device *)um->um_addr; 4252471Swnj 4262574Swnj addr->tmba = um->um_ubinfo; 4272574Swnj addr->tmcs = um->um_cmd | ((um->um_ubinfo >> 12) & 0x30); 4282396Swnj } 4292396Swnj 4302608Swnj /* 4312608Swnj * Tm interrupt routine. 4322608Swnj */ 4332471Swnj /*ARGSUSED*/ 4342630Swnj tmintr(tm11) 4352630Swnj int tm11; 4362396Swnj { 4372608Swnj struct buf *dp; 4381919Swnj register struct buf *bp; 4392630Swnj register struct uba_minfo *um = tmminfo[tm11]; 4402630Swnj register struct device *addr = (struct device *)tmdinfo[tm11]->ui_addr; 4412608Swnj register struct tm_softc *sc; 4422608Swnj int unit; 4431919Swnj register state; 4441919Swnj 4452608Swnj /* 4462608Swnj * If last command was a rewind, and tape is still 4472608Swnj * rewinding, wait for the rewind complete interrupt. 4482608Swnj */ 4492608Swnj if (um->um_tab.b_active == SREW) { 4502608Swnj um->um_tab.b_active = SCOM; 4512608Swnj if (addr->tmer&TM_RWS) 4522608Swnj return; 4531919Swnj } 4542608Swnj /* 4552608Swnj * An operation completed... record status 4562608Swnj */ 4572608Swnj if ((dp = um->um_tab.b_actf) == NULL) 4581919Swnj return; 4592608Swnj bp = dp->b_actf; 4602608Swnj unit = TMUNIT(bp->b_dev); 4612608Swnj sc = &tm_softc[unit]; 4622471Swnj sc->sc_dsreg = addr->tmcs; 4632471Swnj sc->sc_erreg = addr->tmer; 4642471Swnj sc->sc_resid = addr->tmbc; 4651919Swnj if ((bp->b_flags & B_READ) == 0) 4662608Swnj sc->sc_lastiow = 1; 4672471Swnj state = um->um_tab.b_active; 4682471Swnj um->um_tab.b_active = 0; 4692608Swnj /* 4702608Swnj * Check for errors. 4712608Swnj */ 4722608Swnj if (addr->tmcs&TM_ERR) { 4732608Swnj while (addr->tmer & TM_SDWN) 4741919Swnj ; /* await settle down */ 4752608Swnj /* 4762608Swnj * If we hit the end of the tape update our position. 4772608Swnj */ 4782608Swnj if (addr->tmer&TM_EOF) { 4792608Swnj tmseteof(bp); /* set blkno and nxrec */ 4802608Swnj state = SCOM; /* force completion */ 4812608Swnj /* 4822608Swnj * Stuff bc so it will be unstuffed correctly 4832608Swnj * later to get resid. 4842608Swnj */ 4852396Swnj addr->tmbc = -bp->b_bcount; 4862608Swnj goto opdone; 4871919Swnj } 4882608Swnj /* 4892608Swnj * If we were reading and the only error was that the 4902608Swnj * record was to long, then we don't consider this an error. 4912608Swnj */ 4922608Swnj if ((bp->b_flags&B_READ) && 4932608Swnj (addr->tmer&(TM_HARD|TM_SOFT)) == TM_RLE) 4942608Swnj goto ignoreerr; 4952608Swnj /* 4962608Swnj * If error is not hard, and this was an i/o operation 4972608Swnj * retry up to 8 times. 4982608Swnj */ 4992608Swnj if ((addr->tmer&TM_HARD)==0 && state==SIO) { 5002471Swnj if (++um->um_tab.b_errcnt < 7) { 5012471Swnj sc->sc_blkno++; 5022617Swnj ubadone(um); 5032608Swnj goto opcont; 5041919Swnj } 5052608Swnj } else 5062608Swnj /* 5072608Swnj * Hard or non-i/o errors on non-raw tape 5082608Swnj * cause it to close. 5092608Swnj */ 5102608Swnj if (sc->sc_openf>0 && bp != &rtmbuf[unit]) 5112608Swnj sc->sc_openf = -1; 5122608Swnj /* 5132608Swnj * Couldn't recover error 5142608Swnj */ 515*2928Swnj printf("te%d: hard error bn%d er=%b\n", minor(bp->b_dev)&03, 516*2928Swnj bp->b_blkno, sc->sc_erreg, TMEREG_BITS); 5171919Swnj bp->b_flags |= B_ERROR; 5182608Swnj goto opdone; 5191919Swnj } 5202608Swnj /* 5212608Swnj * Advance tape control FSM. 5222608Swnj */ 5232608Swnj ignoreerr: 5241919Swnj switch (state) { 5251919Swnj 5261919Swnj case SIO: 5272608Swnj /* 5282608Swnj * Read/write increments tape block number 5292608Swnj */ 5302471Swnj sc->sc_blkno++; 5312608Swnj goto opdone; 5321919Swnj 5331919Swnj case SCOM: 5342608Swnj /* 5352608Swnj * Unless special operation, op completed. 5362608Swnj */ 5372608Swnj if (bp != &ctmbuf[unit]) 5382608Swnj goto opdone; 5392608Swnj /* 5402608Swnj * Operation on block device... 5412608Swnj * iterate operations which don't repeat 5422608Swnj * for themselves in the hardware; for forward/ 5432608Swnj * backward space record update the current position. 5442608Swnj */ 5452608Swnj switch (bp->b_command) { 5461919Swnj 5472608Swnj case TM_SFORW: 5482608Swnj sc->sc_blkno -= bp->b_repcnt; 5492608Swnj goto opdone; 5501919Swnj 5512608Swnj case TM_SREV: 5522608Swnj sc->sc_blkno += bp->b_repcnt; 5532608Swnj goto opdone; 5542608Swnj 5552608Swnj default: 5562608Swnj if (++bp->b_repcnt < 0) 5572608Swnj goto opcont; 5582608Swnj goto opdone; 5591919Swnj } 5601919Swnj 5611919Swnj case SSEEK: 5622471Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 5632608Swnj goto opcont; 5641919Swnj 5651919Swnj default: 5662608Swnj panic("tmintr"); 5672608Swnj } 5682608Swnj opdone: 5692608Swnj /* 5702608Swnj * Reset error count and remove 5712608Swnj * from device queue. 5722608Swnj */ 5732608Swnj um->um_tab.b_errcnt = 0; 5742608Swnj dp->b_actf = bp->av_forw; 5752608Swnj bp->b_resid = -addr->tmbc; 5762617Swnj ubadone(um); 5772608Swnj iodone(bp); 5782608Swnj /* 5792608Swnj * Circulate slave to end of controller 5802608Swnj * queue to give other slaves a chance. 5812608Swnj */ 5822608Swnj um->um_tab.b_actf = dp->b_forw; 5832608Swnj if (dp->b_actf) { 5842608Swnj dp->b_forw = NULL; 5852608Swnj if (um->um_tab.b_actf == NULL) 5862608Swnj um->um_tab.b_actf = dp; 5872608Swnj else 5882608Swnj um->um_tab.b_actl->b_forw = dp; 5892608Swnj um->um_tab.b_actl = dp; 5902608Swnj } 5912608Swnj if (um->um_tab.b_actf == 0) 5921919Swnj return; 5932608Swnj opcont: 5942608Swnj tmstart(um); 5951919Swnj } 5961919Swnj 5971919Swnj tmseteof(bp) 5981919Swnj register struct buf *bp; 5991919Swnj { 6002608Swnj register int unit = TMUNIT(bp->b_dev); 6012396Swnj register struct device *addr = 6022608Swnj (struct device *)tmdinfo[unit]->ui_addr; 6032608Swnj register struct tm_softc *sc = &tm_softc[unit]; 6041919Swnj 6052608Swnj if (bp == &ctmbuf[unit]) { 6062471Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 6071919Swnj /* reversing */ 6082471Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) - addr->tmbc; 6092471Swnj sc->sc_blkno = sc->sc_nxrec; 6101919Swnj } else { 6111919Swnj /* spacing forward */ 6122471Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) + addr->tmbc; 6132471Swnj sc->sc_nxrec = sc->sc_blkno - 1; 6141919Swnj } 6151919Swnj return; 6161919Swnj } 6171919Swnj /* eof on read */ 6182471Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 6191919Swnj } 6201919Swnj 6211919Swnj tmread(dev) 6222608Swnj dev_t dev; 6231919Swnj { 6241919Swnj 6251919Swnj tmphys(dev); 6262608Swnj physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_READ, minphys); 6271919Swnj } 6281919Swnj 6291919Swnj tmwrite(dev) 6302608Swnj dev_t dev; 6311919Swnj { 6321919Swnj 6331919Swnj tmphys(dev); 6342608Swnj physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_WRITE, minphys); 6351919Swnj } 6361919Swnj 6371919Swnj tmphys(dev) 6382608Swnj dev_t dev; 6391919Swnj { 6401919Swnj register daddr_t a; 6412608Swnj register struct tm_softc *sc = &tm_softc[TMUNIT(dev)]; 6421919Swnj 6431919Swnj a = dbtofsb(u.u_offset >> 9); 6442471Swnj sc->sc_blkno = a; 6452471Swnj sc->sc_nxrec = a + 1; 6461919Swnj } 6471919Swnj 6482608Swnj tmreset(uban) 6492608Swnj int uban; 6502608Swnj { 6512608Swnj register struct uba_minfo *um; 6522630Swnj register tm11, unit; 6532608Swnj register struct uba_dinfo *ui; 6542608Swnj register struct buf *dp; 6552608Swnj 6562630Swnj for (tm11 = 0; tm11 < NTM; tm11++) { 6572630Swnj if ((um = tmminfo[tm11]) == 0 || um->um_alive == 0 || 6582608Swnj um->um_ubanum != uban) 6592608Swnj continue; 660*2928Swnj printf(" tm%d", tm11); 6612608Swnj um->um_tab.b_active = 0; 6622608Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 6632608Swnj if (um->um_ubinfo) { 6642608Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 6652617Swnj ubadone(um); 6662608Swnj } 6672608Swnj ((struct device *)(um->um_addr))->tmcs = TM_DCLR; 6682630Swnj for (unit = 0; unit < NTE; unit++) { 6692608Swnj if ((ui = tmdinfo[unit]) == 0) 6702608Swnj continue; 6712608Swnj if (ui->ui_alive == 0) 6722608Swnj continue; 6732608Swnj dp = &tmutab[unit]; 6742608Swnj dp->b_active = 0; 6752608Swnj dp->b_forw = 0; 6762608Swnj if (um->um_tab.b_actf == NULL) 6772608Swnj um->um_tab.b_actf = dp; 6782608Swnj else 6792608Swnj um->um_tab.b_actl->b_forw = dp; 6802608Swnj um->um_tab.b_actl = dp; 6812608Swnj tm_softc[unit].sc_openf = -1; 6822608Swnj } 6832608Swnj tmstart(um); 6842608Swnj } 6852608Swnj } 6862608Swnj 6871919Swnj /*ARGSUSED*/ 6881919Swnj tmioctl(dev, cmd, addr, flag) 6891919Swnj caddr_t addr; 6901919Swnj dev_t dev; 6911919Swnj { 6922608Swnj int unit = TMUNIT(dev); 6932608Swnj register struct tm_softc *sc = &tm_softc[unit]; 6942608Swnj register struct buf *bp = &ctmbuf[unit]; 6951919Swnj register callcount; 6961919Swnj int fcount; 6971919Swnj struct mtop mtop; 6981919Swnj struct mtget mtget; 6991919Swnj /* we depend of the values and order of the MT codes here */ 7002608Swnj static tmops[] = 7012608Swnj {TM_WEOF,TM_SFORW,TM_SREV,TM_SFORW,TM_SREV,TM_REW,TM_OFFL,TM_SENSE}; 7021919Swnj 7032608Swnj switch (cmd) { 7041919Swnj case MTIOCTOP: /* tape operation */ 7051919Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 7061919Swnj u.u_error = EFAULT; 7071919Swnj return; 7081919Swnj } 7091919Swnj switch(mtop.mt_op) { 7102608Swnj case MTWEOF: 7111919Swnj callcount = mtop.mt_count; 7122608Swnj fcount = 1; 7132608Swnj break; 7142608Swnj case MTFSF: case MTBSF: 7152608Swnj callcount = mtop.mt_count; 7161919Swnj fcount = INF; 7171919Swnj break; 7181919Swnj case MTFSR: case MTBSR: 7191919Swnj callcount = 1; 7201919Swnj fcount = mtop.mt_count; 7211919Swnj break; 7222324Skre case MTREW: case MTOFFL: case MTNOP: 7231919Swnj callcount = 1; 7241919Swnj fcount = 1; 7251919Swnj break; 7261919Swnj default: 7271919Swnj u.u_error = ENXIO; 7281919Swnj return; 7291919Swnj } 7302608Swnj if (callcount <= 0 || fcount <= 0) { 7311919Swnj u.u_error = ENXIO; 7322608Swnj return; 7332608Swnj } 7342608Swnj while (--callcount >= 0) { 7352574Swnj tmcommand(dev, tmops[mtop.mt_op], fcount); 7361919Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 7372608Swnj bp->b_resid) { 7381919Swnj u.u_error = EIO; 7391919Swnj break; 7401919Swnj } 7412608Swnj if ((bp->b_flags&B_ERROR) || sc->sc_erreg&TM_BOT) 7421919Swnj break; 7431919Swnj } 7442608Swnj geterror(bp); 7451919Swnj return; 7461919Swnj case MTIOCGET: 7472471Swnj mtget.mt_dsreg = sc->sc_dsreg; 7482471Swnj mtget.mt_erreg = sc->sc_erreg; 7492471Swnj mtget.mt_resid = sc->sc_resid; 7501919Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 7511919Swnj u.u_error = EFAULT; 7521919Swnj return; 7531919Swnj default: 7541919Swnj u.u_error = ENXIO; 7551919Swnj } 7561919Swnj } 7571919Swnj 7581919Swnj #define DBSIZE 20 7591919Swnj 7602363Swnj tmdump() 7612363Swnj { 7622396Swnj register struct uba_dinfo *ui; 7632396Swnj register struct uba_regs *up; 7642396Swnj register struct device *addr; 7652426Skre int blk, num; 7662426Skre int start; 7671919Swnj 7682426Skre start = 0; 7692426Skre num = maxfree; 7702426Skre #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 7712887Swnj if (tmdinfo[0] == 0) 7722887Swnj return (ENXIO); 7732458Swnj ui = phys(tmdinfo[0], struct uba_dinfo *); 7742396Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 7752396Swnj #if VAX780 7762396Swnj if (cpu == VAX_780) 7772396Swnj ubainit(up); 7781919Swnj #endif 7792324Skre DELAY(1000000); 7802396Swnj addr = (struct device *)ui->ui_physaddr; 7812396Swnj tmwait(addr); 7822608Swnj addr->tmcs = TM_DCLR | TM_GO; 7831919Swnj while (num > 0) { 7841919Swnj blk = num > DBSIZE ? DBSIZE : num; 7852396Swnj tmdwrite(start, blk, addr, up); 7861919Swnj start += blk; 7871919Swnj num -= blk; 7881919Swnj } 7892426Skre tmeof(addr); 7902426Skre tmeof(addr); 7912426Skre tmwait(addr); 7922887Swnj if (addr->tmcs&TM_ERR) 7932887Swnj return (EIO); 7942608Swnj addr->tmcs = TM_REW | TM_GO; 7952471Swnj tmwait(addr); 7962363Swnj return (0); 7971919Swnj } 7981919Swnj 7992608Swnj tmdwrite(dbuf, num, addr, up) 8002608Swnj register dbuf, num; 8012396Swnj register struct device *addr; 8022396Swnj struct uba_regs *up; 8031919Swnj { 8042396Swnj register struct pte *io; 8052396Swnj register int npf; 8061928Swnj 8072396Swnj tmwait(addr); 8082396Swnj io = up->uba_map; 8091919Swnj npf = num+1; 8101928Swnj while (--npf != 0) 8112608Swnj *(int *)io++ = (dbuf++ | (1<<UBA_DPSHIFT) | UBA_MRV); 8122396Swnj *(int *)io = 0; 8132396Swnj addr->tmbc = -(num*NBPG); 8142396Swnj addr->tmba = 0; 8152608Swnj addr->tmcs = TM_WCOM | TM_GO; 8161919Swnj } 8171919Swnj 8182396Swnj tmwait(addr) 8192396Swnj register struct device *addr; 8201919Swnj { 8211928Swnj register s; 8221919Swnj 8231919Swnj do 8242396Swnj s = addr->tmcs; 8252608Swnj while ((s & TM_CUR) == 0); 8261919Swnj } 8271919Swnj 8282396Swnj tmeof(addr) 8292396Swnj struct device *addr; 8301919Swnj { 8311919Swnj 8322396Swnj tmwait(addr); 8332608Swnj addr->tmcs = TM_WEOF | TM_GO; 8341919Swnj } 8351919Swnj #endif 836