xref: /csrg-svn/sys/vax/uba/tm.c (revision 2887)
1*2887Swnj /*	tm.c	4.21	03/03/81	*/
21919Swnj 
32709Swnj #include "te.h"
42630Swnj #if NTM > 0
52670Swnj int	tmgapsdcnt;		/* DEBUG */
61919Swnj /*
72630Swnj  * TM11/TE10 tape driver
82471Swnj  *
92608Swnj  * THIS DRIVER HAS NOT BEEN TESTED WITH MORE THAN ONE TRANSPORT.
101919Swnj  */
112471Swnj #define	DELAY(N)		{ register int d = N; while (--d > 0); }
121919Swnj #include "../h/param.h"
131919Swnj #include "../h/buf.h"
141919Swnj #include "../h/dir.h"
151919Swnj #include "../h/conf.h"
161919Swnj #include "../h/user.h"
171919Swnj #include "../h/file.h"
181919Swnj #include "../h/map.h"
191919Swnj #include "../h/pte.h"
202574Swnj #include "../h/vm.h"
211919Swnj #include "../h/uba.h"
221919Swnj #include "../h/mtio.h"
231919Swnj #include "../h/ioctl.h"
242363Swnj #include "../h/cmap.h"
252396Swnj #include "../h/cpu.h"
261919Swnj 
272396Swnj #include "../h/tmreg.h"
281919Swnj 
292630Swnj struct	buf	ctmbuf[NTE];
302630Swnj struct	buf	rtmbuf[NTE];
311919Swnj 
322608Swnj int	tmprobe(), tmslave(), tmattach(), tmdgo(), tmintr();
332630Swnj struct	uba_minfo *tmminfo[NTM];
342630Swnj struct	uba_dinfo *tmdinfo[NTE];
352630Swnj struct	buf tmutab[NTE];
362608Swnj #ifdef notyet
372630Swnj struct	uba_dinfo *tmip[NTM][4];
382608Swnj #endif
392458Swnj u_short	tmstd[] = { 0772520, 0 };
402396Swnj struct	uba_driver tmdriver =
412630Swnj  { tmprobe, tmslave, tmattach, tmdgo, tmstd, "te", tmdinfo, "tm", tmminfo, 0 };
421919Swnj 
431919Swnj /* bits in minor device */
442608Swnj #define	TMUNIT(dev)	(minor(dev)&03)
451919Swnj #define	T_NOREWIND	04
461919Swnj #define	T_1600BPI	08
471919Swnj 
481919Swnj #define	INF	(daddr_t)1000000L
491919Swnj 
502608Swnj /*
512608Swnj  * Software state per tape transport.
522608Swnj  */
532471Swnj struct	tm_softc {
542608Swnj 	char	sc_openf;	/* lock against multiple opens */
552608Swnj 	char	sc_lastiow;	/* last op was a write */
562608Swnj 	daddr_t	sc_blkno;	/* block number, for block device tape */
572608Swnj 	daddr_t	sc_nxrec;	/* desired block position */
582608Swnj 	u_short	sc_erreg;	/* copy of last erreg */
592608Swnj 	u_short	sc_dsreg;	/* copy of last dsreg */
602608Swnj 	short	sc_resid;	/* copy of last bc */
612670Swnj 	short	sc_lastcmd;	/* last command to handle direction changes */
622630Swnj } tm_softc[NTM];
631919Swnj 
642608Swnj /*
652608Swnj  * States for um->um_tab.b_active, the
662608Swnj  * per controller state flag.
672608Swnj  */
681919Swnj #define	SSEEK	1		/* seeking */
691919Swnj #define	SIO	2		/* doing seq i/o */
701919Swnj #define	SCOM	3		/* sending control command */
712608Swnj #define	SREW	4		/* sending a drive rewind */
721919Swnj 
732608Swnj /* WE CURRENTLY HANDLE REWINDS PRIMITIVELY, BUSYING OUT THE CONTROLLER */
742608Swnj /* DURING THE REWIND... IF WE EVER GET TWO TRANSPORTS, WE CAN DEBUG MORE */
752608Swnj /* SOPHISTICATED LOGIC... THIS SIMPLE CODE AT LEAST MAY WORK. */
761919Swnj 
772426Skre /*
782426Skre  * Determine if there is a controller for
792426Skre  * a tm at address reg.  Our goal is to make the
802426Skre  * device interrupt.
812426Skre  */
822608Swnj tmprobe(reg)
832396Swnj 	caddr_t reg;
842396Swnj {
852458Swnj 	register int br, cvec;
862426Skre 
872608Swnj #ifdef lint
882608Swnj 	br = 0; br = cvec; cvec = br;
892608Swnj #endif
902608Swnj 	((struct device *)reg)->tmcs = TM_IE;
912396Swnj 	/*
922630Swnj 	 * If this is a tm11, it ought to have interrupted
932396Swnj 	 * by now, if it isn't (ie: it is a ts04) then we just
942458Swnj 	 * hope that it didn't interrupt, so autoconf will ignore it.
952458Swnj 	 * Just in case, we will reference one
962396Swnj 	 * of the more distant registers, and hope for a machine
972458Swnj 	 * check, or similar disaster if this is a ts.
982471Swnj 	 *
992471Swnj 	 * Note: on an 11/780, badaddr will just generate
1002471Swnj 	 * a uba error for a ts; but our caller will notice that
1012471Swnj 	 * so we won't check for it.
1022396Swnj 	 */
1032396Swnj 	if (badaddr(&((struct device *)reg)->tmrd, 2))
1042458Swnj 		return (0);
1052458Swnj 	return (1);
1062396Swnj }
1072396Swnj 
1082608Swnj /*
1092608Swnj  * Due to a design flaw, we cannot ascertain if the tape
1102608Swnj  * exists or not unless it is on line - ie: unless a tape is
1112608Swnj  * mounted. This is too servere a restriction to bear,
1122608Swnj  * so all units are assumed to exist.
1132608Swnj  */
1142608Swnj /*ARGSUSED*/
1152574Swnj tmslave(ui, reg)
1162396Swnj 	struct uba_dinfo *ui;
1172396Swnj 	caddr_t reg;
1182396Swnj {
1192458Swnj 
1202458Swnj 	return (1);
1212396Swnj }
1222396Swnj 
1232608Swnj /*
1242608Swnj  * Record attachment of the unit to the controller port.
1252608Swnj  */
1262608Swnj /*ARGSUSED*/
1272608Swnj tmattach(ui)
1282608Swnj 	struct uba_dinfo *ui;
1292608Swnj {
1302608Swnj 
1312608Swnj #ifdef notyet
1322608Swnj 	tmip[ui->ui_ctlr][ui->ui_slave] = ui;
1332608Swnj #endif
1342608Swnj }
1352608Swnj 
1362608Swnj /*
1372608Swnj  * Open the device.  Tapes are unique open
1382608Swnj  * devices, so we refuse if it is already open.
1392608Swnj  * We also check that a tape is available, and
1402608Swnj  * don't block waiting here.
1412608Swnj  */
1421919Swnj tmopen(dev, flag)
1431919Swnj 	dev_t dev;
1441919Swnj 	int flag;
1451919Swnj {
1462608Swnj 	register int unit;
1472396Swnj 	register struct uba_dinfo *ui;
1482608Swnj 	register struct tm_softc *sc;
1491919Swnj 
1502608Swnj 	unit = TMUNIT(dev);
1512630Swnj 	if (unit>=NTE || (sc = &tm_softc[unit])->sc_openf ||
1522608Swnj 	    (ui = tmdinfo[unit]) == 0 || ui->ui_alive == 0) {
1532608Swnj 		u.u_error = ENXIO;
1541919Swnj 		return;
1551919Swnj 	}
1562608Swnj 	tmcommand(dev, TM_SENSE, 1);
1572608Swnj 	if ((sc->sc_erreg&(TM_SELR|TM_TUR)) != (TM_SELR|TM_TUR)) {
1582608Swnj 		uprintf("tape not online\n");
1592471Swnj 		u.u_error = EIO;
1602608Swnj 		return;
1611919Swnj 	}
1622608Swnj 	if ((flag&(FREAD|FWRITE)) == FWRITE && sc->sc_erreg&TM_WRL) {
1632608Swnj 		uprintf("tape write protected\n");
1642608Swnj 		u.u_error = EIO;
1651919Swnj 		return;
1661919Swnj 	}
1672608Swnj 	sc->sc_openf = 1;
1682471Swnj 	sc->sc_blkno = (daddr_t)0;
1692471Swnj 	sc->sc_nxrec = INF;
1702608Swnj 	sc->sc_lastiow = 0;
1712471Swnj 	sc->sc_openf = 1;
1722608Swnj 	return;
1731919Swnj }
1741919Swnj 
1752608Swnj /*
1762608Swnj  * Close tape device.
1772608Swnj  *
1782608Swnj  * If tape was open for writing or last operation was
1792608Swnj  * a write, then write two EOF's and backspace over the last one.
1802608Swnj  * Unless this is a non-rewinding special file, rewind the tape.
1812608Swnj  * Make the tape available to others.
1822608Swnj  */
1831919Swnj tmclose(dev, flag)
1841919Swnj 	register dev_t dev;
1851919Swnj 	register flag;
1861919Swnj {
1872608Swnj 	register struct tm_softc *sc = &tm_softc[TMUNIT(dev)];
1881919Swnj 
1892608Swnj 	if (flag == FWRITE || (flag&FWRITE) && sc->sc_lastiow) {
1902608Swnj 		tmcommand(dev, TM_WEOF, 1);
1912608Swnj 		tmcommand(dev, TM_WEOF, 1);
1922608Swnj 		tmcommand(dev, TM_SREV, 1);
1931919Swnj 	}
1941919Swnj 	if ((minor(dev)&T_NOREWIND) == 0)
1952608Swnj 		tmcommand(dev, TM_REW, 1);
1962471Swnj 	sc->sc_openf = 0;
1971919Swnj }
1981919Swnj 
1992608Swnj /*
2002608Swnj  * Execute a command on the tape drive
2012608Swnj  * a specified number of times.
2022608Swnj  */
2032574Swnj tmcommand(dev, com, count)
2041919Swnj 	dev_t dev;
2051919Swnj 	int com, count;
2061919Swnj {
2071919Swnj 	register struct buf *bp;
2081919Swnj 
2092608Swnj 	bp = &ctmbuf[TMUNIT(dev)];
2101919Swnj 	(void) spl5();
2111919Swnj 	while (bp->b_flags&B_BUSY) {
2121919Swnj 		bp->b_flags |= B_WANTED;
2131919Swnj 		sleep((caddr_t)bp, PRIBIO);
2141919Swnj 	}
2151919Swnj 	bp->b_flags = B_BUSY|B_READ;
2161919Swnj 	(void) spl0();
2171919Swnj 	bp->b_dev = dev;
2181919Swnj 	bp->b_repcnt = -count;
2191919Swnj 	bp->b_command = com;
2201919Swnj 	bp->b_blkno = 0;
2211919Swnj 	tmstrategy(bp);
2221919Swnj 	iowait(bp);
2231919Swnj 	if (bp->b_flags&B_WANTED)
2241919Swnj 		wakeup((caddr_t)bp);
2251919Swnj 	bp->b_flags &= B_ERROR;
2261919Swnj }
2271919Swnj 
2282608Swnj /*
2292608Swnj  * Decipher a tape operation and do what is needed
2302608Swnj  * to see that it happens.
2312608Swnj  */
2321919Swnj tmstrategy(bp)
2331919Swnj 	register struct buf *bp;
2341919Swnj {
2352608Swnj 	int unit = TMUNIT(bp->b_dev);
2362608Swnj 	register struct uba_minfo *um;
2372608Swnj 	register struct buf *dp;
2382608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
2391919Swnj 
2402608Swnj 	/*
2412608Swnj 	 * Put transfer at end of unit queue
2422608Swnj 	 */
2432608Swnj 	dp = &tmutab[unit];
2441919Swnj 	bp->av_forw = NULL;
2451919Swnj 	(void) spl5();
2462608Swnj 	if (dp->b_actf == NULL) {
2472608Swnj 		dp->b_actf = bp;
2482608Swnj 		/*
2492608Swnj 		 * Transport not already active...
2502608Swnj 		 * put at end of controller queue.
2512608Swnj 		 */
2522608Swnj 		dp->b_forw = NULL;
2532608Swnj 		um = tmdinfo[unit]->ui_mi;
2542608Swnj 		if (um->um_tab.b_actf == NULL)
2552608Swnj 			um->um_tab.b_actf = dp;
2562608Swnj 		else
2572608Swnj 			um->um_tab.b_actl->b_forw = dp;
2582608Swnj 		um->um_tab.b_actl = dp;
2592608Swnj 	} else
2602608Swnj 		dp->b_actl->av_forw = bp;
2612608Swnj 	dp->b_actl = bp;
2622608Swnj 	/*
2632608Swnj 	 * If the controller is not busy, get
2642608Swnj 	 * it going.
2652608Swnj 	 */
2662608Swnj 	if (um->um_tab.b_active == 0)
2672608Swnj 		tmstart(um);
2681919Swnj 	(void) spl0();
2691919Swnj }
2701919Swnj 
2712608Swnj /*
2722608Swnj  * Start activity on a tm controller.
2732608Swnj  */
2742608Swnj tmstart(um)
2752608Swnj 	register struct uba_minfo *um;
2761919Swnj {
2772608Swnj 	register struct buf *bp, *dp;
2782608Swnj 	register struct device *addr = (struct device *)um->um_addr;
2792608Swnj 	register struct tm_softc *sc;
2802396Swnj 	register struct uba_dinfo *ui;
2812608Swnj 	int unit, cmd;
2822471Swnj 	daddr_t blkno;
2831919Swnj 
2842608Swnj 	/*
2852608Swnj 	 * Look for an idle transport on the controller.
2862608Swnj 	 */
2871919Swnj loop:
2882608Swnj 	if ((dp = um->um_tab.b_actf) == NULL)
2891919Swnj 		return;
2902608Swnj 	if ((bp = dp->b_actf) == NULL) {
2912608Swnj 		um->um_tab.b_actf = dp->b_forw;
2922608Swnj 		goto loop;
2932608Swnj 	}
2942608Swnj 	unit = TMUNIT(bp->b_dev);
2952608Swnj 	ui = tmdinfo[unit];
2962608Swnj 	/*
2972608Swnj 	 * Record pre-transfer status (e.g. for TM_SENSE)
2982608Swnj 	 */
2992608Swnj 	sc = &tm_softc[unit];
3002608Swnj 	addr = (struct device *)um->um_addr;
3012608Swnj 	addr->tmcs = (ui->ui_slave << 8);
3022471Swnj 	sc->sc_dsreg = addr->tmcs;
3032471Swnj 	sc->sc_erreg = addr->tmer;
3042471Swnj 	sc->sc_resid = addr->tmbc;
3052608Swnj 	/*
3062608Swnj 	 * Default is that last command was NOT a write command;
3072608Swnj 	 * if we do a write command we will notice this in tmintr().
3082608Swnj 	 */
3092608Swnj 	sc->sc_lastiow = 1;
3102608Swnj 	if (sc->sc_openf < 0 || (addr->tmcs&TM_CUR) == 0) {
3112608Swnj 		/*
3122608Swnj 		 * Have had a hard error on this (non-raw) tape,
3132608Swnj 		 * or the tape unit is now unavailable (e.g. taken off
3142608Swnj 		 * line).
3152608Swnj 		 */
3162608Swnj 		bp->b_flags |= B_ERROR;
3171919Swnj 		goto next;
3181919Swnj 	}
3192608Swnj 	/*
3202608Swnj 	 * If operation is not a control operation,
3212608Swnj 	 * check for boundary conditions.
3222608Swnj 	 */
3232608Swnj 	if (bp != &ctmbuf[unit]) {
3242608Swnj 		if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) {
3252608Swnj 			bp->b_flags |= B_ERROR;
3262608Swnj 			bp->b_error = ENXIO;		/* past EOF */
3272608Swnj 			goto next;
3281919Swnj 		}
3292608Swnj 		if (dbtofsb(bp->b_blkno) == sc->sc_nxrec &&
3302608Swnj 		    bp->b_flags&B_READ) {
3312608Swnj 			bp->b_resid = bp->b_bcount;
3322608Swnj 			clrbuf(bp);			/* at EOF */
3332608Swnj 			goto next;
3342608Swnj 		}
3352608Swnj 		if ((bp->b_flags&B_READ) == 0)
3362608Swnj 			/* write sets EOF */
3372608Swnj 			sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1;
3381919Swnj 	}
3392608Swnj 	/*
3402608Swnj 	 * Set up the command, and then if this is a mt ioctl,
3412608Swnj 	 * do the operation using, for TM_SFORW and TM_SREV, the specified
3422608Swnj 	 * operation count.
3432608Swnj 	 */
3442608Swnj 	cmd = TM_IE | TM_GO | (ui->ui_slave << 8);
3452608Swnj 	if ((minor(bp->b_dev) & T_1600BPI) == 0)
3462608Swnj 		cmd |= TM_D800;
3472608Swnj 	if (bp == &ctmbuf[unit]) {
3482608Swnj 		if (bp->b_command == TM_SENSE)
3492608Swnj 			goto next;
3502608Swnj 		um->um_tab.b_active =
3512608Swnj 		    bp->b_command == TM_REW ? SREW : SCOM;
3522608Swnj 		if (bp->b_command == TM_SFORW || bp->b_command == TM_SREV)
3532608Swnj 			addr->tmbc = bp->b_repcnt;
3542670Swnj 		goto dobpcmd;
3552608Swnj 	}
3562608Swnj 	/*
3572608Swnj 	 * If the data transfer command is in the correct place,
3582608Swnj 	 * set up all the registers except the csr, and give
3592608Swnj 	 * control over to the UNIBUS adapter routines, to
3602608Swnj 	 * wait for resources to start the i/o.
3612608Swnj 	 */
3622471Swnj 	if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) {
3632396Swnj 		addr->tmbc = -bp->b_bcount;
3641919Swnj 		if ((bp->b_flags&B_READ) == 0) {
3652471Swnj 			if (um->um_tab.b_errcnt)
3662608Swnj 				cmd |= TM_WIRG;
3671919Swnj 			else
3682608Swnj 				cmd |= TM_WCOM;
3691919Swnj 		} else
3702608Swnj 			cmd |= TM_RCOM;
3712471Swnj 		um->um_tab.b_active = SIO;
3722574Swnj 		um->um_cmd = cmd;
3732670Swnj /*
3742670Swnj 		if (tmreverseop(sc->sc_lastcmd))
3752670Swnj 			while (addr->tmer & TM_SDWN)
3762670Swnj 				tmgapsdcnt++;
3772670Swnj */
3782670Swnj 		sc->sc_lastcmd = TM_RCOM;		/* will serve */
3792574Swnj 		ubago(ui);
3801919Swnj 		return;
3811919Swnj 	}
3822608Swnj 	/*
3832608Swnj 	 * Block tape positioned incorrectly;
3842608Swnj 	 * seek forwards or backwards to the correct spot.
3852608Swnj 	 */
3862471Swnj 	um->um_tab.b_active = SSEEK;
3871919Swnj 	if (blkno < dbtofsb(bp->b_blkno)) {
3882670Swnj 		bp->b_command = TM_SFORW;
3892396Swnj 		addr->tmbc = blkno - dbtofsb(bp->b_blkno);
3901919Swnj 	} else {
3912670Swnj 		bp->b_command = TM_SREV;
3922396Swnj 		addr->tmbc = dbtofsb(bp->b_blkno) - blkno;
3931919Swnj 	}
3942670Swnj dobpcmd:
3952670Swnj /*
3962670Swnj 	if (tmreverseop(sc->sc_lastcmd) != tmreverseop(bp->b_command))
3972670Swnj 		while (addr->tmer & TM_SDWN)
3982670Swnj 			tmgapsdcnt++;
3992670Swnj */
4002670Swnj 	sc->sc_lastcmd = bp->b_command;
4012670Swnj 	addr->tmcs = (cmd | bp->b_command);
4021919Swnj 	return;
4031919Swnj 
4041919Swnj next:
4052608Swnj 	/*
4062608Swnj 	 * Done with this operation due to error or
4072608Swnj 	 * the fact that it doesn't do anything.
4082608Swnj 	 * Release UBA resources (if any), dequeue
4092608Swnj 	 * the transfer and continue processing this slave.
4102608Swnj 	 */
4112608Swnj 	if (um->um_ubinfo)
4122617Swnj 		ubadone(um);
4132608Swnj 	um->um_tab.b_errcnt = 0;
4142608Swnj 	dp->b_actf = bp->av_forw;
4151919Swnj 	iodone(bp);
4161919Swnj 	goto loop;
4171919Swnj }
4181919Swnj 
4192608Swnj /*
4202608Swnj  * The UNIBUS resources we needed have been
4212608Swnj  * allocated to us; start the device.
4222608Swnj  */
4232574Swnj tmdgo(um)
4242574Swnj 	register struct uba_minfo *um;
4251919Swnj {
4262574Swnj 	register struct device *addr = (struct device *)um->um_addr;
4272471Swnj 
4282574Swnj 	addr->tmba = um->um_ubinfo;
4292574Swnj 	addr->tmcs = um->um_cmd | ((um->um_ubinfo >> 12) & 0x30);
4302396Swnj }
4312396Swnj 
4322608Swnj /*
4332608Swnj  * Tm interrupt routine.
4342608Swnj  */
4352471Swnj /*ARGSUSED*/
4362630Swnj tmintr(tm11)
4372630Swnj 	int tm11;
4382396Swnj {
4392608Swnj 	struct buf *dp;
4401919Swnj 	register struct buf *bp;
4412630Swnj 	register struct uba_minfo *um = tmminfo[tm11];
4422630Swnj 	register struct device *addr = (struct device *)tmdinfo[tm11]->ui_addr;
4432608Swnj 	register struct tm_softc *sc;
4442608Swnj 	int unit;
4451919Swnj 	register state;
4461919Swnj 
4472608Swnj 	/*
4482608Swnj 	 * If last command was a rewind, and tape is still
4492608Swnj 	 * rewinding, wait for the rewind complete interrupt.
4502608Swnj 	 */
4512608Swnj 	if (um->um_tab.b_active == SREW) {
4522608Swnj 		um->um_tab.b_active = SCOM;
4532608Swnj 		if (addr->tmer&TM_RWS)
4542608Swnj 			return;
4551919Swnj 	}
4562608Swnj 	/*
4572608Swnj 	 * An operation completed... record status
4582608Swnj 	 */
4592608Swnj 	if ((dp = um->um_tab.b_actf) == NULL)
4601919Swnj 		return;
4612608Swnj 	bp = dp->b_actf;
4622608Swnj 	unit = TMUNIT(bp->b_dev);
4632608Swnj 	sc = &tm_softc[unit];
4642471Swnj 	sc->sc_dsreg = addr->tmcs;
4652471Swnj 	sc->sc_erreg = addr->tmer;
4662471Swnj 	sc->sc_resid = addr->tmbc;
4671919Swnj 	if ((bp->b_flags & B_READ) == 0)
4682608Swnj 		sc->sc_lastiow = 1;
4692471Swnj 	state = um->um_tab.b_active;
4702471Swnj 	um->um_tab.b_active = 0;
4712608Swnj 	/*
4722608Swnj 	 * Check for errors.
4732608Swnj 	 */
4742608Swnj 	if (addr->tmcs&TM_ERR) {
4752608Swnj 		while (addr->tmer & TM_SDWN)
4761919Swnj 			;			/* await settle down */
4772608Swnj 		/*
4782608Swnj 		 * If we hit the end of the tape update our position.
4792608Swnj 		 */
4802608Swnj 		if (addr->tmer&TM_EOF) {
4812608Swnj 			tmseteof(bp);		/* set blkno and nxrec */
4822608Swnj 			state = SCOM;		/* force completion */
4832608Swnj 			/*
4842608Swnj 			 * Stuff bc so it will be unstuffed correctly
4852608Swnj 			 * later to get resid.
4862608Swnj 			 */
4872396Swnj 			addr->tmbc = -bp->b_bcount;
4882608Swnj 			goto opdone;
4891919Swnj 		}
4902608Swnj 		/*
4912608Swnj 		 * If we were reading and the only error was that the
4922608Swnj 		 * record was to long, then we don't consider this an error.
4932608Swnj 		 */
4942608Swnj 		if ((bp->b_flags&B_READ) &&
4952608Swnj 		    (addr->tmer&(TM_HARD|TM_SOFT)) == TM_RLE)
4962608Swnj 			goto ignoreerr;
4972608Swnj 		/*
4982608Swnj 		 * If error is not hard, and this was an i/o operation
4992608Swnj 		 * retry up to 8 times.
5002608Swnj 		 */
5012608Swnj 		if ((addr->tmer&TM_HARD)==0 && state==SIO) {
5022471Swnj 			if (++um->um_tab.b_errcnt < 7) {
5032608Swnj /* SHOULD CHECK THAT RECOVERY WORKS IN THIS CASE */
5042608Swnj /* AND THEN ONLY PRINT IF errcnt==7 */
5052608Swnj 				if((addr->tmer&TM_SOFT) == TM_NXM)
5061919Swnj 					printf("TM UBA late error\n");
5072471Swnj 				sc->sc_blkno++;
5082617Swnj 				ubadone(um);
5092608Swnj 				goto opcont;
5101919Swnj 			}
5112608Swnj 		} else
5122608Swnj 			/*
5132608Swnj 			 * Hard or non-i/o errors on non-raw tape
5142608Swnj 			 * cause it to close.
5152608Swnj 			 */
5162608Swnj 			if (sc->sc_openf>0 && bp != &rtmbuf[unit])
5172608Swnj 				sc->sc_openf = -1;
5182608Swnj 		/*
5192608Swnj 		 * Couldn't recover error
5202608Swnj 		 */
5212675Swnj 		harderr(bp);
5222778Swnj 		printf("tm%d er=%b\n", dkunit(bp),
5232675Swnj 		    sc->sc_erreg, TMEREG_BITS);
5241919Swnj 		bp->b_flags |= B_ERROR;
5252608Swnj 		goto opdone;
5261919Swnj 	}
5272608Swnj 	/*
5282608Swnj 	 * Advance tape control FSM.
5292608Swnj 	 */
5302608Swnj ignoreerr:
5311919Swnj 	switch (state) {
5321919Swnj 
5331919Swnj 	case SIO:
5342608Swnj 		/*
5352608Swnj 		 * Read/write increments tape block number
5362608Swnj 		 */
5372471Swnj 		sc->sc_blkno++;
5382608Swnj 		goto opdone;
5391919Swnj 
5401919Swnj 	case SCOM:
5412608Swnj 		/*
5422608Swnj 		 * Unless special operation, op completed.
5432608Swnj 		 */
5442608Swnj 		if (bp != &ctmbuf[unit])
5452608Swnj 			goto opdone;
5462608Swnj 		/*
5472608Swnj 		 * Operation on block device...
5482608Swnj 		 * iterate operations which don't repeat
5492608Swnj 		 * for themselves in the hardware; for forward/
5502608Swnj 		 * backward space record update the current position.
5512608Swnj 		 */
5522608Swnj 		switch (bp->b_command) {
5531919Swnj 
5542608Swnj 		case TM_SFORW:
5552608Swnj 			sc->sc_blkno -= bp->b_repcnt;
5562608Swnj 			goto opdone;
5571919Swnj 
5582608Swnj 		case TM_SREV:
5592608Swnj 			sc->sc_blkno += bp->b_repcnt;
5602608Swnj 			goto opdone;
5612608Swnj 
5622608Swnj 		default:
5632608Swnj 			if (++bp->b_repcnt < 0)
5642608Swnj 				goto opcont;
5652608Swnj 			goto opdone;
5661919Swnj 		}
5671919Swnj 
5681919Swnj 	case SSEEK:
5692471Swnj 		sc->sc_blkno = dbtofsb(bp->b_blkno);
5702608Swnj 		goto opcont;
5711919Swnj 
5721919Swnj 	default:
5732608Swnj 		panic("tmintr");
5742608Swnj 	}
5752608Swnj opdone:
5762608Swnj 	/*
5772608Swnj 	 * Reset error count and remove
5782608Swnj 	 * from device queue.
5792608Swnj 	 */
5802608Swnj 	um->um_tab.b_errcnt = 0;
5812608Swnj 	dp->b_actf = bp->av_forw;
5822608Swnj 	bp->b_resid = -addr->tmbc;
5832617Swnj 	ubadone(um);
5842608Swnj 	iodone(bp);
5852608Swnj 	/*
5862608Swnj 	 * Circulate slave to end of controller
5872608Swnj 	 * queue to give other slaves a chance.
5882608Swnj 	 */
5892608Swnj 	um->um_tab.b_actf = dp->b_forw;
5902608Swnj 	if (dp->b_actf) {
5912608Swnj 		dp->b_forw = NULL;
5922608Swnj 		if (um->um_tab.b_actf == NULL)
5932608Swnj 			um->um_tab.b_actf = dp;
5942608Swnj 		else
5952608Swnj 			um->um_tab.b_actl->b_forw = dp;
5962608Swnj 		um->um_tab.b_actl = dp;
5972608Swnj 	}
5982608Swnj 	if (um->um_tab.b_actf == 0)
5991919Swnj 		return;
6002608Swnj opcont:
6012608Swnj 	tmstart(um);
6021919Swnj }
6031919Swnj 
6041919Swnj tmseteof(bp)
6051919Swnj 	register struct buf *bp;
6061919Swnj {
6072608Swnj 	register int unit = TMUNIT(bp->b_dev);
6082396Swnj 	register struct device *addr =
6092608Swnj 	    (struct device *)tmdinfo[unit]->ui_addr;
6102608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
6111919Swnj 
6122608Swnj 	if (bp == &ctmbuf[unit]) {
6132471Swnj 		if (sc->sc_blkno > dbtofsb(bp->b_blkno)) {
6141919Swnj 			/* reversing */
6152471Swnj 			sc->sc_nxrec = dbtofsb(bp->b_blkno) - addr->tmbc;
6162471Swnj 			sc->sc_blkno = sc->sc_nxrec;
6171919Swnj 		} else {
6181919Swnj 			/* spacing forward */
6192471Swnj 			sc->sc_blkno = dbtofsb(bp->b_blkno) + addr->tmbc;
6202471Swnj 			sc->sc_nxrec = sc->sc_blkno - 1;
6211919Swnj 		}
6221919Swnj 		return;
6231919Swnj 	}
6241919Swnj 	/* eof on read */
6252471Swnj 	sc->sc_nxrec = dbtofsb(bp->b_blkno);
6261919Swnj }
6271919Swnj 
6281919Swnj tmread(dev)
6292608Swnj 	dev_t dev;
6301919Swnj {
6311919Swnj 
6321919Swnj 	tmphys(dev);
6332608Swnj 	physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_READ, minphys);
6341919Swnj }
6351919Swnj 
6361919Swnj tmwrite(dev)
6372608Swnj 	dev_t dev;
6381919Swnj {
6391919Swnj 
6401919Swnj 	tmphys(dev);
6412608Swnj 	physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_WRITE, minphys);
6421919Swnj }
6431919Swnj 
6441919Swnj tmphys(dev)
6452608Swnj 	dev_t dev;
6461919Swnj {
6471919Swnj 	register daddr_t a;
6482608Swnj 	register struct tm_softc *sc = &tm_softc[TMUNIT(dev)];
6491919Swnj 
6501919Swnj 	a = dbtofsb(u.u_offset >> 9);
6512471Swnj 	sc->sc_blkno = a;
6522471Swnj 	sc->sc_nxrec = a + 1;
6531919Swnj }
6541919Swnj 
6552608Swnj tmreset(uban)
6562608Swnj 	int uban;
6572608Swnj {
6582608Swnj 	int printed = 0;
6592608Swnj 	register struct uba_minfo *um;
6602630Swnj 	register tm11, unit;
6612608Swnj 	register struct uba_dinfo *ui;
6622608Swnj 	register struct buf *dp;
6632608Swnj 
6642630Swnj 	for (tm11 = 0; tm11 < NTM; tm11++) {
6652630Swnj 		if ((um = tmminfo[tm11]) == 0 || um->um_alive == 0 ||
6662608Swnj 		   um->um_ubanum != uban)
6672608Swnj 			continue;
6682608Swnj 		if (printed == 0) {
6692608Swnj 			printf(" tm");
6702608Swnj 			DELAY(2000000);		/* time to self test */
6712608Swnj 			printed = 1;
6722608Swnj 		}
6732608Swnj 		um->um_tab.b_active = 0;
6742608Swnj 		um->um_tab.b_actf = um->um_tab.b_actl = 0;
6752608Swnj 		if (um->um_ubinfo) {
6762608Swnj 			printf("<%d>", (um->um_ubinfo>>28)&0xf);
6772617Swnj 			ubadone(um);
6782608Swnj 		}
6792608Swnj 		((struct device *)(um->um_addr))->tmcs = TM_DCLR;
6802630Swnj 		for (unit = 0; unit < NTE; unit++) {
6812608Swnj 			if ((ui = tmdinfo[unit]) == 0)
6822608Swnj 				continue;
6832608Swnj 			if (ui->ui_alive == 0)
6842608Swnj 				continue;
6852608Swnj 			dp = &tmutab[unit];
6862608Swnj 			dp->b_active = 0;
6872608Swnj 			dp->b_forw = 0;
6882608Swnj 			if (um->um_tab.b_actf == NULL)
6892608Swnj 				um->um_tab.b_actf = dp;
6902608Swnj 			else
6912608Swnj 				um->um_tab.b_actl->b_forw = dp;
6922608Swnj 			um->um_tab.b_actl = dp;
6932608Swnj 			tm_softc[unit].sc_openf = -1;
6942608Swnj 		}
6952608Swnj 		tmstart(um);
6962608Swnj 	}
6972608Swnj }
6982608Swnj 
6991919Swnj /*ARGSUSED*/
7001919Swnj tmioctl(dev, cmd, addr, flag)
7011919Swnj 	caddr_t addr;
7021919Swnj 	dev_t dev;
7031919Swnj {
7042608Swnj 	int unit = TMUNIT(dev);
7052608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
7062608Swnj 	register struct buf *bp = &ctmbuf[unit];
7071919Swnj 	register callcount;
7081919Swnj 	int fcount;
7091919Swnj 	struct mtop mtop;
7101919Swnj 	struct mtget mtget;
7111919Swnj 	/* we depend of the values and order of the MT codes here */
7122608Swnj 	static tmops[] =
7132608Swnj 	   {TM_WEOF,TM_SFORW,TM_SREV,TM_SFORW,TM_SREV,TM_REW,TM_OFFL,TM_SENSE};
7141919Swnj 
7152608Swnj 	switch (cmd) {
7161919Swnj 		case MTIOCTOP:	/* tape operation */
7171919Swnj 		if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) {
7181919Swnj 			u.u_error = EFAULT;
7191919Swnj 			return;
7201919Swnj 		}
7211919Swnj 		switch(mtop.mt_op) {
7222608Swnj 		case MTWEOF:
7231919Swnj 			callcount = mtop.mt_count;
7242608Swnj 			fcount = 1;
7252608Swnj 			break;
7262608Swnj 		case MTFSF: case MTBSF:
7272608Swnj 			callcount = mtop.mt_count;
7281919Swnj 			fcount = INF;
7291919Swnj 			break;
7301919Swnj 		case MTFSR: case MTBSR:
7311919Swnj 			callcount = 1;
7321919Swnj 			fcount = mtop.mt_count;
7331919Swnj 			break;
7342324Skre 		case MTREW: case MTOFFL: case MTNOP:
7351919Swnj 			callcount = 1;
7361919Swnj 			fcount = 1;
7371919Swnj 			break;
7381919Swnj 		default:
7391919Swnj 			u.u_error = ENXIO;
7401919Swnj 			return;
7411919Swnj 		}
7422608Swnj 		if (callcount <= 0 || fcount <= 0) {
7431919Swnj 			u.u_error = ENXIO;
7442608Swnj 			return;
7452608Swnj 		}
7462608Swnj 		while (--callcount >= 0) {
7472574Swnj 			tmcommand(dev, tmops[mtop.mt_op], fcount);
7481919Swnj 			if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) &&
7492608Swnj 			    bp->b_resid) {
7501919Swnj 				u.u_error = EIO;
7511919Swnj 				break;
7521919Swnj 			}
7532608Swnj 			if ((bp->b_flags&B_ERROR) || sc->sc_erreg&TM_BOT)
7541919Swnj 				break;
7551919Swnj 		}
7562608Swnj 		geterror(bp);
7571919Swnj 		return;
7581919Swnj 	case MTIOCGET:
7592471Swnj 		mtget.mt_dsreg = sc->sc_dsreg;
7602471Swnj 		mtget.mt_erreg = sc->sc_erreg;
7612471Swnj 		mtget.mt_resid = sc->sc_resid;
7621919Swnj 		if (copyout((caddr_t)&mtget, addr, sizeof(mtget)))
7631919Swnj 			u.u_error = EFAULT;
7641919Swnj 		return;
7651919Swnj 	default:
7661919Swnj 		u.u_error = ENXIO;
7671919Swnj 	}
7681919Swnj }
7691919Swnj 
7701919Swnj #define	DBSIZE	20
7711919Swnj 
7722363Swnj tmdump()
7732363Swnj {
7742396Swnj 	register struct uba_dinfo *ui;
7752396Swnj 	register struct uba_regs *up;
7762396Swnj 	register struct device *addr;
7772426Skre 	int blk, num;
7782426Skre 	int start;
7791919Swnj 
7802426Skre 	start = 0;
7812426Skre 	num = maxfree;
7822426Skre #define	phys(a,b)	((b)((int)(a)&0x7fffffff))
783*2887Swnj 	if (tmdinfo[0] == 0)
784*2887Swnj 		return (ENXIO);
7852458Swnj 	ui = phys(tmdinfo[0], struct uba_dinfo *);
7862396Swnj 	up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba;
7872396Swnj #if VAX780
7882396Swnj 	if (cpu == VAX_780)
7892396Swnj 		ubainit(up);
7901919Swnj #endif
7912324Skre 	DELAY(1000000);
7922396Swnj 	addr = (struct device *)ui->ui_physaddr;
7932396Swnj 	tmwait(addr);
7942608Swnj 	addr->tmcs = TM_DCLR | TM_GO;
7951919Swnj 	while (num > 0) {
7961919Swnj 		blk = num > DBSIZE ? DBSIZE : num;
7972396Swnj 		tmdwrite(start, blk, addr, up);
7981919Swnj 		start += blk;
7991919Swnj 		num -= blk;
8001919Swnj 	}
8012426Skre 	tmeof(addr);
8022426Skre 	tmeof(addr);
8032426Skre 	tmwait(addr);
804*2887Swnj 	if (addr->tmcs&TM_ERR)
805*2887Swnj 		return (EIO);
8062608Swnj 	addr->tmcs = TM_REW | TM_GO;
8072471Swnj 	tmwait(addr);
8082363Swnj 	return (0);
8091919Swnj }
8101919Swnj 
8112608Swnj tmdwrite(dbuf, num, addr, up)
8122608Swnj 	register dbuf, num;
8132396Swnj 	register struct device *addr;
8142396Swnj 	struct uba_regs *up;
8151919Swnj {
8162396Swnj 	register struct pte *io;
8172396Swnj 	register int npf;
8181928Swnj 
8192396Swnj 	tmwait(addr);
8202396Swnj 	io = up->uba_map;
8211919Swnj 	npf = num+1;
8221928Swnj 	while (--npf != 0)
8232608Swnj 		 *(int *)io++ = (dbuf++ | (1<<UBA_DPSHIFT) | UBA_MRV);
8242396Swnj 	*(int *)io = 0;
8252396Swnj 	addr->tmbc = -(num*NBPG);
8262396Swnj 	addr->tmba = 0;
8272608Swnj 	addr->tmcs = TM_WCOM | TM_GO;
8281919Swnj }
8291919Swnj 
8302396Swnj tmwait(addr)
8312396Swnj 	register struct device *addr;
8321919Swnj {
8331928Swnj 	register s;
8341919Swnj 
8351919Swnj 	do
8362396Swnj 		s = addr->tmcs;
8372608Swnj 	while ((s & TM_CUR) == 0);
8381919Swnj }
8391919Swnj 
8402396Swnj tmeof(addr)
8412396Swnj 	struct device *addr;
8421919Swnj {
8431919Swnj 
8442396Swnj 	tmwait(addr);
8452608Swnj 	addr->tmcs = TM_WEOF | TM_GO;
8461919Swnj }
8471919Swnj #endif
848