xref: /csrg-svn/sys/vax/uba/tm.c (revision 2608)
1*2608Swnj /*	tm.c	4.14	02/21/81	*/
21919Swnj 
31940Swnj #include "tm.h"
42471Swnj #if NTM03 > 0
51919Swnj /*
61919Swnj  * TM tape driver
72471Swnj  *
8*2608Swnj  * THIS DRIVER HAS NOT BEEN TESTED WITH MORE THAN ONE TRANSPORT.
91919Swnj  */
102471Swnj #define	DELAY(N)		{ register int d = N; while (--d > 0); }
111919Swnj #include "../h/param.h"
121919Swnj #include "../h/buf.h"
131919Swnj #include "../h/dir.h"
141919Swnj #include "../h/conf.h"
151919Swnj #include "../h/user.h"
161919Swnj #include "../h/file.h"
171919Swnj #include "../h/map.h"
181919Swnj #include "../h/pte.h"
192574Swnj #include "../h/vm.h"
201919Swnj #include "../h/uba.h"
211919Swnj #include "../h/mtio.h"
221919Swnj #include "../h/ioctl.h"
232363Swnj #include "../h/cmap.h"
242396Swnj #include "../h/cpu.h"
251919Swnj 
262396Swnj #include "../h/tmreg.h"
271919Swnj 
28*2608Swnj struct	buf	ctmbuf[NTM11];
29*2608Swnj struct	buf	rtmbuf[NTM11];
301919Swnj 
31*2608Swnj int	tmprobe(), tmslave(), tmattach(), tmdgo(), tmintr();
322471Swnj struct	uba_minfo *tmminfo[NTM03];
332471Swnj struct	uba_dinfo *tmdinfo[NTM11];
34*2608Swnj struct	buf tmutab[NTM11];
35*2608Swnj #ifdef notyet
36*2608Swnj struct	uba_dinfo *tmip[NTM03][4];
37*2608Swnj #endif
382458Swnj u_short	tmstd[] = { 0772520, 0 };
392396Swnj struct	uba_driver tmdriver =
40*2608Swnj   { tmprobe, tmslave, tmattach, tmdgo, tmstd, "mtm", tmdinfo, "tm", tmminfo };
411919Swnj 
421919Swnj /* bits in minor device */
43*2608Swnj #define	TMUNIT(dev)	(minor(dev)&03)
441919Swnj #define	T_NOREWIND	04
451919Swnj #define	T_1600BPI	08
461919Swnj 
471919Swnj #define	INF	(daddr_t)1000000L
481919Swnj 
49*2608Swnj /*
50*2608Swnj  * Software state per tape transport.
51*2608Swnj  */
522471Swnj struct	tm_softc {
53*2608Swnj 	char	sc_openf;	/* lock against multiple opens */
54*2608Swnj 	char	sc_lastiow;	/* last op was a write */
55*2608Swnj 	daddr_t	sc_blkno;	/* block number, for block device tape */
56*2608Swnj 	daddr_t	sc_nxrec;	/* desired block position */
57*2608Swnj 	u_short	sc_erreg;	/* copy of last erreg */
58*2608Swnj 	u_short	sc_dsreg;	/* copy of last dsreg */
59*2608Swnj 	short	sc_resid;	/* copy of last bc */
602471Swnj } tm_softc[NTM03];
611919Swnj 
62*2608Swnj /*
63*2608Swnj  * States for um->um_tab.b_active, the
64*2608Swnj  * per controller state flag.
65*2608Swnj  */
661919Swnj #define	SSEEK	1		/* seeking */
671919Swnj #define	SIO	2		/* doing seq i/o */
681919Swnj #define	SCOM	3		/* sending control command */
69*2608Swnj #define	SREW	4		/* sending a drive rewind */
701919Swnj 
71*2608Swnj /* WE CURRENTLY HANDLE REWINDS PRIMITIVELY, BUSYING OUT THE CONTROLLER */
72*2608Swnj /* DURING THE REWIND... IF WE EVER GET TWO TRANSPORTS, WE CAN DEBUG MORE */
73*2608Swnj /* SOPHISTICATED LOGIC... THIS SIMPLE CODE AT LEAST MAY WORK. */
741919Swnj 
752426Skre /*
762426Skre  * Determine if there is a controller for
772426Skre  * a tm at address reg.  Our goal is to make the
782426Skre  * device interrupt.
792426Skre  */
80*2608Swnj tmprobe(reg)
812396Swnj 	caddr_t reg;
822396Swnj {
832458Swnj 	register int br, cvec;
842426Skre 
85*2608Swnj #ifdef lint
86*2608Swnj 	br = 0; br = cvec; cvec = br;
87*2608Swnj #endif
88*2608Swnj 	((struct device *)reg)->tmcs = TM_IE;
892396Swnj 	/*
90*2608Swnj 	 * If this is a tm03, it ought to have interrupted
912396Swnj 	 * by now, if it isn't (ie: it is a ts04) then we just
922458Swnj 	 * hope that it didn't interrupt, so autoconf will ignore it.
932458Swnj 	 * Just in case, we will reference one
942396Swnj 	 * of the more distant registers, and hope for a machine
952458Swnj 	 * check, or similar disaster if this is a ts.
962471Swnj 	 *
972471Swnj 	 * Note: on an 11/780, badaddr will just generate
982471Swnj 	 * a uba error for a ts; but our caller will notice that
992471Swnj 	 * so we won't check for it.
1002396Swnj 	 */
1012396Swnj 	if (badaddr(&((struct device *)reg)->tmrd, 2))
1022458Swnj 		return (0);
1032458Swnj 	return (1);
1042396Swnj }
1052396Swnj 
106*2608Swnj /*
107*2608Swnj  * Due to a design flaw, we cannot ascertain if the tape
108*2608Swnj  * exists or not unless it is on line - ie: unless a tape is
109*2608Swnj  * mounted. This is too servere a restriction to bear,
110*2608Swnj  * so all units are assumed to exist.
111*2608Swnj  */
112*2608Swnj /*ARGSUSED*/
1132574Swnj tmslave(ui, reg)
1142396Swnj 	struct uba_dinfo *ui;
1152396Swnj 	caddr_t reg;
1162396Swnj {
1172458Swnj 
1182458Swnj 	return (1);
1192396Swnj }
1202396Swnj 
121*2608Swnj /*
122*2608Swnj  * Record attachment of the unit to the controller port.
123*2608Swnj  */
124*2608Swnj /*ARGSUSED*/
125*2608Swnj tmattach(ui)
126*2608Swnj 	struct uba_dinfo *ui;
127*2608Swnj {
128*2608Swnj 
129*2608Swnj #ifdef notyet
130*2608Swnj 	tmip[ui->ui_ctlr][ui->ui_slave] = ui;
131*2608Swnj #endif
132*2608Swnj }
133*2608Swnj 
134*2608Swnj /*
135*2608Swnj  * Open the device.  Tapes are unique open
136*2608Swnj  * devices, so we refuse if it is already open.
137*2608Swnj  * We also check that a tape is available, and
138*2608Swnj  * don't block waiting here.
139*2608Swnj  */
1401919Swnj tmopen(dev, flag)
1411919Swnj 	dev_t dev;
1421919Swnj 	int flag;
1431919Swnj {
144*2608Swnj 	register int unit;
1452396Swnj 	register struct uba_dinfo *ui;
146*2608Swnj 	register struct tm_softc *sc;
1471919Swnj 
148*2608Swnj 	unit = TMUNIT(dev);
149*2608Swnj 	if (unit>=NTM11 || (sc = &tm_softc[unit])->sc_openf ||
150*2608Swnj 	    (ui = tmdinfo[unit]) == 0 || ui->ui_alive == 0) {
151*2608Swnj 		u.u_error = ENXIO;
1521919Swnj 		return;
1531919Swnj 	}
154*2608Swnj 	tmcommand(dev, TM_SENSE, 1);
155*2608Swnj 	if ((sc->sc_erreg&(TM_SELR|TM_TUR)) != (TM_SELR|TM_TUR)) {
156*2608Swnj 		uprintf("tape not online\n");
1572471Swnj 		u.u_error = EIO;
158*2608Swnj 		return;
1591919Swnj 	}
160*2608Swnj 	if ((flag&(FREAD|FWRITE)) == FWRITE && sc->sc_erreg&TM_WRL) {
161*2608Swnj 		uprintf("tape write protected\n");
162*2608Swnj 		u.u_error = EIO;
1631919Swnj 		return;
1641919Swnj 	}
165*2608Swnj 	sc->sc_openf = 1;
1662471Swnj 	sc->sc_blkno = (daddr_t)0;
1672471Swnj 	sc->sc_nxrec = INF;
168*2608Swnj 	sc->sc_lastiow = 0;
1692471Swnj 	sc->sc_openf = 1;
170*2608Swnj 	return;
1711919Swnj }
1721919Swnj 
173*2608Swnj /*
174*2608Swnj  * Close tape device.
175*2608Swnj  *
176*2608Swnj  * If tape was open for writing or last operation was
177*2608Swnj  * a write, then write two EOF's and backspace over the last one.
178*2608Swnj  * Unless this is a non-rewinding special file, rewind the tape.
179*2608Swnj  * Make the tape available to others.
180*2608Swnj  */
1811919Swnj tmclose(dev, flag)
1821919Swnj 	register dev_t dev;
1831919Swnj 	register flag;
1841919Swnj {
185*2608Swnj 	register struct tm_softc *sc = &tm_softc[TMUNIT(dev)];
1861919Swnj 
187*2608Swnj 	if (flag == FWRITE || (flag&FWRITE) && sc->sc_lastiow) {
188*2608Swnj 		tmcommand(dev, TM_WEOF, 1);
189*2608Swnj 		tmcommand(dev, TM_WEOF, 1);
190*2608Swnj 		tmcommand(dev, TM_SREV, 1);
1911919Swnj 	}
1921919Swnj 	if ((minor(dev)&T_NOREWIND) == 0)
193*2608Swnj 		tmcommand(dev, TM_REW, 1);
1942471Swnj 	sc->sc_openf = 0;
1951919Swnj }
1961919Swnj 
197*2608Swnj /*
198*2608Swnj  * Execute a command on the tape drive
199*2608Swnj  * a specified number of times.
200*2608Swnj  */
2012574Swnj tmcommand(dev, com, count)
2021919Swnj 	dev_t dev;
2031919Swnj 	int com, count;
2041919Swnj {
2051919Swnj 	register struct buf *bp;
2061919Swnj 
207*2608Swnj 	bp = &ctmbuf[TMUNIT(dev)];
2081919Swnj 	(void) spl5();
2091919Swnj 	while (bp->b_flags&B_BUSY) {
2101919Swnj 		bp->b_flags |= B_WANTED;
2111919Swnj 		sleep((caddr_t)bp, PRIBIO);
2121919Swnj 	}
2131919Swnj 	bp->b_flags = B_BUSY|B_READ;
2141919Swnj 	(void) spl0();
2151919Swnj 	bp->b_dev = dev;
2161919Swnj 	bp->b_repcnt = -count;
2171919Swnj 	bp->b_command = com;
2181919Swnj 	bp->b_blkno = 0;
2191919Swnj 	tmstrategy(bp);
2201919Swnj 	iowait(bp);
2211919Swnj 	if (bp->b_flags&B_WANTED)
2221919Swnj 		wakeup((caddr_t)bp);
2231919Swnj 	bp->b_flags &= B_ERROR;
2241919Swnj }
2251919Swnj 
226*2608Swnj /*
227*2608Swnj  * Decipher a tape operation and do what is needed
228*2608Swnj  * to see that it happens.
229*2608Swnj  */
2301919Swnj tmstrategy(bp)
2311919Swnj 	register struct buf *bp;
2321919Swnj {
233*2608Swnj 	int unit = TMUNIT(bp->b_dev);
234*2608Swnj 	register struct uba_minfo *um;
235*2608Swnj 	register struct buf *dp;
236*2608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
2371919Swnj 
238*2608Swnj 	/*
239*2608Swnj 	 * Put transfer at end of unit queue
240*2608Swnj 	 */
241*2608Swnj 	dp = &tmutab[unit];
2421919Swnj 	bp->av_forw = NULL;
2431919Swnj 	(void) spl5();
244*2608Swnj 	if (dp->b_actf == NULL) {
245*2608Swnj 		dp->b_actf = bp;
246*2608Swnj 		/*
247*2608Swnj 		 * Transport not already active...
248*2608Swnj 		 * put at end of controller queue.
249*2608Swnj 		 */
250*2608Swnj 		dp->b_forw = NULL;
251*2608Swnj 		um = tmdinfo[unit]->ui_mi;
252*2608Swnj 		if (um->um_tab.b_actf == NULL)
253*2608Swnj 			um->um_tab.b_actf = dp;
254*2608Swnj 		else
255*2608Swnj 			um->um_tab.b_actl->b_forw = dp;
256*2608Swnj 		um->um_tab.b_actl = dp;
257*2608Swnj 	} else
258*2608Swnj 		dp->b_actl->av_forw = bp;
259*2608Swnj 	dp->b_actl = bp;
260*2608Swnj 	/*
261*2608Swnj 	 * If the controller is not busy, get
262*2608Swnj 	 * it going.
263*2608Swnj 	 */
264*2608Swnj 	if (um->um_tab.b_active == 0)
265*2608Swnj 		tmstart(um);
2661919Swnj 	(void) spl0();
2671919Swnj }
2681919Swnj 
269*2608Swnj /*
270*2608Swnj  * Start activity on a tm controller.
271*2608Swnj  */
272*2608Swnj tmstart(um)
273*2608Swnj 	register struct uba_minfo *um;
2741919Swnj {
275*2608Swnj 	register struct buf *bp, *dp;
276*2608Swnj 	register struct device *addr = (struct device *)um->um_addr;
277*2608Swnj 	register struct tm_softc *sc;
2782396Swnj 	register struct uba_dinfo *ui;
279*2608Swnj 	int unit, cmd;
2802471Swnj 	daddr_t blkno;
2811919Swnj 
282*2608Swnj 	/*
283*2608Swnj 	 * Look for an idle transport on the controller.
284*2608Swnj 	 */
2851919Swnj loop:
286*2608Swnj 	if ((dp = um->um_tab.b_actf) == NULL)
2871919Swnj 		return;
288*2608Swnj 	if ((bp = dp->b_actf) == NULL) {
289*2608Swnj 		um->um_tab.b_actf = dp->b_forw;
290*2608Swnj 		goto loop;
291*2608Swnj 	}
292*2608Swnj 	unit = TMUNIT(bp->b_dev);
293*2608Swnj 	ui = tmdinfo[unit];
294*2608Swnj 	/*
295*2608Swnj 	 * Record pre-transfer status (e.g. for TM_SENSE)
296*2608Swnj 	 */
297*2608Swnj 	sc = &tm_softc[unit];
298*2608Swnj 	addr = (struct device *)um->um_addr;
299*2608Swnj 	addr->tmcs = (ui->ui_slave << 8);
3002471Swnj 	sc->sc_dsreg = addr->tmcs;
3012471Swnj 	sc->sc_erreg = addr->tmer;
3022471Swnj 	sc->sc_resid = addr->tmbc;
303*2608Swnj 	/*
304*2608Swnj 	 * Default is that last command was NOT a write command;
305*2608Swnj 	 * if we do a write command we will notice this in tmintr().
306*2608Swnj 	 */
307*2608Swnj 	sc->sc_lastiow = 1;
308*2608Swnj 	if (sc->sc_openf < 0 || (addr->tmcs&TM_CUR) == 0) {
309*2608Swnj 		/*
310*2608Swnj 		 * Have had a hard error on this (non-raw) tape,
311*2608Swnj 		 * or the tape unit is now unavailable (e.g. taken off
312*2608Swnj 		 * line).
313*2608Swnj 		 */
314*2608Swnj 		bp->b_flags |= B_ERROR;
3151919Swnj 		goto next;
3161919Swnj 	}
317*2608Swnj 	/*
318*2608Swnj 	 * If operation is not a control operation,
319*2608Swnj 	 * check for boundary conditions.
320*2608Swnj 	 */
321*2608Swnj 	if (bp != &ctmbuf[unit]) {
322*2608Swnj 		if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) {
323*2608Swnj 			bp->b_flags |= B_ERROR;
324*2608Swnj 			bp->b_error = ENXIO;		/* past EOF */
325*2608Swnj 			goto next;
3261919Swnj 		}
327*2608Swnj 		if (dbtofsb(bp->b_blkno) == sc->sc_nxrec &&
328*2608Swnj 		    bp->b_flags&B_READ) {
329*2608Swnj 			bp->b_resid = bp->b_bcount;
330*2608Swnj 			clrbuf(bp);			/* at EOF */
331*2608Swnj 			goto next;
332*2608Swnj 		}
333*2608Swnj 		if ((bp->b_flags&B_READ) == 0)
334*2608Swnj 			/* write sets EOF */
335*2608Swnj 			sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1;
3361919Swnj 	}
337*2608Swnj 	/*
338*2608Swnj 	 * Set up the command, and then if this is a mt ioctl,
339*2608Swnj 	 * do the operation using, for TM_SFORW and TM_SREV, the specified
340*2608Swnj 	 * operation count.
341*2608Swnj 	 */
342*2608Swnj 	cmd = TM_IE | TM_GO | (ui->ui_slave << 8);
343*2608Swnj 	if ((minor(bp->b_dev) & T_1600BPI) == 0)
344*2608Swnj 		cmd |= TM_D800;
345*2608Swnj 	if (bp == &ctmbuf[unit]) {
346*2608Swnj 		if (bp->b_command == TM_SENSE)
347*2608Swnj 			goto next;
348*2608Swnj 		cmd |= bp->b_command;
349*2608Swnj 		um->um_tab.b_active =
350*2608Swnj 		    bp->b_command == TM_REW ? SREW : SCOM;
351*2608Swnj 		if (bp->b_command == TM_SFORW || bp->b_command == TM_SREV)
352*2608Swnj 			addr->tmbc = bp->b_repcnt;
353*2608Swnj 		addr->tmcs = cmd;
354*2608Swnj 		return;
355*2608Swnj 	}
356*2608Swnj 	/*
357*2608Swnj 	 * If the data transfer command is in the correct place,
358*2608Swnj 	 * set up all the registers except the csr, and give
359*2608Swnj 	 * control over to the UNIBUS adapter routines, to
360*2608Swnj 	 * wait for resources to start the i/o.
361*2608Swnj 	 */
3622471Swnj 	if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) {
3632396Swnj 		addr->tmbc = -bp->b_bcount;
3641919Swnj 		if ((bp->b_flags&B_READ) == 0) {
3652471Swnj 			if (um->um_tab.b_errcnt)
366*2608Swnj 				cmd |= TM_WIRG;
3671919Swnj 			else
368*2608Swnj 				cmd |= TM_WCOM;
3691919Swnj 		} else
370*2608Swnj 			cmd |= TM_RCOM;
3712471Swnj 		um->um_tab.b_active = SIO;
3722574Swnj 		um->um_cmd = cmd;
3732574Swnj 		ubago(ui);
3741919Swnj 		return;
3751919Swnj 	}
376*2608Swnj 	/*
377*2608Swnj 	 * Block tape positioned incorrectly;
378*2608Swnj 	 * seek forwards or backwards to the correct spot.
379*2608Swnj 	 */
3802471Swnj 	um->um_tab.b_active = SSEEK;
3811919Swnj 	if (blkno < dbtofsb(bp->b_blkno)) {
382*2608Swnj 		cmd |= TM_SFORW;
3832396Swnj 		addr->tmbc = blkno - dbtofsb(bp->b_blkno);
3841919Swnj 	} else {
385*2608Swnj 		cmd |= TM_SREV;
3862396Swnj 		addr->tmbc = dbtofsb(bp->b_blkno) - blkno;
3871919Swnj 	}
3882396Swnj 	addr->tmcs = cmd;
3891919Swnj 	return;
3901919Swnj 
3911919Swnj next:
392*2608Swnj 	/*
393*2608Swnj 	 * Done with this operation due to error or
394*2608Swnj 	 * the fact that it doesn't do anything.
395*2608Swnj 	 * Release UBA resources (if any), dequeue
396*2608Swnj 	 * the transfer and continue processing this slave.
397*2608Swnj 	 */
398*2608Swnj 	if (um->um_ubinfo)
399*2608Swnj 		ubarelse(um->um_ubanum, &um->um_ubinfo);
400*2608Swnj 	um->um_tab.b_errcnt = 0;
401*2608Swnj 	dp->b_actf = bp->av_forw;
4021919Swnj 	iodone(bp);
4031919Swnj 	goto loop;
4041919Swnj }
4051919Swnj 
406*2608Swnj /*
407*2608Swnj  * The UNIBUS resources we needed have been
408*2608Swnj  * allocated to us; start the device.
409*2608Swnj  */
4102574Swnj tmdgo(um)
4112574Swnj 	register struct uba_minfo *um;
4121919Swnj {
4132574Swnj 	register struct device *addr = (struct device *)um->um_addr;
4142471Swnj 
4152574Swnj 	addr->tmba = um->um_ubinfo;
4162574Swnj 	addr->tmcs = um->um_cmd | ((um->um_ubinfo >> 12) & 0x30);
4172396Swnj }
4182396Swnj 
419*2608Swnj /*
420*2608Swnj  * Tm interrupt routine.
421*2608Swnj  */
4222471Swnj /*ARGSUSED*/
423*2608Swnj tmintr(tm03)
424*2608Swnj 	int tm03;
4252396Swnj {
426*2608Swnj 	struct buf *dp;
4271919Swnj 	register struct buf *bp;
428*2608Swnj 	register struct uba_minfo *um = tmminfo[tm03];
429*2608Swnj 	register struct device *addr = (struct device *)tmdinfo[tm03]->ui_addr;
430*2608Swnj 	register struct tm_softc *sc;
431*2608Swnj 	int unit;
4321919Swnj 	register state;
4331919Swnj 
434*2608Swnj 	/*
435*2608Swnj 	 * If last command was a rewind, and tape is still
436*2608Swnj 	 * rewinding, wait for the rewind complete interrupt.
437*2608Swnj 	 */
438*2608Swnj 	if (um->um_tab.b_active == SREW) {
439*2608Swnj 		um->um_tab.b_active = SCOM;
440*2608Swnj 		if (addr->tmer&TM_RWS)
441*2608Swnj 			return;
4421919Swnj 	}
443*2608Swnj 	/*
444*2608Swnj 	 * An operation completed... record status
445*2608Swnj 	 */
446*2608Swnj 	if ((dp = um->um_tab.b_actf) == NULL)
4471919Swnj 		return;
448*2608Swnj 	bp = dp->b_actf;
449*2608Swnj 	unit = TMUNIT(bp->b_dev);
450*2608Swnj 	sc = &tm_softc[unit];
4512471Swnj 	sc->sc_dsreg = addr->tmcs;
4522471Swnj 	sc->sc_erreg = addr->tmer;
4532471Swnj 	sc->sc_resid = addr->tmbc;
4541919Swnj 	if ((bp->b_flags & B_READ) == 0)
455*2608Swnj 		sc->sc_lastiow = 1;
4562471Swnj 	state = um->um_tab.b_active;
4572471Swnj 	um->um_tab.b_active = 0;
458*2608Swnj 	/*
459*2608Swnj 	 * Check for errors.
460*2608Swnj 	 */
461*2608Swnj 	if (addr->tmcs&TM_ERR) {
462*2608Swnj 		while (addr->tmer & TM_SDWN)
4631919Swnj 			;			/* await settle down */
464*2608Swnj 		/*
465*2608Swnj 		 * If we hit the end of the tape update our position.
466*2608Swnj 		 */
467*2608Swnj 		if (addr->tmer&TM_EOF) {
468*2608Swnj 			tmseteof(bp);		/* set blkno and nxrec */
469*2608Swnj 			state = SCOM;		/* force completion */
470*2608Swnj 			/*
471*2608Swnj 			 * Stuff bc so it will be unstuffed correctly
472*2608Swnj 			 * later to get resid.
473*2608Swnj 			 */
4742396Swnj 			addr->tmbc = -bp->b_bcount;
475*2608Swnj 			goto opdone;
4761919Swnj 		}
477*2608Swnj 		/*
478*2608Swnj 		 * If we were reading and the only error was that the
479*2608Swnj 		 * record was to long, then we don't consider this an error.
480*2608Swnj 		 */
481*2608Swnj 		if ((bp->b_flags&B_READ) &&
482*2608Swnj 		    (addr->tmer&(TM_HARD|TM_SOFT)) == TM_RLE)
483*2608Swnj 			goto ignoreerr;
484*2608Swnj 		/*
485*2608Swnj 		 * If error is not hard, and this was an i/o operation
486*2608Swnj 		 * retry up to 8 times.
487*2608Swnj 		 */
488*2608Swnj 		if ((addr->tmer&TM_HARD)==0 && state==SIO) {
4892471Swnj 			if (++um->um_tab.b_errcnt < 7) {
490*2608Swnj /* SHOULD CHECK THAT RECOVERY WORKS IN THIS CASE */
491*2608Swnj /* AND THEN ONLY PRINT IF errcnt==7 */
492*2608Swnj 				if((addr->tmer&TM_SOFT) == TM_NXM)
4931919Swnj 					printf("TM UBA late error\n");
4942471Swnj 				sc->sc_blkno++;
4952574Swnj 				ubarelse(um->um_ubanum, &um->um_ubinfo);
496*2608Swnj 				goto opcont;
4971919Swnj 			}
498*2608Swnj 		} else
499*2608Swnj 			/*
500*2608Swnj 			 * Hard or non-i/o errors on non-raw tape
501*2608Swnj 			 * cause it to close.
502*2608Swnj 			 */
503*2608Swnj 			if (sc->sc_openf>0 && bp != &rtmbuf[unit])
504*2608Swnj 				sc->sc_openf = -1;
505*2608Swnj 		/*
506*2608Swnj 		 * Couldn't recover error
507*2608Swnj 		 */
5082471Swnj 		deverror(bp, sc->sc_erreg, sc->sc_dsreg);
5091919Swnj 		bp->b_flags |= B_ERROR;
510*2608Swnj 		goto opdone;
5111919Swnj 	}
512*2608Swnj 	/*
513*2608Swnj 	 * Advance tape control FSM.
514*2608Swnj 	 */
515*2608Swnj ignoreerr:
5161919Swnj 	switch (state) {
5171919Swnj 
5181919Swnj 	case SIO:
519*2608Swnj 		/*
520*2608Swnj 		 * Read/write increments tape block number
521*2608Swnj 		 */
5222471Swnj 		sc->sc_blkno++;
523*2608Swnj 		goto opdone;
5241919Swnj 
5251919Swnj 	case SCOM:
526*2608Swnj 		/*
527*2608Swnj 		 * Unless special operation, op completed.
528*2608Swnj 		 */
529*2608Swnj 		if (bp != &ctmbuf[unit])
530*2608Swnj 			goto opdone;
531*2608Swnj 		/*
532*2608Swnj 		 * Operation on block device...
533*2608Swnj 		 * iterate operations which don't repeat
534*2608Swnj 		 * for themselves in the hardware; for forward/
535*2608Swnj 		 * backward space record update the current position.
536*2608Swnj 		 */
537*2608Swnj 		switch (bp->b_command) {
5381919Swnj 
539*2608Swnj 		case TM_SFORW:
540*2608Swnj 			sc->sc_blkno -= bp->b_repcnt;
541*2608Swnj 			goto opdone;
5421919Swnj 
543*2608Swnj 		case TM_SREV:
544*2608Swnj 			sc->sc_blkno += bp->b_repcnt;
545*2608Swnj 			goto opdone;
546*2608Swnj 
547*2608Swnj 		default:
548*2608Swnj 			if (++bp->b_repcnt < 0)
549*2608Swnj 				goto opcont;
550*2608Swnj 			goto opdone;
5511919Swnj 		}
5521919Swnj 
5531919Swnj 	case SSEEK:
5542471Swnj 		sc->sc_blkno = dbtofsb(bp->b_blkno);
555*2608Swnj 		goto opcont;
5561919Swnj 
5571919Swnj 	default:
558*2608Swnj 		panic("tmintr");
559*2608Swnj 	}
560*2608Swnj opdone:
561*2608Swnj 	/*
562*2608Swnj 	 * Reset error count and remove
563*2608Swnj 	 * from device queue.
564*2608Swnj 	 */
565*2608Swnj 	um->um_tab.b_errcnt = 0;
566*2608Swnj 	dp->b_actf = bp->av_forw;
567*2608Swnj 	bp->b_resid = -addr->tmbc;
568*2608Swnj 	ubarelse(um->um_ubanum, &um->um_ubinfo);
569*2608Swnj 	iodone(bp);
570*2608Swnj 	/*
571*2608Swnj 	 * Circulate slave to end of controller
572*2608Swnj 	 * queue to give other slaves a chance.
573*2608Swnj 	 */
574*2608Swnj 	um->um_tab.b_actf = dp->b_forw;
575*2608Swnj 	if (dp->b_actf) {
576*2608Swnj 		dp->b_forw = NULL;
577*2608Swnj 		if (um->um_tab.b_actf == NULL)
578*2608Swnj 			um->um_tab.b_actf = dp;
579*2608Swnj 		else
580*2608Swnj 			um->um_tab.b_actl->b_forw = dp;
581*2608Swnj 		um->um_tab.b_actl = dp;
582*2608Swnj 	}
583*2608Swnj 	if (um->um_tab.b_actf == 0)
5841919Swnj 		return;
585*2608Swnj opcont:
586*2608Swnj 	tmstart(um);
5871919Swnj }
5881919Swnj 
5891919Swnj tmseteof(bp)
5901919Swnj 	register struct buf *bp;
5911919Swnj {
592*2608Swnj 	register int unit = TMUNIT(bp->b_dev);
5932396Swnj 	register struct device *addr =
594*2608Swnj 	    (struct device *)tmdinfo[unit]->ui_addr;
595*2608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
5961919Swnj 
597*2608Swnj 	if (bp == &ctmbuf[unit]) {
5982471Swnj 		if (sc->sc_blkno > dbtofsb(bp->b_blkno)) {
5991919Swnj 			/* reversing */
6002471Swnj 			sc->sc_nxrec = dbtofsb(bp->b_blkno) - addr->tmbc;
6012471Swnj 			sc->sc_blkno = sc->sc_nxrec;
6021919Swnj 		} else {
6031919Swnj 			/* spacing forward */
6042471Swnj 			sc->sc_blkno = dbtofsb(bp->b_blkno) + addr->tmbc;
6052471Swnj 			sc->sc_nxrec = sc->sc_blkno - 1;
6061919Swnj 		}
6071919Swnj 		return;
6081919Swnj 	}
6091919Swnj 	/* eof on read */
6102471Swnj 	sc->sc_nxrec = dbtofsb(bp->b_blkno);
6111919Swnj }
6121919Swnj 
6131919Swnj tmread(dev)
614*2608Swnj 	dev_t dev;
6151919Swnj {
6161919Swnj 
6171919Swnj 	tmphys(dev);
618*2608Swnj 	physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_READ, minphys);
6191919Swnj }
6201919Swnj 
6211919Swnj tmwrite(dev)
622*2608Swnj 	dev_t dev;
6231919Swnj {
6241919Swnj 
6251919Swnj 	tmphys(dev);
626*2608Swnj 	physio(tmstrategy, &rtmbuf[TMUNIT(dev)], dev, B_WRITE, minphys);
6271919Swnj }
6281919Swnj 
6291919Swnj tmphys(dev)
630*2608Swnj 	dev_t dev;
6311919Swnj {
6321919Swnj 	register daddr_t a;
633*2608Swnj 	register struct tm_softc *sc = &tm_softc[TMUNIT(dev)];
6341919Swnj 
6351919Swnj 	a = dbtofsb(u.u_offset >> 9);
6362471Swnj 	sc->sc_blkno = a;
6372471Swnj 	sc->sc_nxrec = a + 1;
6381919Swnj }
6391919Swnj 
640*2608Swnj tmreset(uban)
641*2608Swnj 	int uban;
642*2608Swnj {
643*2608Swnj 	int printed = 0;
644*2608Swnj 	register struct uba_minfo *um;
645*2608Swnj 	register tm03, unit;
646*2608Swnj 	register struct uba_dinfo *ui;
647*2608Swnj 	register struct buf *dp;
648*2608Swnj 
649*2608Swnj 	for (tm03 = 0; tm03 < NTM03; tm03++) {
650*2608Swnj 		if ((um = tmminfo[tm03]) == 0 || um->um_alive == 0 ||
651*2608Swnj 		   um->um_ubanum != uban)
652*2608Swnj 			continue;
653*2608Swnj 		if (printed == 0) {
654*2608Swnj 			printf(" tm");
655*2608Swnj 			DELAY(2000000);		/* time to self test */
656*2608Swnj 			printed = 1;
657*2608Swnj 		}
658*2608Swnj 		um->um_tab.b_active = 0;
659*2608Swnj 		um->um_tab.b_actf = um->um_tab.b_actl = 0;
660*2608Swnj 		if (um->um_ubinfo) {
661*2608Swnj 			printf("<%d>", (um->um_ubinfo>>28)&0xf);
662*2608Swnj 			ubarelse(um->um_ubanum, &um->um_ubinfo);
663*2608Swnj 		}
664*2608Swnj 		((struct device *)(um->um_addr))->tmcs = TM_DCLR;
665*2608Swnj 		for (unit = 0; unit < NTM11; unit++) {
666*2608Swnj 			if ((ui = tmdinfo[unit]) == 0)
667*2608Swnj 				continue;
668*2608Swnj 			if (ui->ui_alive == 0)
669*2608Swnj 				continue;
670*2608Swnj 			dp = &tmutab[unit];
671*2608Swnj 			dp->b_active = 0;
672*2608Swnj 			dp->b_forw = 0;
673*2608Swnj 			if (um->um_tab.b_actf == NULL)
674*2608Swnj 				um->um_tab.b_actf = dp;
675*2608Swnj 			else
676*2608Swnj 				um->um_tab.b_actl->b_forw = dp;
677*2608Swnj 			um->um_tab.b_actl = dp;
678*2608Swnj 			tm_softc[unit].sc_openf = -1;
679*2608Swnj 		}
680*2608Swnj 		tmstart(um);
681*2608Swnj 	}
682*2608Swnj }
683*2608Swnj 
6841919Swnj /*ARGSUSED*/
6851919Swnj tmioctl(dev, cmd, addr, flag)
6861919Swnj 	caddr_t addr;
6871919Swnj 	dev_t dev;
6881919Swnj {
689*2608Swnj 	int unit = TMUNIT(dev);
690*2608Swnj 	register struct tm_softc *sc = &tm_softc[unit];
691*2608Swnj 	register struct buf *bp = &ctmbuf[unit];
6921919Swnj 	register callcount;
6931919Swnj 	int fcount;
6941919Swnj 	struct mtop mtop;
6951919Swnj 	struct mtget mtget;
6961919Swnj 	/* we depend of the values and order of the MT codes here */
697*2608Swnj 	static tmops[] =
698*2608Swnj 	   {TM_WEOF,TM_SFORW,TM_SREV,TM_SFORW,TM_SREV,TM_REW,TM_OFFL,TM_SENSE};
6991919Swnj 
700*2608Swnj 	switch (cmd) {
7011919Swnj 		case MTIOCTOP:	/* tape operation */
7021919Swnj 		if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) {
7031919Swnj 			u.u_error = EFAULT;
7041919Swnj 			return;
7051919Swnj 		}
7061919Swnj 		switch(mtop.mt_op) {
707*2608Swnj 		case MTWEOF:
7081919Swnj 			callcount = mtop.mt_count;
709*2608Swnj 			fcount = 1;
710*2608Swnj 			break;
711*2608Swnj 		case MTFSF: case MTBSF:
712*2608Swnj 			callcount = mtop.mt_count;
7131919Swnj 			fcount = INF;
7141919Swnj 			break;
7151919Swnj 		case MTFSR: case MTBSR:
7161919Swnj 			callcount = 1;
7171919Swnj 			fcount = mtop.mt_count;
7181919Swnj 			break;
7192324Skre 		case MTREW: case MTOFFL: case MTNOP:
7201919Swnj 			callcount = 1;
7211919Swnj 			fcount = 1;
7221919Swnj 			break;
7231919Swnj 		default:
7241919Swnj 			u.u_error = ENXIO;
7251919Swnj 			return;
7261919Swnj 		}
727*2608Swnj 		if (callcount <= 0 || fcount <= 0) {
7281919Swnj 			u.u_error = ENXIO;
729*2608Swnj 			return;
730*2608Swnj 		}
731*2608Swnj 		while (--callcount >= 0) {
7322574Swnj 			tmcommand(dev, tmops[mtop.mt_op], fcount);
7331919Swnj 			if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) &&
734*2608Swnj 			    bp->b_resid) {
7351919Swnj 				u.u_error = EIO;
7361919Swnj 				break;
7371919Swnj 			}
738*2608Swnj 			if ((bp->b_flags&B_ERROR) || sc->sc_erreg&TM_BOT)
7391919Swnj 				break;
7401919Swnj 		}
741*2608Swnj 		geterror(bp);
7421919Swnj 		return;
7431919Swnj 	case MTIOCGET:
7442471Swnj 		mtget.mt_dsreg = sc->sc_dsreg;
7452471Swnj 		mtget.mt_erreg = sc->sc_erreg;
7462471Swnj 		mtget.mt_resid = sc->sc_resid;
7471919Swnj 		if (copyout((caddr_t)&mtget, addr, sizeof(mtget)))
7481919Swnj 			u.u_error = EFAULT;
7491919Swnj 		return;
7501919Swnj 	default:
7511919Swnj 		u.u_error = ENXIO;
7521919Swnj 	}
7531919Swnj }
7541919Swnj 
7551919Swnj #define	DBSIZE	20
7561919Swnj 
7572363Swnj tmdump()
7582363Swnj {
7592396Swnj 	register struct uba_dinfo *ui;
7602396Swnj 	register struct uba_regs *up;
7612396Swnj 	register struct device *addr;
7622426Skre 	int blk, num;
7632426Skre 	int start;
7641919Swnj 
7652426Skre 	start = 0;
7662426Skre 	num = maxfree;
7672426Skre #define	phys(a,b)	((b)((int)(a)&0x7fffffff))
7682458Swnj 	if (tmdinfo[0] == 0) {
7692396Swnj 		printf("dna\n");
7702396Swnj 		return (-1);
7712396Swnj 	}
7722458Swnj 	ui = phys(tmdinfo[0], struct uba_dinfo *);
7732396Swnj 	up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba;
7742396Swnj #if VAX780
7752396Swnj 	if (cpu == VAX_780)
7762396Swnj 		ubainit(up);
7771919Swnj #endif
7782324Skre 	DELAY(1000000);
7792396Swnj 	addr = (struct device *)ui->ui_physaddr;
7802396Swnj 	tmwait(addr);
781*2608Swnj 	addr->tmcs = TM_DCLR | TM_GO;
7821919Swnj 	while (num > 0) {
7831919Swnj 		blk = num > DBSIZE ? DBSIZE : num;
7842396Swnj 		tmdwrite(start, blk, addr, up);
7851919Swnj 		start += blk;
7861919Swnj 		num -= blk;
7871919Swnj 	}
7882426Skre 	tmeof(addr);
7892426Skre 	tmeof(addr);
7902426Skre 	tmwait(addr);
791*2608Swnj 	addr->tmcs = TM_REW | TM_GO;
7922471Swnj 	tmwait(addr);
7932363Swnj 	return (0);
7941919Swnj }
7951919Swnj 
796*2608Swnj tmdwrite(dbuf, num, addr, up)
797*2608Swnj 	register dbuf, num;
7982396Swnj 	register struct device *addr;
7992396Swnj 	struct uba_regs *up;
8001919Swnj {
8012396Swnj 	register struct pte *io;
8022396Swnj 	register int npf;
8031928Swnj 
8042396Swnj 	tmwait(addr);
8052396Swnj 	io = up->uba_map;
8061919Swnj 	npf = num+1;
8071928Swnj 	while (--npf != 0)
808*2608Swnj 		 *(int *)io++ = (dbuf++ | (1<<UBA_DPSHIFT) | UBA_MRV);
8092396Swnj 	*(int *)io = 0;
8102396Swnj 	addr->tmbc = -(num*NBPG);
8112396Swnj 	addr->tmba = 0;
812*2608Swnj 	addr->tmcs = TM_WCOM | TM_GO;
8131919Swnj }
8141919Swnj 
8152396Swnj tmwait(addr)
8162396Swnj 	register struct device *addr;
8171919Swnj {
8181928Swnj 	register s;
8191919Swnj 
8201919Swnj 	do
8212396Swnj 		s = addr->tmcs;
822*2608Swnj 	while ((s & TM_CUR) == 0);
8231919Swnj }
8241919Swnj 
8252396Swnj tmeof(addr)
8262396Swnj 	struct device *addr;
8271919Swnj {
8281919Swnj 
8292396Swnj 	tmwait(addr);
830*2608Swnj 	addr->tmcs = TM_WEOF | TM_GO;
8311919Swnj }
8321919Swnj #endif
833