1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)qdreg.h 1.4 Berkeley 06/03/88 7 */ 8 /* derived from: @(#)qdreg.h 6.1 (ULTRIX) 11/24/87 */ 9 10 /************************************************************************ 11 * * 12 * Copyright (c) 1985, 1986 by * 13 * Digital Equipment Corporation, Maynard, MA * 14 * All rights reserved. * 15 * * 16 * This software is furnished under a license and may be used and * 17 * copied only in accordance with the terms of such license and * 18 * with the inclusion of the above copyright notice. This * 19 * software or any other copies thereof may not be provided or * 20 * otherwise made available to any other person. No title to and * 21 * ownership of the software is hereby transferred. * 22 * * 23 * The information in this software is subject to change without * 24 * notice and should not be construed as a commitment by Digital * 25 * Equipment Corporation. * 26 * * 27 * Digital assumes no responsibility for the use or reliability * 28 * of its software on equipment which is not supplied by Digital. * 29 * * 30 ************************************************************************/ 31 32 /* 33 * qdreg.h 34 * 35 * Modification history 36 * 37 * QDSS registers/data structures and definitions 38 * 39 * 4-Feb-85 - longo 40 * 41 * Created file. 42 * 43 * 18-Mar-85 - longo 44 * 45 * Added DGA CSR bit definitions. 46 * 47 * 20-Mar-85 - longo 48 * 49 * Revised register naming conventions. 50 * 51 * 28-Mar-85 - longo 52 * 53 * Added DUART register struct. 54 * 55 * 19-Apr-85 - longo 56 * 57 * Removed "base" entry from 'struct qdmap'. 58 * 59 * 1-May-85 - longo 60 * 61 * Changed layout of DUART device map data structure and 62 * added command/intrpt/status bit definitions. 63 * 64 * 4-Jun-85 - longo 65 * 66 * Added bit definitions for ADDER registers. 67 * 68 * 10-Sep-85 - longo 69 * 70 * Changed dga struct DMA address entry names. 71 * 72 * 25-Sep-85 - longo 73 * 74 * Changed ADDER status bit constant. 75 * 76 * 20-May-86 - ricky palmer 77 * 78 * Added new DEVIOCGET ioctl request code. V2.0 79 * 80 */ 81 #define DEV_SIZE 8 /*XXX*/ 82 83 /* Dragon ADDER reg map */ 84 /* ADDER register bit definitions */ 85 /* Y_SCROLL_CONSTANT */ 86 87 #define SCROLL_ERASE 0x2000 88 #define ADDER_SCROLL_DOWN 0x1000 89 90 /* ADDER status and interrupt enable registers [1], [2], [3] */ 91 92 #define DISABLE 0x0000 93 #define PAUSE_COMPLETE 0x0001 94 #define FRAME_SYNC 0x0002 95 #define INIT_COMPLETE 0x0004 96 #define RASTEROP_COMPLETE 0x0008 97 98 #define ADDRESS_COMPLETE 0x0010 99 #define RX_READY 0x0020 100 #define TX_READY 0x0040 101 #define ID_SCROLL_READY 0x0080 102 103 #define TOP_CLIP 0x0100 104 #define BOTTOM_CLIP 0x0200 105 #define LEFT_CLIP 0x0400 106 #define RIGHT_CLIP 0x0800 107 #define NO_CLIP 0x1000 108 #define VSYNC 0x2000 109 110 /* ADDER command register [8], [10] */ 111 112 #define OCR_zero 0x0000 113 #define Z_BLOCK0 0x0000 114 #define OCRA 0x0000 115 #define OCRB 0x0004 116 #define RASTEROP 0x02c0 117 #define PBT 0x03c0 118 #define BTPZ 0x0bb0 119 #define PTBZ 0x07a0 120 #define DTE 0x0400 121 #define S1E 0x0800 122 #define S2E 0x1000 123 #define VIPER_Z_LOAD 0x01A0 124 #define ID_LOAD 0x0100 125 #define CANCEL 0x0000 126 #define LF_R1 0x0000 127 #define LF_R2 0x0010 128 #define LF_R3 0x0020 129 #define LF_R4 0x0030 130 131 /* ADDER rasterop mode register [9] */ 132 133 #define NORMAL 0x0000 134 #define LINEAR_PATTERN 0x0002 135 #define X_FILL 0x0003 136 #define Y_FILL 0x0007 137 #define BASELINE 0x0008 138 #define HOLE_ENABLE 0x0010 139 #define SRC_1_INDEX_ENABLE 0x0020 140 #define DST_INDEX_ENABLE 0x0040 141 #define DST_WRITE_ENABLE 0x0080 142 143 /* ADDER source 2 size register */ 144 145 #define NO_TILE 0x0080 146 147 /* External registers base addresses */ 148 149 #define CS_UPDATE_MASK 0x0060 150 #define CS_SCROLL_MASK 0x0040 151 152 /* VIPER registers */ 153 154 #define RESOLUTION_MODE 0x0080 155 #define MEMORY_BUS_WIDTH 0x0081 156 #define PLANE_ADDRESS 0x0083 157 #define LU_FUNCTION_R1 0x0084 158 #define LU_FUNCTION_R2 0x0085 159 #define LU_FUNCTION_R3 0x0086 160 #define LU_FUNCTION_R4 0x0087 161 #define MASK_1 0x0088 162 #define MASK_2 0x0089 163 #define SOURCE 0x008a 164 #define SOURCE_Z 0x0000 165 #define BACKGROUND_COLOR 0x008e 166 #define BACKGROUND_COLOR_Z 0x000C 167 #define FOREGROUND_COLOR 0x008f 168 #define FOREGROUND_COLOR_Z 0x0004 169 #define SRC1_OCR_A 0x0090 170 #define SRC2_OCR_A 0x0091 171 #define DST_OCR_A 0x0092 172 #define SRC1_OCR_B 0x0094 173 #define SRC2_OCR_B 0x0095 174 #define DST_OCR_B 0x0096 175 176 /* VIPER scroll registers */ 177 178 #define SCROLL_CONSTANT 0x0082 179 #define SCROLL_FILL 0x008b 180 #define SCROLL_FILL_Z 0x0008 181 #define LEFT_SCROLL_MASK 0x008c 182 #define RIGHT_SCROLL_MASK 0x008d 183 184 /* VIPER register bit definitions */ 185 186 #define EXT_NONE 0x0000 187 #define EXT_SOURCE 0x0001 188 #define EXT_M1_M2 0x0002 189 #define INT_NONE 0x0000 190 #define INT_SOURCE 0x0004 191 #define INT_M1_M2 0x0008 192 #define ID 0x0010 193 #define NO_ID 0x0000 194 #define WAIT 0x0020 195 #define NO_WAIT 0x0000 196 #define BAR_SHIFT_DELAY WAIT 197 #define NO_BAR_SHIFT_DELAY NO_WAIT 198 199 200 /* VIPER logical function unit codes */ 201 202 #define LF_ZEROS 0x0000 203 #define LF_D_XOR_S 0x0006 204 #define LF_SOURCE 0x000A 205 #define LF_D_OR_S 0x000E 206 #define LF_ONES 0x000F 207 #define INV_M1_M2 0x0030 208 #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */ 209 210 /* VIPER scroll register [2] */ 211 212 #define SCROLL_DISABLE 0x0040 213 #define SCROLL_ENABLE 0x0020 214 #define VIPER_LEFT 0x0000 215 #define VIPER_RIGHT 0x0010 216 #define VIPER_UP 0x0040 217 #define VIPER_DOWN 0x0000 218 219 /* Adder scroll register */ 220 221 #define ADDER_UP 0x0000 222 #define ADDER_DOWN 0x1000 223 224 /* Misc scroll definitions */ 225 226 #define UP 0 227 #define DOWN 1 228 #define LEFT 2 229 #define RIGHT 3 230 #define NODIR 4 231 #define SCROLL_VMAX 31 232 #define SCROLL_HMAX 15 233 #define NEW 2 234 #define OLD 1 235 #define BUSY 1 236 #define DRAG 1 237 #define SCROLL 0 238 239 /* miscellaneous defines */ 240 241 #define ALL_PLANES 0xffffffff 242 #define UNITY 0x1fff /* Adder scale factor */ 243 #define MAX_SCREEN_X 1024 244 #define MAX_SCREEN_Y 864 245 #define FONT_HEIGHT 32 246 247 struct adder { 248 249 /* adder control registers */ 250 251 u_short register_address; /* ADDER reg pntr for use by DGA */ 252 u_short request_enable; /* DMA request enables */ 253 u_short interrupt_enable; /* interrupt enables */ 254 u_short status; /* ADDER status bits */ 255 u_short reserved1; /* test function only */ 256 u_short spare1; /* spare address (what else?) */ 257 258 u_short reserved2; /* test function only */ 259 u_short id_data; /* data path to I/D bus */ 260 u_short command; /* ADDER chip command register */ 261 u_short rasterop_mode; /* sets rasterop execution modes */ 262 u_short cmd; /* duplicate path to above cmd reg */ 263 u_short reserved3; /* test function only */ 264 265 /* scroll registers */ 266 267 u_short ID_scroll_data; /* I/D bus scroll data */ 268 u_short ID_scroll_command; /* I/D bus scroll command */ 269 u_short scroll_x_min; /* X scroll min - left boundary */ 270 u_short scroll_x_max; /* X scroll max - right boundary */ 271 u_short scroll_y_min; /* Y scroll min - upper boundary */ 272 u_short scroll_y_max; /* Y scroll max - lower boundary */ 273 u_short pause; /* Y coord to set stat when scanned */ 274 u_short y_offset_pending; /* vertical scroll control */ 275 u_short y_scroll_constant; 276 277 /* update control registers */ 278 279 u_short x_index_pending; /* x pending index */ 280 u_short y_index_pending; /* y pending index */ 281 u_short x_index_new; /* new x index */ 282 u_short y_index_new; /* new y index */ 283 u_short x_index_old; /* old x index */ 284 u_short y_index_old; /* old y index */ 285 u_short x_clip_min; /* left clipping boundary */ 286 u_short x_clip_max; /* right clipping boundary */ 287 u_short y_clip_min; /* upper clipping boundary */ 288 u_short y_clip_max; /* lower clipping boundary */ 289 u_short spare2; /* spare address (another!) */ 290 291 /* rasterop control registers */ 292 293 u_short source_1_dx; /* source #1 x vector */ 294 u_short source_1_dy; /* source #1 y vector*/ 295 u_short source_1_x; /* source #1 x origin */ 296 u_short source_1_y; /* source #1 y origin */ 297 u_short destination_x; /* destination x origin */ 298 u_short destination_y; /* destination y origin */ 299 u_short fast_dest_dx; /* destination x fast vector */ 300 u_short fast_dest_dy; /* destination y fast vector */ 301 u_short slow_dest_dx; /* destination x slow vector */ 302 u_short slow_dest_dy; /* destination y slow vector */ 303 u_short fast_scale; /* scale factor for fast vector */ 304 u_short slow_scale; /* scale factor for slow vector */ 305 u_short source_2_x; /* source #2 x origin */ 306 u_short source_2_y; /* source #2 y origin */ 307 u_short source_2_size; /* source #2 height & width */ 308 u_short error_1; /* error regs (?) */ 309 u_short error_2; 310 311 /* screen format control registers */ 312 313 u_short y_scan_count_0; /* y scan counts for vert timing */ 314 u_short y_scan_count_1; 315 u_short y_scan_count_2; 316 u_short y_scan_count_3; 317 u_short x_scan_conf; /* x scan configuration */ 318 u_short x_limit; 319 u_short y_limit; 320 u_short x_scan_count_0; /* x scan count for horiz timing */ 321 u_short x_scan_count_1; 322 u_short x_scan_count_2; 323 u_short x_scan_count_3; 324 u_short x_scan_count_4; 325 u_short x_scan_count_5; 326 u_short x_scan_count_6; 327 u_short sync_phase_adj; /* sync phase (horiz sync count) */ 328 }; 329 330 /*--------------------- 331 * DUART definitions */ 332 333 /* command definitions */ 334 335 #define EN_RCV 0x01 336 #define DIS_RCV 0x02 337 #define EN_XMT 0x04 338 #define DIS_XMT 0x08 339 #define RESET_M 0x10 340 #define RESET_RCV 0x20 341 #define RESET_XMT 0x30 342 #define RESET_ERR 0x40 343 #define RESET_BD 0x50 344 #define START_BREAK 0x60 345 #define STOP_BREAK 0x70 346 347 /* interupt bit definitions */ 348 349 #define EI_XMT_A 0x01 350 #define EI_RCV_A 0x02 351 #define EI_XMT_B 0x10 352 #define EI_RCV_B 0x20 353 354 #define XMT_RDY_A 0x01 355 #define RCV_RDY_A 0x02 356 #define XMT_RDY_B 0x10 357 #define RCV_RDY_B 0x20 358 359 /* status register bit defintions */ 360 361 #define RCV_RDY 0x01 362 #define FIFO_FULL 0x02 363 #define XMT_RDY 0x04 364 #define XMT_EMT 0x08 365 #define OVER_ERR 0x10 366 #define ERR_PARITY 0x20 367 #define FRAME_ERR 0x40 368 #define RCVD_BREAK 0x80 369 370 371 struct duart { 372 373 /* channel A - LK201 */ 374 375 short modeA; /* ch.A mode reg (read/write) */ 376 short statusA; /* ch.A status reg (read) */ 377 #define clkselA statusA /* ch.A clock slect reg (write) */ 378 short cmdA; /* ch.A command reg (write) */ 379 short dataA; /* rcv/xmt data ch.A (read/write) */ 380 short inchng; /* input change state reg (read) */ 381 #define auxctl inchng /* auxiliary control reg (write) */ 382 short istatus; /* interrupt status reg (read) */ 383 #define imask istatus /* interrupt mask reg (write) */ 384 short CThi; /* counter/timer hi byte (read) */ 385 #define CTRhi CThi /* counter/timer hi reg (write) */ 386 short CTlo; /* counter/timer lo byte (read) */ 387 #define CTRlo CTlo /* counter/timer lo reg (write) */ 388 389 /* channel B - pointing device */ 390 391 short modeB; /* ch.B mode reg (read/write) */ 392 short statusB; /* ch.B status reg (read) */ 393 #define clkselB statusB /* ch.B clock select reg (write) */ 394 short cmdB; /* ch.B command reg (write) */ 395 short dataB; /* ch.B rcv/xmt data (read/write) */ 396 short rsrvd; 397 short inport; /* input port (read) */ 398 #define outconf inport /* output port config reg (write) */ 399 short strctr; /* start counter command (read) */ 400 #define setbits setctr /* output bits set command (write) */ 401 short stpctr; /* stop counter command (read) */ 402 #define resetbits stpctr /* output bits reset cmd (write) */ 403 404 }; 405 406 /* Driver and data specific structure */ 407 struct qd_softc { 408 long sc_flags; /* Flags */ 409 long sc_category_flags; /* Category flags */ 410 u_long sc_softcnt; /* Soft error count total */ 411 u_long sc_hardcnt; /* Hard error count total */ 412 char sc_device[DEV_SIZE]; /* Device type string */ 413 }; 414