1 2 /* 3 * @(#)qdreg.h 1.2 Berkeley 08/07/87 4 * @(#)qdreg.h 1.5 (ULTRIX) 5/21/86 5 */ 6 7 /************************************************************************ 8 * * 9 * Copyright (c) 1985, 1986 by * 10 * Digital Equipment Corporation, Maynard, MA * 11 * All rights reserved. * 12 * * 13 * This software is furnished under a license and may be used and * 14 * copied only in accordance with the terms of such license and * 15 * with the inclusion of the above copyright notice. This * 16 * software or any other copies thereof may not be provided or * 17 * otherwise made available to any other person. No title to and * 18 * ownership of the software is hereby transferred. * 19 * * 20 * The information in this software is subject to change without * 21 * notice and should not be construed as a commitment by Digital * 22 * Equipment Corporation. * 23 * * 24 * Digital assumes no responsibility for the use or reliability * 25 * of its software on equipment which is not supplied by Digital. * 26 * * 27 ************************************************************************/ 28 29 /* 30 * qdreg.h 31 * 32 * Modification history 33 * 34 * QDSS registers/data structures and definitions 35 * 36 * 4-Feb-85 - longo 37 * 38 * Created file. 39 * 40 * 18-Mar-85 - longo 41 * 42 * Added DGA CSR bit definitions. 43 * 44 * 20-Mar-85 - longo 45 * 46 * Revised register naming conventions. 47 * 48 * 28-Mar-85 - longo 49 * 50 * Added DUART register struct. 51 * 52 * 19-Apr-85 - longo 53 * 54 * Removed "base" entry from 'struct qdmap'. 55 * 56 * 1-May-85 - longo 57 * 58 * Changed layout of DUART device map data structure and 59 * added command/intrpt/status bit definitions. 60 * 61 * 4-Jun-85 - longo 62 * 63 * Added bit definitions for ADDER registers. 64 * 65 * 10-Sep-85 - longo 66 * 67 * Changed dga struct DMA address entry names. 68 * 69 * 25-Sep-85 - longo 70 * 71 * Changed ADDER status bit constant. 72 * 73 * 20-May-86 - ricky palmer 74 * 75 * Added new DEVIOCGET ioctl request code. V2.0 76 * 77 */ 78 79 /* Dragon ADDER reg map */ 80 /* ADDER register bit definitions */ 81 /* Y_SCROLL_CONSTANT */ 82 83 #define SCROLL_ERASE 0x2000 84 #define ADDER_SCROLL_DOWN 0x1000 85 86 /* ADDER status and interrupt enable registers [1], [2], [3] */ 87 88 #define DISABLE 0x0000 89 #define PAUSE_COMPLETE 0x0001 90 #define FRAME_SYNC 0x0002 91 #define INIT_COMPLETE 0x0004 92 #define RASTEROP_COMPLETE 0x0008 93 94 #define ADDRESS_COMPLETE 0x0010 95 #define RX_READY 0x0020 96 #define TX_READY 0x0040 97 #define ID_SCROLL_READY 0x0080 98 99 #define TOP_CLIP 0x0100 100 #define BOTTOM_CLIP 0x0200 101 #define LEFT_CLIP 0x0400 102 #define RIGHT_CLIP 0x0800 103 #define NO_CLIP 0x1000 104 #define VSYNC 0x2000 105 106 /* ADDER command register [8], [10] */ 107 108 #define OCR_zero 0x0000 109 #define Z_BLOCK0 0x0000 110 #define OCRA 0x0000 111 #define OCRB 0x0004 112 #define RASTEROP 0x02c0 113 #define PBT 0x03c0 114 #define BTPZ 0x0bb0 115 #define PTBZ 0x07a0 116 #define DTE 0x0400 117 #define S1E 0x0800 118 #define S2E 0x1000 119 #define VIPER_Z_LOAD 0x01A0 120 #define ID_LOAD 0x0100 121 #define CANCEL 0x0000 122 #define LF_R1 0x0000 123 #define LF_R2 0x0010 124 #define LF_R3 0x0020 125 #define LF_R4 0x0030 126 127 /* ADDER rasterop mode register [9] */ 128 129 #define NORMAL 0x0000 130 #define LINEAR_PATTERN 0x0002 131 #define X_FILL 0x0003 132 #define Y_FILL 0x0007 133 #define BASELINE 0x0008 134 #define HOLE_ENABLE 0x0010 135 #define SRC_1_INDEX_ENABLE 0x0020 136 #define DST_INDEX_ENABLE 0x0040 137 #define DST_WRITE_ENABLE 0x0080 138 139 /* ADDER source 2 size register */ 140 141 #define NO_TILE 0x0080 142 143 /* External registers base addresses */ 144 145 #define CS_UPDATE_MASK 0x0060 146 #define CS_SCROLL_MASK 0x0040 147 148 /* VIPER registers */ 149 150 #define RESOLUTION_MODE 0x0080 151 #define MEMORY_BUS_WIDTH 0x0081 152 #define PLANE_ADDRESS 0x0083 153 #define LU_FUNCTION_R1 0x0084 154 #define LU_FUNCTION_R2 0x0085 155 #define LU_FUNCTION_R3 0x0086 156 #define LU_FUNCTION_R4 0x0087 157 #define MASK_1 0x0088 158 #define MASK_2 0x0089 159 #define SOURCE 0x008a 160 #define SOURCE_Z 0x0000 161 #define BACKGROUND_COLOR 0x008e 162 #define BACKGROUND_COLOR_Z 0x000C 163 #define FOREGROUND_COLOR 0x008f 164 #define FOREGROUND_COLOR_Z 0x0004 165 #define SRC1_OCR_A 0x0090 166 #define SRC2_OCR_A 0x0091 167 #define DST_OCR_A 0x0092 168 #define SRC1_OCR_B 0x0094 169 #define SRC2_OCR_B 0x0095 170 #define DST_OCR_B 0x0096 171 172 /* VIPER scroll registers */ 173 174 #define SCROLL_CONSTANT 0x0082 175 #define SCROLL_FILL 0x008b 176 #define SCROLL_FILL_Z 0x0008 177 #define LEFT_SCROLL_MASK 0x008c 178 #define RIGHT_SCROLL_MASK 0x008d 179 180 /* VIPER register bit definitions */ 181 182 #define EXT_NONE 0x0000 183 #define EXT_SOURCE 0x0001 184 #define EXT_M1_M2 0x0002 185 #define INT_NONE 0x0000 186 #define INT_SOURCE 0x0004 187 #define INT_M1_M2 0x0008 188 #define ID 0x0010 189 #define NO_ID 0x0000 190 #define WAIT 0x0020 191 #define NO_WAIT 0x0000 192 #define BAR_SHIFT_DELAY WAIT 193 #define NO_BAR_SHIFT_DELAY NO_WAIT 194 195 196 /* VIPER logical function unit codes */ 197 198 #define LF_ZEROS 0x0000 199 #define LF_D_XOR_S 0x0006 200 #define LF_SOURCE 0x000A 201 #define LF_D_OR_S 0x000E 202 #define LF_ONES 0x000F 203 #define INV_M1_M2 0x0030 204 #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */ 205 206 /* VIPER scroll register [2] */ 207 208 #define SCROLL_DISABLE 0x0040 209 #define SCROLL_ENABLE 0x0020 210 #define VIPER_LEFT 0x0000 211 #define VIPER_RIGHT 0x0010 212 #define VIPER_UP 0x0040 213 #define VIPER_DOWN 0x0000 214 215 /* Adder scroll register */ 216 217 #define ADDER_UP 0x0000 218 #define ADDER_DOWN 0x1000 219 220 /* Misc scroll definitions */ 221 222 #define UP 0 223 #define DOWN 1 224 #define LEFT 2 225 #define RIGHT 3 226 #define NODIR 4 227 #define SCROLL_VMAX 31 228 #define SCROLL_HMAX 15 229 #define NEW 2 230 #define OLD 1 231 #define BUSY 1 232 #define DRAG 1 233 #define SCROLL 0 234 235 /* miscellaneous defines */ 236 237 #define ALL_PLANES 0xffffffff 238 #define UNITY 0x1fff /* Adder scale factor */ 239 #define MAX_SCREEN_X 1024 240 #define MAX_SCREEN_Y 864 241 #define FONT_HEIGHT 32 242 243 struct adder { 244 245 /* adder control registers */ 246 247 u_short register_address; /* ADDER reg pntr for use by DGA */ 248 u_short request_enable; /* DMA request enables */ 249 u_short interrupt_enable; /* interrupt enables */ 250 u_short status; /* ADDER status bits */ 251 u_short reserved1; /* test function only */ 252 u_short spare1; /* spare address (what else?) */ 253 254 u_short reserved2; /* test function only */ 255 u_short id_data; /* data path to I/D bus */ 256 u_short command; /* ADDER chip command register */ 257 u_short rasterop_mode; /* sets rasterop execution modes */ 258 u_short cmd; /* duplicate path to above cmd reg */ 259 u_short reserved3; /* test function only */ 260 261 /* scroll registers */ 262 263 u_short ID_scroll_data; /* I/D bus scroll data */ 264 u_short ID_scroll_command; /* I/D bus scroll command */ 265 u_short scroll_x_min; /* X scroll min - left boundary */ 266 u_short scroll_x_max; /* X scroll max - right boundary */ 267 u_short scroll_y_min; /* Y scroll min - upper boundary */ 268 u_short scroll_y_max; /* Y scroll max - lower boundary */ 269 u_short pause; /* Y coord to set stat when scanned */ 270 u_short y_offset_pending; /* vertical scroll control */ 271 u_short y_scroll_constant; 272 273 /* update control registers */ 274 275 u_short x_index_pending; /* x pending index */ 276 u_short y_index_pending; /* y pending index */ 277 u_short x_index_new; /* new x index */ 278 u_short y_index_new; /* new y index */ 279 u_short x_index_old; /* old x index */ 280 u_short y_index_old; /* old y index */ 281 u_short x_clip_min; /* left clipping boundary */ 282 u_short x_clip_max; /* right clipping boundary */ 283 u_short y_clip_min; /* upper clipping boundary */ 284 u_short y_clip_max; /* lower clipping boundary */ 285 u_short spare2; /* spare address (another!) */ 286 287 /* rasterop control registers */ 288 289 u_short source_1_dx; /* source #1 x vector */ 290 u_short source_1_dy; /* source #1 y vector*/ 291 u_short source_1_x; /* source #1 x origin */ 292 u_short source_1_y; /* source #1 y origin */ 293 u_short destination_x; /* destination x origin */ 294 u_short destination_y; /* destination y origin */ 295 u_short fast_dest_dx; /* destination x fast vector */ 296 u_short fast_dest_dy; /* destination y fast vector */ 297 u_short slow_dest_dx; /* destination x slow vector */ 298 u_short slow_dest_dy; /* destination y slow vector */ 299 u_short fast_scale; /* scale factor for fast vector */ 300 u_short slow_scale; /* scale factor for slow vector */ 301 u_short source_2_x; /* source #2 x origin */ 302 u_short source_2_y; /* source #2 y origin */ 303 u_short source_2_size; /* source #2 height & width */ 304 u_short error_1; /* error regs (?) */ 305 u_short error_2; 306 307 /* screen format control registers */ 308 309 u_short y_scan_count_0; /* y scan counts for vert timing */ 310 u_short y_scan_count_1; 311 u_short y_scan_count_2; 312 u_short y_scan_count_3; 313 u_short x_scan_conf; /* x scan configuration */ 314 u_short x_limit; 315 u_short y_limit; 316 u_short x_scan_count_0; /* x scan count for horiz timing */ 317 u_short x_scan_count_1; 318 u_short x_scan_count_2; 319 u_short x_scan_count_3; 320 u_short x_scan_count_4; 321 u_short x_scan_count_5; 322 u_short x_scan_count_6; 323 u_short sync_phase_adj; /* sync phase (horiz sync count) */ 324 }; 325 326 /*--------------------- 327 * DUART definitions */ 328 329 /* command definitions */ 330 331 #define EN_RCV 0x01 332 #define DIS_RCV 0x02 333 #define EN_XMT 0x04 334 #define DIS_XMT 0x08 335 #define RESET_M 0x10 336 #define RESET_RCV 0x20 337 #define RESET_XMT 0x30 338 #define RESET_ERR 0x40 339 #define RESET_BD 0x50 340 #define START_BREAK 0x60 341 #define STOP_BREAK 0x70 342 343 /* interupt bit definitions */ 344 345 #define EI_XMT_A 0x01 346 #define EI_RCV_A 0x02 347 #define EI_XMT_B 0x10 348 #define EI_RCV_B 0x20 349 350 #define XMT_RDY_A 0x01 351 #define RCV_RDY_A 0x02 352 #define XMT_RDY_B 0x10 353 #define RCV_RDY_B 0x20 354 355 /* status register bit defintions */ 356 357 #define RCV_RDY 0x01 358 #define FIFO_FULL 0x02 359 #define XMT_RDY 0x04 360 #define XMT_EMT 0x08 361 #define OVER_ERR 0x10 362 #define ERR_PARITY 0x20 363 #define FRAME_ERR 0x40 364 #define RCVD_BREAK 0x80 365 366 367 struct duart { 368 369 /* channel A - LK201 */ 370 371 short modeA; /* ch.A mode reg (read/write) */ 372 short statusA; /* ch.A status reg (read) */ 373 #define clkselA statusA /* ch.A clock slect reg (write) */ 374 short cmdA; /* ch.A command reg (write) */ 375 short dataA; /* rcv/xmt data ch.A (read/write) */ 376 short inchng; /* input change state reg (read) */ 377 #define auxctl inchng /* auxiliary control reg (write) */ 378 short istatus; /* interrupt status reg (read) */ 379 #define imask istatus /* interrupt mask reg (write) */ 380 short CThi; /* counter/timer hi byte (read) */ 381 #define CTRhi CThi /* counter/timer hi reg (write) */ 382 short CTlo; /* counter/timer lo byte (read) */ 383 #define CTRlo CTlo /* counter/timer lo reg (write) */ 384 385 /* channel B - pointing device */ 386 387 short modeB; /* ch.B mode reg (read/write) */ 388 short statusB; /* ch.B status reg (read) */ 389 #define clkselB statusB /* ch.B clock select reg (write) */ 390 short cmdB; /* ch.B command reg (write) */ 391 short dataB; /* ch.B rcv/xmt data (read/write) */ 392 short rsrvd; 393 short inport; /* input port (read) */ 394 #define outconf inport /* output port config reg (write) */ 395 short strctr; /* start counter command (read) */ 396 #define setbits setctr /* output bits set command (write) */ 397 short stpctr; /* stop counter command (read) */ 398 #define resetbits stpctr /* output bits reset cmd (write) */ 399 400 }; 401 402 /* Driver and data specific structure */ 403 #define DEV_SIZE 8 /* from ultrix - i don't see where its used ! - marc */ 404 struct qd_softc { 405 long sc_flags; /* Flags */ 406 long sc_category_flags; /* Category flags */ 407 u_long sc_softcnt; /* Soft error count total */ 408 u_long sc_hardcnt; /* Hard error count total */ 409 char sc_device[DEV_SIZE]; /* Device type string */ 410 }; 411