1*49567Sbostic /*- 2*49567Sbostic * Copyright (c) 1982, 1986 The Regents of the University of California. 3*49567Sbostic * All rights reserved. 434543Smarc * 5*49567Sbostic * %sccs.include.redist.c% 6*49567Sbostic * 7*49567Sbostic * @(#)qdreg.h 7.1 (Berkeley) 05/09/91 831809Smarc */ 931809Smarc 1031809Smarc /************************************************************************ 1131809Smarc * * 1231809Smarc * Copyright (c) 1985, 1986 by * 1331809Smarc * Digital Equipment Corporation, Maynard, MA * 1431809Smarc * All rights reserved. * 1531809Smarc * * 1631809Smarc * This software is furnished under a license and may be used and * 1731809Smarc * copied only in accordance with the terms of such license and * 1831809Smarc * with the inclusion of the above copyright notice. This * 1931809Smarc * software or any other copies thereof may not be provided or * 2031809Smarc * otherwise made available to any other person. No title to and * 2131809Smarc * ownership of the software is hereby transferred. * 2231809Smarc * * 2331809Smarc * The information in this software is subject to change without * 2431809Smarc * notice and should not be construed as a commitment by Digital * 2531809Smarc * Equipment Corporation. * 2631809Smarc * * 2731809Smarc * Digital assumes no responsibility for the use or reliability * 2831809Smarc * of its software on equipment which is not supplied by Digital. * 2931809Smarc * * 3031809Smarc ************************************************************************/ 3131809Smarc 3231809Smarc /* Dragon ADDER reg map */ 3331809Smarc /* ADDER register bit definitions */ 3431809Smarc /* Y_SCROLL_CONSTANT */ 3531809Smarc 3631809Smarc #define SCROLL_ERASE 0x2000 3731809Smarc #define ADDER_SCROLL_DOWN 0x1000 3831809Smarc 3931809Smarc /* ADDER status and interrupt enable registers [1], [2], [3] */ 4031809Smarc 4131809Smarc #define DISABLE 0x0000 4231809Smarc #define PAUSE_COMPLETE 0x0001 4331809Smarc #define FRAME_SYNC 0x0002 4431809Smarc #define INIT_COMPLETE 0x0004 4531809Smarc #define RASTEROP_COMPLETE 0x0008 4631809Smarc 4731809Smarc #define ADDRESS_COMPLETE 0x0010 4831809Smarc #define RX_READY 0x0020 4931809Smarc #define TX_READY 0x0040 5031809Smarc #define ID_SCROLL_READY 0x0080 5131809Smarc 5231809Smarc #define TOP_CLIP 0x0100 5331809Smarc #define BOTTOM_CLIP 0x0200 5431809Smarc #define LEFT_CLIP 0x0400 5531809Smarc #define RIGHT_CLIP 0x0800 5631809Smarc #define NO_CLIP 0x1000 5731809Smarc #define VSYNC 0x2000 5831809Smarc 5931809Smarc /* ADDER command register [8], [10] */ 6031809Smarc 6131809Smarc #define OCR_zero 0x0000 6231809Smarc #define Z_BLOCK0 0x0000 6331809Smarc #define OCRA 0x0000 6431809Smarc #define OCRB 0x0004 6531809Smarc #define RASTEROP 0x02c0 6631809Smarc #define PBT 0x03c0 6731809Smarc #define BTPZ 0x0bb0 6831809Smarc #define PTBZ 0x07a0 6931809Smarc #define DTE 0x0400 7031809Smarc #define S1E 0x0800 7131809Smarc #define S2E 0x1000 7231809Smarc #define VIPER_Z_LOAD 0x01A0 7331809Smarc #define ID_LOAD 0x0100 7431809Smarc #define CANCEL 0x0000 7531809Smarc #define LF_R1 0x0000 7631809Smarc #define LF_R2 0x0010 7731809Smarc #define LF_R3 0x0020 7831809Smarc #define LF_R4 0x0030 7931809Smarc 8031809Smarc /* ADDER rasterop mode register [9] */ 8131809Smarc 8231809Smarc #define NORMAL 0x0000 8331809Smarc #define LINEAR_PATTERN 0x0002 8431809Smarc #define X_FILL 0x0003 8531809Smarc #define Y_FILL 0x0007 8631809Smarc #define BASELINE 0x0008 8731809Smarc #define HOLE_ENABLE 0x0010 8831809Smarc #define SRC_1_INDEX_ENABLE 0x0020 8931809Smarc #define DST_INDEX_ENABLE 0x0040 9031809Smarc #define DST_WRITE_ENABLE 0x0080 9131809Smarc 9231809Smarc /* ADDER source 2 size register */ 9331809Smarc 9431809Smarc #define NO_TILE 0x0080 9531809Smarc 9631809Smarc /* External registers base addresses */ 9731809Smarc 9831809Smarc #define CS_UPDATE_MASK 0x0060 9931809Smarc #define CS_SCROLL_MASK 0x0040 10031809Smarc 10131809Smarc /* VIPER registers */ 10231809Smarc 10331809Smarc #define RESOLUTION_MODE 0x0080 10431809Smarc #define MEMORY_BUS_WIDTH 0x0081 10531809Smarc #define PLANE_ADDRESS 0x0083 10631809Smarc #define LU_FUNCTION_R1 0x0084 10731809Smarc #define LU_FUNCTION_R2 0x0085 10831809Smarc #define LU_FUNCTION_R3 0x0086 10931809Smarc #define LU_FUNCTION_R4 0x0087 11031809Smarc #define MASK_1 0x0088 11131809Smarc #define MASK_2 0x0089 11231809Smarc #define SOURCE 0x008a 11331809Smarc #define SOURCE_Z 0x0000 11431809Smarc #define BACKGROUND_COLOR 0x008e 11531809Smarc #define BACKGROUND_COLOR_Z 0x000C 11631809Smarc #define FOREGROUND_COLOR 0x008f 11731809Smarc #define FOREGROUND_COLOR_Z 0x0004 11831809Smarc #define SRC1_OCR_A 0x0090 11931809Smarc #define SRC2_OCR_A 0x0091 12031809Smarc #define DST_OCR_A 0x0092 12131809Smarc #define SRC1_OCR_B 0x0094 12231809Smarc #define SRC2_OCR_B 0x0095 12331809Smarc #define DST_OCR_B 0x0096 12431809Smarc 12531809Smarc /* VIPER scroll registers */ 12631809Smarc 12731809Smarc #define SCROLL_CONSTANT 0x0082 12831809Smarc #define SCROLL_FILL 0x008b 12931809Smarc #define SCROLL_FILL_Z 0x0008 13031809Smarc #define LEFT_SCROLL_MASK 0x008c 13131809Smarc #define RIGHT_SCROLL_MASK 0x008d 13231809Smarc 13331809Smarc /* VIPER register bit definitions */ 13431809Smarc 13531809Smarc #define EXT_NONE 0x0000 13631809Smarc #define EXT_SOURCE 0x0001 13731809Smarc #define EXT_M1_M2 0x0002 13831809Smarc #define INT_NONE 0x0000 13931809Smarc #define INT_SOURCE 0x0004 14031809Smarc #define INT_M1_M2 0x0008 14131809Smarc #define ID 0x0010 14231809Smarc #define NO_ID 0x0000 14331809Smarc #define WAIT 0x0020 14431809Smarc #define NO_WAIT 0x0000 14531809Smarc #define BAR_SHIFT_DELAY WAIT 14631809Smarc #define NO_BAR_SHIFT_DELAY NO_WAIT 14731809Smarc 14831809Smarc 14931809Smarc /* VIPER logical function unit codes */ 15031809Smarc 15131809Smarc #define LF_ZEROS 0x0000 15231809Smarc #define LF_D_XOR_S 0x0006 15331809Smarc #define LF_SOURCE 0x000A 15431809Smarc #define LF_D_OR_S 0x000E 15531809Smarc #define LF_ONES 0x000F 15631809Smarc #define INV_M1_M2 0x0030 15731809Smarc #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */ 15831809Smarc 15931809Smarc /* VIPER scroll register [2] */ 16031809Smarc 16131809Smarc #define SCROLL_DISABLE 0x0040 16231809Smarc #define SCROLL_ENABLE 0x0020 16331809Smarc #define VIPER_LEFT 0x0000 16431809Smarc #define VIPER_RIGHT 0x0010 16531809Smarc #define VIPER_UP 0x0040 16631809Smarc #define VIPER_DOWN 0x0000 16731809Smarc 16831809Smarc /* Adder scroll register */ 16931809Smarc 17031809Smarc #define ADDER_UP 0x0000 17131809Smarc #define ADDER_DOWN 0x1000 17231809Smarc 17331809Smarc /* Misc scroll definitions */ 17431809Smarc 17531809Smarc #define UP 0 17631809Smarc #define DOWN 1 17731809Smarc #define LEFT 2 17831809Smarc #define RIGHT 3 17931809Smarc #define NODIR 4 18031809Smarc #define SCROLL_VMAX 31 18131809Smarc #define SCROLL_HMAX 15 18231809Smarc #define NEW 2 18331809Smarc #define OLD 1 18431809Smarc #define BUSY 1 18531809Smarc #define DRAG 1 18631809Smarc #define SCROLL 0 18731809Smarc 18831809Smarc /* miscellaneous defines */ 18931809Smarc 19031809Smarc #define ALL_PLANES 0xffffffff 19131809Smarc #define UNITY 0x1fff /* Adder scale factor */ 19231809Smarc #define MAX_SCREEN_X 1024 19331809Smarc #define MAX_SCREEN_Y 864 19431809Smarc #define FONT_HEIGHT 32 19531809Smarc 19631809Smarc struct adder { 19731809Smarc 19831809Smarc /* adder control registers */ 19931809Smarc 20031809Smarc u_short register_address; /* ADDER reg pntr for use by DGA */ 20131809Smarc u_short request_enable; /* DMA request enables */ 20231809Smarc u_short interrupt_enable; /* interrupt enables */ 20331809Smarc u_short status; /* ADDER status bits */ 20431809Smarc u_short reserved1; /* test function only */ 20531809Smarc u_short spare1; /* spare address (what else?) */ 20631809Smarc 20731809Smarc u_short reserved2; /* test function only */ 20831809Smarc u_short id_data; /* data path to I/D bus */ 20931809Smarc u_short command; /* ADDER chip command register */ 21031809Smarc u_short rasterop_mode; /* sets rasterop execution modes */ 21131809Smarc u_short cmd; /* duplicate path to above cmd reg */ 21231809Smarc u_short reserved3; /* test function only */ 21331809Smarc 21431809Smarc /* scroll registers */ 21531809Smarc 21631809Smarc u_short ID_scroll_data; /* I/D bus scroll data */ 21731809Smarc u_short ID_scroll_command; /* I/D bus scroll command */ 21831809Smarc u_short scroll_x_min; /* X scroll min - left boundary */ 21931809Smarc u_short scroll_x_max; /* X scroll max - right boundary */ 22031809Smarc u_short scroll_y_min; /* Y scroll min - upper boundary */ 22131809Smarc u_short scroll_y_max; /* Y scroll max - lower boundary */ 22231809Smarc u_short pause; /* Y coord to set stat when scanned */ 22331809Smarc u_short y_offset_pending; /* vertical scroll control */ 22431809Smarc u_short y_scroll_constant; 22531809Smarc 22631809Smarc /* update control registers */ 22731809Smarc 22831809Smarc u_short x_index_pending; /* x pending index */ 22931809Smarc u_short y_index_pending; /* y pending index */ 23031809Smarc u_short x_index_new; /* new x index */ 23131809Smarc u_short y_index_new; /* new y index */ 23231809Smarc u_short x_index_old; /* old x index */ 23331809Smarc u_short y_index_old; /* old y index */ 23431809Smarc u_short x_clip_min; /* left clipping boundary */ 23531809Smarc u_short x_clip_max; /* right clipping boundary */ 23631809Smarc u_short y_clip_min; /* upper clipping boundary */ 23731809Smarc u_short y_clip_max; /* lower clipping boundary */ 23831809Smarc u_short spare2; /* spare address (another!) */ 23931809Smarc 24031809Smarc /* rasterop control registers */ 24131809Smarc 24231809Smarc u_short source_1_dx; /* source #1 x vector */ 24331809Smarc u_short source_1_dy; /* source #1 y vector*/ 24431809Smarc u_short source_1_x; /* source #1 x origin */ 24531809Smarc u_short source_1_y; /* source #1 y origin */ 24631809Smarc u_short destination_x; /* destination x origin */ 24731809Smarc u_short destination_y; /* destination y origin */ 24831809Smarc u_short fast_dest_dx; /* destination x fast vector */ 24931809Smarc u_short fast_dest_dy; /* destination y fast vector */ 25031809Smarc u_short slow_dest_dx; /* destination x slow vector */ 25131809Smarc u_short slow_dest_dy; /* destination y slow vector */ 25231809Smarc u_short fast_scale; /* scale factor for fast vector */ 25331809Smarc u_short slow_scale; /* scale factor for slow vector */ 25431809Smarc u_short source_2_x; /* source #2 x origin */ 25531809Smarc u_short source_2_y; /* source #2 y origin */ 25631809Smarc u_short source_2_size; /* source #2 height & width */ 25731809Smarc u_short error_1; /* error regs (?) */ 25831809Smarc u_short error_2; 25931809Smarc 26031809Smarc /* screen format control registers */ 26131809Smarc 26231809Smarc u_short y_scan_count_0; /* y scan counts for vert timing */ 26331809Smarc u_short y_scan_count_1; 26431809Smarc u_short y_scan_count_2; 26531809Smarc u_short y_scan_count_3; 26631809Smarc u_short x_scan_conf; /* x scan configuration */ 26731809Smarc u_short x_limit; 26831809Smarc u_short y_limit; 26931809Smarc u_short x_scan_count_0; /* x scan count for horiz timing */ 27031809Smarc u_short x_scan_count_1; 27131809Smarc u_short x_scan_count_2; 27231809Smarc u_short x_scan_count_3; 27331809Smarc u_short x_scan_count_4; 27431809Smarc u_short x_scan_count_5; 27531809Smarc u_short x_scan_count_6; 27631809Smarc u_short sync_phase_adj; /* sync phase (horiz sync count) */ 27731809Smarc }; 27831809Smarc 27931809Smarc /*--------------------- 28031809Smarc * DUART definitions */ 28131809Smarc 28231809Smarc /* command definitions */ 28331809Smarc 28431809Smarc #define EN_RCV 0x01 28531809Smarc #define DIS_RCV 0x02 28631809Smarc #define EN_XMT 0x04 28731809Smarc #define DIS_XMT 0x08 28831809Smarc #define RESET_M 0x10 28931809Smarc #define RESET_RCV 0x20 29031809Smarc #define RESET_XMT 0x30 29131809Smarc #define RESET_ERR 0x40 29231809Smarc #define RESET_BD 0x50 29331809Smarc #define START_BREAK 0x60 29431809Smarc #define STOP_BREAK 0x70 29531809Smarc 29631809Smarc /* interupt bit definitions */ 29731809Smarc 29831809Smarc #define EI_XMT_A 0x01 29931809Smarc #define EI_RCV_A 0x02 30031809Smarc #define EI_XMT_B 0x10 30131809Smarc #define EI_RCV_B 0x20 30231809Smarc 30331809Smarc #define XMT_RDY_A 0x01 30431809Smarc #define RCV_RDY_A 0x02 30531809Smarc #define XMT_RDY_B 0x10 30631809Smarc #define RCV_RDY_B 0x20 30731809Smarc 30831809Smarc /* status register bit defintions */ 30931809Smarc 31031809Smarc #define RCV_RDY 0x01 31131809Smarc #define FIFO_FULL 0x02 31231809Smarc #define XMT_RDY 0x04 31331809Smarc #define XMT_EMT 0x08 31431809Smarc #define OVER_ERR 0x10 31531809Smarc #define ERR_PARITY 0x20 31631809Smarc #define FRAME_ERR 0x40 31731809Smarc #define RCVD_BREAK 0x80 31831809Smarc 31931809Smarc 32031809Smarc struct duart { 32131809Smarc 32231809Smarc /* channel A - LK201 */ 32331809Smarc 32431809Smarc short modeA; /* ch.A mode reg (read/write) */ 32531809Smarc short statusA; /* ch.A status reg (read) */ 32631809Smarc #define clkselA statusA /* ch.A clock slect reg (write) */ 32731809Smarc short cmdA; /* ch.A command reg (write) */ 32831809Smarc short dataA; /* rcv/xmt data ch.A (read/write) */ 32931809Smarc short inchng; /* input change state reg (read) */ 33031809Smarc #define auxctl inchng /* auxiliary control reg (write) */ 33131809Smarc short istatus; /* interrupt status reg (read) */ 33231809Smarc #define imask istatus /* interrupt mask reg (write) */ 33331809Smarc short CThi; /* counter/timer hi byte (read) */ 33431809Smarc #define CTRhi CThi /* counter/timer hi reg (write) */ 33531809Smarc short CTlo; /* counter/timer lo byte (read) */ 33631809Smarc #define CTRlo CTlo /* counter/timer lo reg (write) */ 33731809Smarc 33831809Smarc /* channel B - pointing device */ 33931809Smarc 34031809Smarc short modeB; /* ch.B mode reg (read/write) */ 34131809Smarc short statusB; /* ch.B status reg (read) */ 34231809Smarc #define clkselB statusB /* ch.B clock select reg (write) */ 34331809Smarc short cmdB; /* ch.B command reg (write) */ 34431809Smarc short dataB; /* ch.B rcv/xmt data (read/write) */ 34531809Smarc short rsrvd; 34631809Smarc short inport; /* input port (read) */ 34731809Smarc #define outconf inport /* output port config reg (write) */ 34831809Smarc short strctr; /* start counter command (read) */ 34931809Smarc #define setbits setctr /* output bits set command (write) */ 35031809Smarc short stpctr; /* stop counter command (read) */ 35131809Smarc #define resetbits stpctr /* output bits reset cmd (write) */ 35231809Smarc 35331809Smarc }; 354