1*7623Ssam /* psreg.h 4.2 82/08/01 */ 27292Ssam 37292Ssam 47292Ssam /* 57292Ssam * The Real Nitty Gritty Device Registers 67292Ssam */ 77292Ssam 87292Ssam struct psdevice { 97292Ssam short int ps_data; /* data register */ 107292Ssam short int ps_addr; /* address register */ 117292Ssam short int ps_wcount; /* word count register */ 127292Ssam short int ps_busaddr; /* unibus address register */ 137292Ssam short int ps_iostat; /* io status register */ 147292Ssam }; 157292Ssam 167292Ssam /* 177292Ssam * Possible ioctl's 187292Ssam */ 19*7623Ssam #define PSIOAUTOREFRESH _IO(p, 0) /* auto refresh */ 20*7623Ssam #define PSIOSINGLEREFRESH _IO(p, 1) /* single refresh */ 21*7623Ssam #define PSIOAUTOMAP _IO(p, 2) /* auto map */ 22*7623Ssam #define PSIOSINGLEMAP _IO(p, 3) /* single map */ 23*7623Ssam #define PSIODOUBLEBUFFER _IO(p, 4) /* double buffer */ 24*7623Ssam #define PSIOSINGLEBUFFER _IO(p, 5) /* single buffer */ 25*7623Ssam #define PSIOWAITREFRESH _IO(p, 6) /* await refresh */ 26*7623Ssam #define PSIOWAITMAP _IO(p, 7) /* await map */ 27*7623Ssam #define PSIOWAITHIT _IO(p, 8) /* await hit */ 28*7623Ssam #define PSIOSTOPREFRESH _IO(p, 9) /* stop refresh */ 29*7623Ssam #define PSIOSTOPMAP _IO(p,10) /* stop map */ 30*7623Ssam #define PSIOGETADDR _IOR(p,11, int) /* get Unibus address */ 317292Ssam 327292Ssam /* 337292Ssam * Picture system io status register bits 347292Ssam */ 357292Ssam 367292Ssam #define DIOREADY 0100000 377292Ssam #define PSAHOLD 040000 387292Ssam #define PSRESET 020000 397292Ssam #define DIORESET 010000 407292Ssam #define DMARESET 04000 417292Ssam #define PSIE 0400 427292Ssam #define DMAREADY 0200 437292Ssam #define DMAIE 0100 447292Ssam #define PASSIVE 010 457292Ssam #define DMAIN 04 467292Ssam #define NEXEM 02 477292Ssam #define GO 01 487292Ssam 497292Ssam /* 507292Ssam * Picture system memory mapping control registers: SCB 0177400-0177410 517292Ssam */ 527292Ssam 537292Ssam #define EXMMR_DMA 0177400 547292Ssam #define EXMMR_DIO 0177404 557292Ssam #define EXMMR_RC 0177405 567292Ssam #define EXMMR_MAPOUT 0177406 577292Ssam #define EXMMR_MAPIN 0177407 587292Ssam #define EXMSR 0177410 597292Ssam 607292Ssam /* 617292Ssam * Extended memory status register bits 627292Ssam */ 637292Ssam 647292Ssam #define DBERROR 0100000 657292Ssam #define SBERROR 040000 667292Ssam #define MEMREADY 0200 677292Ssam #define DBIE 0100 687292Ssam #define MMENBL 02 697292Ssam #define INITMEM 01 707292Ssam 717292Ssam /* 727292Ssam * Size of extended memory 737292Ssam */ 747292Ssam 757292Ssam #define NEXMPAGES (256*2) 767292Ssam #define WORDSPERPAGE (256) 777292Ssam 787292Ssam /* 797292Ssam * MAP picture processor registers: SCB 0177750-0177753 807292Ssam */ 817292Ssam 827292Ssam #define MAOL 0177750 837292Ssam #define MAOA 0177751 847292Ssam #define MAIA 0177752 857292Ssam #define MASR 0177753 867292Ssam #define MAMSR 0177754 877292Ssam 887292Ssam /* 897292Ssam * MAP status register bits 907292Ssam */ 917292Ssam 927292Ssam #define PPDONE 0100000 937292Ssam #define FIFOFULL 040000 947292Ssam #define FIFOEMPTY 020000 957292Ssam #define HIT 010000 967292Ssam #define IB 04000 977292Ssam #define TAKE 02000 987292Ssam #define MMODE 01400 997292Ssam #define MOSTOPPED 0200 1007292Ssam #define IOUT 0100 1017292Ssam #define MAO 040 1027292Ssam #define MAI 020 1037292Ssam #define HIT_HOLD 010 1047292Ssam #define RSR_HOLD 04 1057292Ssam #define VEC_HOLD 02 1067292Ssam #define MAP_RESET 01 1077292Ssam 1087292Ssam /* 1097292Ssam * Refresh controller registers: SCB 0177730-0177737 1107292Ssam */ 1117292Ssam 1127292Ssam #define RFCSN 0177730 1137292Ssam #define RFSN 0177731 1147292Ssam #define RFAWA 0177732 1157292Ssam #define RFAWL 0177733 1167292Ssam #define RFAIA 0177734 1177292Ssam #define RFASA 0177735 1187292Ssam #define RFAIL 0177736 1197292Ssam #define RFSR 0177737 1207292Ssam 1217292Ssam /* 1227292Ssam * Refresh controller status register bits 1237292Ssam */ 1247292Ssam 1257292Ssam #define RFSTOPPED 0100000 1267292Ssam #define RFHOLD 040000 1277292Ssam #define RFSTART 020000 1287292Ssam #define AUTOREF 010000 1297292Ssam #define RFBLANK 04000 1307292Ssam #define RIGHT 02000 1317292Ssam #define LGFIFO_FULL 01000 1327292Ssam #define NOT_EXEC 0200 1337292Ssam #define SKIPSEG 0100 1347292Ssam #define WRITEBACK 040 1357292Ssam #define SEARCH 020 1367292Ssam #define MATCH_HOLD 010 1377292Ssam #define MATCH_DEC 04 1387292Ssam #define SEARCH_MODE 03 1397292Ssam 1407292Ssam /* 1417292Ssam * Interrupt control 1427292Ssam */ 1437292Ssam 1447292Ssam #define RTCREQ 0177760 1457292Ssam #define RTCIE 0177761 1467292Ssam #define SYSREQ 0177762 1477292Ssam #define SYSIE 0177763 1487292Ssam #define DEVREQ 0177764 1497292Ssam #define DEVIE 0177765 1507292Ssam 1517292Ssam /* 1527292Ssam * System interrupt request bits 1537292Ssam */ 1547292Ssam 1557292Ssam #define LPEN_REQ 0200 1567292Ssam #define MATCH_REQ 0100 1577292Ssam #define WBSTOP_REQ 040 1587292Ssam #define RFSTOP_REQ 020 1597292Ssam #define MOSTOP_REQ 010 1607292Ssam #define JUMP_REQ 04 1617292Ssam #define HIT_REQ 02 1627292Ssam #define HALT_REQ 01 1637292Ssam 1647292Ssam /* 1657292Ssam * Real-Time Clock registers 1667292Ssam */ 1677292Ssam 1687292Ssam #define RTCCNT 0177744 1697292Ssam #define RTCSR 0177745 1707292Ssam 1717292Ssam /* 1727292Ssam * Real-Time Clock status register bits 1737292Ssam */ 1747292Ssam 1757292Ssam #define HZ120 040 1767292Ssam #define EXT 020 1777292Ssam #define SYNC 010 1787292Ssam #define EXTSEL2 04 1797292Ssam #define EXTSEL1 02 1807292Ssam #define RUN 01 1817292Ssam 1827292Ssam /* 1837292Ssam * Control dials a/d registers 1847292Ssam */ 1857292Ssam 1867292Ssam #define ADDR0 0177500 1877292Ssam #define ADDR1 0177501 1887292Ssam #define ADDR2 0177502 1897292Ssam #define ADDR3 0177503 1907292Ssam #define ADDR4 0177504 1917292Ssam #define ADDR5 0177505 1927292Ssam #define ADDR6 0177506 1937292Ssam #define ADDR7 0177507 1947292Ssam 1957292Ssam /* 1967292Ssam * Function switches and lights 1977292Ssam */ 1987292Ssam 1997292Ssam #define FSWR 0177626 2007292Ssam #define FSLR 0177627 201