1*14601Ssam /* psreg.h 4.3 83/08/13 */ 27292Ssam 37292Ssam 47292Ssam /* 57292Ssam * The Real Nitty Gritty Device Registers 67292Ssam */ 77292Ssam 87292Ssam struct psdevice { 97292Ssam short int ps_data; /* data register */ 107292Ssam short int ps_addr; /* address register */ 117292Ssam short int ps_wcount; /* word count register */ 127292Ssam short int ps_busaddr; /* unibus address register */ 137292Ssam short int ps_iostat; /* io status register */ 147292Ssam }; 157292Ssam 167292Ssam /* 177292Ssam * Possible ioctl's 187292Ssam */ 197623Ssam #define PSIOAUTOREFRESH _IO(p, 0) /* auto refresh */ 207623Ssam #define PSIOSINGLEREFRESH _IO(p, 1) /* single refresh */ 217623Ssam #define PSIOAUTOMAP _IO(p, 2) /* auto map */ 227623Ssam #define PSIOSINGLEMAP _IO(p, 3) /* single map */ 237623Ssam #define PSIODOUBLEBUFFER _IO(p, 4) /* double buffer */ 247623Ssam #define PSIOSINGLEBUFFER _IO(p, 5) /* single buffer */ 257623Ssam #define PSIOWAITREFRESH _IO(p, 6) /* await refresh */ 267623Ssam #define PSIOWAITMAP _IO(p, 7) /* await map */ 277623Ssam #define PSIOWAITHIT _IO(p, 8) /* await hit */ 287623Ssam #define PSIOSTOPREFRESH _IO(p, 9) /* stop refresh */ 297623Ssam #define PSIOSTOPMAP _IO(p,10) /* stop map */ 307623Ssam #define PSIOGETADDR _IOR(p,11, int) /* get Unibus address */ 31*14601Ssam #define PSIOTIMEREFRESH _IO(p,12) /* time refresh */ 327292Ssam 337292Ssam /* 347292Ssam * Picture system io status register bits 357292Ssam */ 367292Ssam 377292Ssam #define DIOREADY 0100000 387292Ssam #define PSAHOLD 040000 397292Ssam #define PSRESET 020000 407292Ssam #define DIORESET 010000 417292Ssam #define DMARESET 04000 427292Ssam #define PSIE 0400 437292Ssam #define DMAREADY 0200 447292Ssam #define DMAIE 0100 457292Ssam #define PASSIVE 010 467292Ssam #define DMAIN 04 477292Ssam #define NEXEM 02 487292Ssam #define GO 01 497292Ssam 507292Ssam /* 517292Ssam * Picture system memory mapping control registers: SCB 0177400-0177410 527292Ssam */ 537292Ssam 547292Ssam #define EXMMR_DMA 0177400 557292Ssam #define EXMMR_DIO 0177404 567292Ssam #define EXMMR_RC 0177405 577292Ssam #define EXMMR_MAPOUT 0177406 587292Ssam #define EXMMR_MAPIN 0177407 597292Ssam #define EXMSR 0177410 607292Ssam 617292Ssam /* 627292Ssam * Extended memory status register bits 637292Ssam */ 647292Ssam 657292Ssam #define DBERROR 0100000 667292Ssam #define SBERROR 040000 677292Ssam #define MEMREADY 0200 687292Ssam #define DBIE 0100 697292Ssam #define MMENBL 02 707292Ssam #define INITMEM 01 717292Ssam 727292Ssam /* 737292Ssam * Size of extended memory 747292Ssam */ 757292Ssam 767292Ssam #define NEXMPAGES (256*2) 777292Ssam #define WORDSPERPAGE (256) 787292Ssam 797292Ssam /* 807292Ssam * MAP picture processor registers: SCB 0177750-0177753 817292Ssam */ 827292Ssam 837292Ssam #define MAOL 0177750 847292Ssam #define MAOA 0177751 857292Ssam #define MAIA 0177752 867292Ssam #define MASR 0177753 877292Ssam #define MAMSR 0177754 887292Ssam 897292Ssam /* 907292Ssam * MAP status register bits 917292Ssam */ 927292Ssam 937292Ssam #define PPDONE 0100000 947292Ssam #define FIFOFULL 040000 957292Ssam #define FIFOEMPTY 020000 967292Ssam #define HIT 010000 977292Ssam #define IB 04000 987292Ssam #define TAKE 02000 997292Ssam #define MMODE 01400 1007292Ssam #define MOSTOPPED 0200 1017292Ssam #define IOUT 0100 1027292Ssam #define MAO 040 1037292Ssam #define MAI 020 1047292Ssam #define HIT_HOLD 010 1057292Ssam #define RSR_HOLD 04 1067292Ssam #define VEC_HOLD 02 1077292Ssam #define MAP_RESET 01 1087292Ssam 1097292Ssam /* 1107292Ssam * Refresh controller registers: SCB 0177730-0177737 1117292Ssam */ 1127292Ssam 1137292Ssam #define RFCSN 0177730 1147292Ssam #define RFSN 0177731 1157292Ssam #define RFAWA 0177732 1167292Ssam #define RFAWL 0177733 1177292Ssam #define RFAIA 0177734 1187292Ssam #define RFASA 0177735 1197292Ssam #define RFAIL 0177736 1207292Ssam #define RFSR 0177737 1217292Ssam 1227292Ssam /* 1237292Ssam * Refresh controller status register bits 1247292Ssam */ 1257292Ssam 1267292Ssam #define RFSTOPPED 0100000 1277292Ssam #define RFHOLD 040000 1287292Ssam #define RFSTART 020000 1297292Ssam #define AUTOREF 010000 1307292Ssam #define RFBLANK 04000 1317292Ssam #define RIGHT 02000 1327292Ssam #define LGFIFO_FULL 01000 1337292Ssam #define NOT_EXEC 0200 1347292Ssam #define SKIPSEG 0100 1357292Ssam #define WRITEBACK 040 1367292Ssam #define SEARCH 020 1377292Ssam #define MATCH_HOLD 010 1387292Ssam #define MATCH_DEC 04 1397292Ssam #define SEARCH_MODE 03 1407292Ssam 1417292Ssam /* 1427292Ssam * Interrupt control 1437292Ssam */ 1447292Ssam 1457292Ssam #define RTCREQ 0177760 1467292Ssam #define RTCIE 0177761 1477292Ssam #define SYSREQ 0177762 1487292Ssam #define SYSIE 0177763 1497292Ssam #define DEVREQ 0177764 1507292Ssam #define DEVIE 0177765 1517292Ssam 1527292Ssam /* 1537292Ssam * System interrupt request bits 1547292Ssam */ 1557292Ssam 1567292Ssam #define LPEN_REQ 0200 1577292Ssam #define MATCH_REQ 0100 1587292Ssam #define WBSTOP_REQ 040 1597292Ssam #define RFSTOP_REQ 020 1607292Ssam #define MOSTOP_REQ 010 1617292Ssam #define JUMP_REQ 04 1627292Ssam #define HIT_REQ 02 1637292Ssam #define HALT_REQ 01 1647292Ssam 1657292Ssam /* 1667292Ssam * Real-Time Clock registers 1677292Ssam */ 1687292Ssam 1697292Ssam #define RTCCNT 0177744 1707292Ssam #define RTCSR 0177745 1717292Ssam 1727292Ssam /* 1737292Ssam * Real-Time Clock status register bits 1747292Ssam */ 1757292Ssam 1767292Ssam #define HZ120 040 1777292Ssam #define EXT 020 1787292Ssam #define SYNC 010 1797292Ssam #define EXTSEL2 04 1807292Ssam #define EXTSEL1 02 1817292Ssam #define RUN 01 1827292Ssam 1837292Ssam /* 1847292Ssam * Control dials a/d registers 1857292Ssam */ 1867292Ssam 1877292Ssam #define ADDR0 0177500 1887292Ssam #define ADDR1 0177501 1897292Ssam #define ADDR2 0177502 1907292Ssam #define ADDR3 0177503 1917292Ssam #define ADDR4 0177504 1927292Ssam #define ADDR5 0177505 1937292Ssam #define ADDR6 0177506 1947292Ssam #define ADDR7 0177507 1957292Ssam 1967292Ssam /* 1977292Ssam * Function switches and lights 1987292Ssam */ 1997292Ssam 2007292Ssam #define FSWR 0177626 2017292Ssam #define FSLR 0177627 202