1*49567Sbostic /*- 2*49567Sbostic * Copyright (c) 1982, 1986 The Regents of the University of California. 3*49567Sbostic * All rights reserved. 423335Smckusick * 5*49567Sbostic * %sccs.include.redist.c% 6*49567Sbostic * 7*49567Sbostic * @(#)psreg.h 7.3 (Berkeley) 05/09/91 823335Smckusick */ 97292Ssam 107292Ssam 117292Ssam /* 127292Ssam * The Real Nitty Gritty Device Registers 137292Ssam */ 147292Ssam 157292Ssam struct psdevice { 167292Ssam short int ps_data; /* data register */ 177292Ssam short int ps_addr; /* address register */ 187292Ssam short int ps_wcount; /* word count register */ 197292Ssam short int ps_busaddr; /* unibus address register */ 207292Ssam short int ps_iostat; /* io status register */ 217292Ssam }; 227292Ssam 237292Ssam /* 247292Ssam * Possible ioctl's 257292Ssam */ 2633103Sbostic #define PSIOAUTOREFRESH _IO('p', 0) /* auto refresh */ 2733103Sbostic #define PSIOSINGLEREFRESH _IO('p', 1) /* single refresh */ 2833103Sbostic #define PSIOAUTOMAP _IO('p', 2) /* auto map */ 2933103Sbostic #define PSIOSINGLEMAP _IO('p', 3) /* single map */ 3033103Sbostic #define PSIODOUBLEBUFFER _IO('p', 4) /* double buffer */ 3133103Sbostic #define PSIOSINGLEBUFFER _IO('p', 5) /* single buffer */ 3233103Sbostic #define PSIOWAITREFRESH _IO('p', 6) /* await refresh */ 3333103Sbostic #define PSIOWAITMAP _IO('p', 7) /* await map */ 3433103Sbostic #define PSIOWAITHIT _IO('p', 8) /* await hit */ 3533103Sbostic #define PSIOSTOPREFRESH _IO('p', 9) /* stop refresh */ 3633103Sbostic #define PSIOSTOPMAP _IO('p',10) /* stop map */ 3733103Sbostic #define PSIOGETADDR _IOR('p',11, int) /* get Unibus address */ 3833103Sbostic #define PSIOTIMEREFRESH _IO('p',12) /* time refresh */ 397292Ssam 407292Ssam /* 417292Ssam * Picture system io status register bits 427292Ssam */ 437292Ssam 447292Ssam #define DIOREADY 0100000 457292Ssam #define PSAHOLD 040000 467292Ssam #define PSRESET 020000 477292Ssam #define DIORESET 010000 487292Ssam #define DMARESET 04000 497292Ssam #define PSIE 0400 507292Ssam #define DMAREADY 0200 517292Ssam #define DMAIE 0100 527292Ssam #define PASSIVE 010 537292Ssam #define DMAIN 04 547292Ssam #define NEXEM 02 557292Ssam #define GO 01 567292Ssam 577292Ssam /* 587292Ssam * Picture system memory mapping control registers: SCB 0177400-0177410 597292Ssam */ 607292Ssam 617292Ssam #define EXMMR_DMA 0177400 627292Ssam #define EXMMR_DIO 0177404 637292Ssam #define EXMMR_RC 0177405 647292Ssam #define EXMMR_MAPOUT 0177406 657292Ssam #define EXMMR_MAPIN 0177407 667292Ssam #define EXMSR 0177410 677292Ssam 687292Ssam /* 697292Ssam * Extended memory status register bits 707292Ssam */ 717292Ssam 727292Ssam #define DBERROR 0100000 737292Ssam #define SBERROR 040000 747292Ssam #define MEMREADY 0200 757292Ssam #define DBIE 0100 767292Ssam #define MMENBL 02 777292Ssam #define INITMEM 01 787292Ssam 797292Ssam /* 807292Ssam * Size of extended memory 817292Ssam */ 827292Ssam 837292Ssam #define NEXMPAGES (256*2) 847292Ssam #define WORDSPERPAGE (256) 857292Ssam 867292Ssam /* 877292Ssam * MAP picture processor registers: SCB 0177750-0177753 887292Ssam */ 897292Ssam 907292Ssam #define MAOL 0177750 917292Ssam #define MAOA 0177751 927292Ssam #define MAIA 0177752 937292Ssam #define MASR 0177753 947292Ssam #define MAMSR 0177754 957292Ssam 967292Ssam /* 977292Ssam * MAP status register bits 987292Ssam */ 997292Ssam 1007292Ssam #define PPDONE 0100000 1017292Ssam #define FIFOFULL 040000 1027292Ssam #define FIFOEMPTY 020000 1037292Ssam #define HIT 010000 1047292Ssam #define IB 04000 1057292Ssam #define TAKE 02000 1067292Ssam #define MMODE 01400 1077292Ssam #define MOSTOPPED 0200 1087292Ssam #define IOUT 0100 1097292Ssam #define MAO 040 1107292Ssam #define MAI 020 1117292Ssam #define HIT_HOLD 010 1127292Ssam #define RSR_HOLD 04 1137292Ssam #define VEC_HOLD 02 1147292Ssam #define MAP_RESET 01 1157292Ssam 1167292Ssam /* 1177292Ssam * Refresh controller registers: SCB 0177730-0177737 1187292Ssam */ 1197292Ssam 1207292Ssam #define RFCSN 0177730 1217292Ssam #define RFSN 0177731 1227292Ssam #define RFAWA 0177732 1237292Ssam #define RFAWL 0177733 1247292Ssam #define RFAIA 0177734 1257292Ssam #define RFASA 0177735 1267292Ssam #define RFAIL 0177736 1277292Ssam #define RFSR 0177737 1287292Ssam 1297292Ssam /* 1307292Ssam * Refresh controller status register bits 1317292Ssam */ 1327292Ssam 1337292Ssam #define RFSTOPPED 0100000 1347292Ssam #define RFHOLD 040000 1357292Ssam #define RFSTART 020000 1367292Ssam #define AUTOREF 010000 1377292Ssam #define RFBLANK 04000 1387292Ssam #define RIGHT 02000 1397292Ssam #define LGFIFO_FULL 01000 1407292Ssam #define NOT_EXEC 0200 1417292Ssam #define SKIPSEG 0100 1427292Ssam #define WRITEBACK 040 1437292Ssam #define SEARCH 020 1447292Ssam #define MATCH_HOLD 010 1457292Ssam #define MATCH_DEC 04 1467292Ssam #define SEARCH_MODE 03 1477292Ssam 1487292Ssam /* 1497292Ssam * Interrupt control 1507292Ssam */ 1517292Ssam 1527292Ssam #define RTCREQ 0177760 1537292Ssam #define RTCIE 0177761 1547292Ssam #define SYSREQ 0177762 1557292Ssam #define SYSIE 0177763 1567292Ssam #define DEVREQ 0177764 1577292Ssam #define DEVIE 0177765 1587292Ssam 1597292Ssam /* 1607292Ssam * System interrupt request bits 1617292Ssam */ 1627292Ssam 1637292Ssam #define LPEN_REQ 0200 1647292Ssam #define MATCH_REQ 0100 1657292Ssam #define WBSTOP_REQ 040 1667292Ssam #define RFSTOP_REQ 020 1677292Ssam #define MOSTOP_REQ 010 1687292Ssam #define JUMP_REQ 04 1697292Ssam #define HIT_REQ 02 1707292Ssam #define HALT_REQ 01 1717292Ssam 1727292Ssam /* 1737292Ssam * Real-Time Clock registers 1747292Ssam */ 1757292Ssam 1767292Ssam #define RTCCNT 0177744 1777292Ssam #define RTCSR 0177745 1787292Ssam 1797292Ssam /* 1807292Ssam * Real-Time Clock status register bits 1817292Ssam */ 1827292Ssam 1837292Ssam #define HZ120 040 1847292Ssam #define EXT 020 1857292Ssam #define SYNC 010 1867292Ssam #define EXTSEL2 04 1877292Ssam #define EXTSEL1 02 1887292Ssam #define RUN 01 1897292Ssam 1907292Ssam /* 1917292Ssam * Control dials a/d registers 1927292Ssam */ 1937292Ssam 1947292Ssam #define ADDR0 0177500 1957292Ssam #define ADDR1 0177501 1967292Ssam #define ADDR2 0177502 1977292Ssam #define ADDR3 0177503 1987292Ssam #define ADDR4 0177504 1997292Ssam #define ADDR5 0177505 2007292Ssam #define ADDR6 0177506 2017292Ssam #define ADDR7 0177507 2027292Ssam 2037292Ssam /* 2047292Ssam * Function switches and lights 2057292Ssam */ 2067292Ssam 2077292Ssam #define FSWR 0177626 2087292Ssam #define FSLR 0177627 209