xref: /csrg-svn/sys/vax/uba/npreg.h (revision 30866)
126200Ssklower /*
226267Ssklower  * Copyright (c) 1986 MICOM-Interlan, Inc., Boxborough Mass
326267Ssklower  * All rights reserved.  The Berkeley software License Agreement
426267Ssklower  * specifies the terms and conditions for redistribution.
526200Ssklower  *
6*30866Skarels  *	@(#)npreg.h	7.2 (Berkeley) 04/08/87
7*30866Skarels  *
8*30866Skarels  * Merged header file for MICOM-Interlan NP100.
926200Ssklower  */
1026200Ssklower 
1126200Ssklower /*
12*30866Skarels  *	np100.h version 1.3
1326200Ssklower  *
14*30866Skarels  *	This version retrieved: 8/18/86 @ 18:58:44
15*30866Skarels  *	    This delta created: 8/18/86 @ 18:27:32
1626200Ssklower  */
1726200Ssklower /*
1826200Ssklower  * Typedefs for the VAX
1926200Ssklower  */
2026200Ssklower 
2126200Ssklower typedef short	sign16;			/* 16 bit signed value */
2226200Ssklower typedef unsigned short unsign16;	/* 16 bit unsigned value */
2326200Ssklower typedef unsigned unsign32;		/* 32 bit unsigned value */
2426200Ssklower typedef long paddr_t;			/* Physical addresses */
2526200Ssklower 
2626200Ssklower 
2726200Ssklower /*
2826200Ssklower  * Tunables
2926200Ssklower  */
3026200Ssklower 
3126200Ssklower 
3226200Ssklower #define NUMCQE		40		/* Number of CQE's per board */
3326200Ssklower 
3426200Ssklower /* Host configuration word in Status Block */
3526200Ssklower 
3626200Ssklower /*
3726200Ssklower  * To disable the lock/unlock internal function calls clear the 0x8000
3826200Ssklower  * bit in the host configuration word (HOSTCONF)
3926200Ssklower  */
4026200Ssklower 
4126200Ssklower #define	HOSTCONF	0x0109	/* See above */
4226200Ssklower #define	LOWBYTE		1
4326200Ssklower #define	HIGHBYTE	0
4426200Ssklower #define BUFFMAPPED	0
4526200Ssklower 
4626200Ssklower /*
4726200Ssklower  * Memory mapping definintions for PM68DUAL hardware.
4826200Ssklower  */
4926200Ssklower 
5026200Ssklower #ifdef PM68DUAL
5126200Ssklower #define	PISHMEM		0x200000
5226200Ssklower #define PISHMEMSIZE	2
5326200Ssklower #define PIOFF		0x8000		/* change this to unique mem add. */
5426200Ssklower #define PIWINDOW	MBUSBUFR + PIOFF
5526200Ssklower #define WINDOWSIZE	2
5626200Ssklower #endif
5726200Ssklower #define	NPMAXXFR	32768		/* Maximum number of bytes / read */
5826200Ssklower 
5926200Ssklower /*
6026200Ssklower  * Define the protocols supported by the NP Driver.
6126200Ssklower  */
6226200Ssklower 
6326200Ssklower #define NONE		0x00	/* No protocols active for a process */
6426200Ssklower #define NPMAINT		0x01	/* Maintenance protocol, superusers only */
6526200Ssklower #define NPNTS		0x02	/* NTS Terminal Server */
66*30866Skarels #define NPIDP		0x04	/* Direct Datalink Access */
6726200Ssklower #define NPDLA		0x04	/* Direct Datalink Access */
6826200Ssklower #define NPXNS		0x06	/* Xerox NS ITP */
6926200Ssklower #define NPTCP		0x08	/* TCP/IP */
7026200Ssklower #define NPISO		0x0A	/* ISO */
7126200Ssklower #define NPCLCONN	0xFF	/* Closed connection, i.e. no protocol */
7226200Ssklower 
7326200Ssklower /*
7426200Ssklower  * Convert the protocol to a value used in the Device Protocol Mask field
7526200Ssklower  * of the Shared Memory Status Block.
7626200Ssklower  */
7726200Ssklower 
7826200Ssklower #define PROTOMASK(x)	( 1 << (x) )
7926200Ssklower 
8026200Ssklower /*
8126200Ssklower  * Special requests handled by the NP Driver
8226200Ssklower  */
8326200Ssklower 
8426200Ssklower #define OS_STP		03400	/* Shut down connection on I Board */
8526200Ssklower #define NPSTOP		3	/* Conversion from above (OS_STP) */
8626200Ssklower #define NPCHNGP		50	/* Change the protocol on a connection */
8726200Ssklower #define NPCHNGB		51	/* Change the Board number */
8826200Ssklower 
8926200Ssklower /*
9026200Ssklower  * Miscellaneous
9126200Ssklower  */
9226200Ssklower 
9326200Ssklower #define ON		0x8000  /* Used for Command Q's scan and change flag */
9426200Ssklower #define UBADDRMASK	0x3FFFF /* 18 bit UNIBUS address */
9526200Ssklower #define INTMASK		0xFFFFFFFC /* Used for address validation */
9626200Ssklower #define CMDMASK		0xFFFF	/* Mask ioctl cmd field (see ioctl.h) */
9726200Ssklower #define NPPSADDR	0x324	/* Pointer to addr of on-board panic string */
9826200Ssklower #define	PANLEN		133		/* length of the panic buffer */
9926200Ssklower 
10026200Ssklower /*
10126200Ssklower  * Map function code from user to I-Board format
10226200Ssklower  */
10326200Ssklower 
10426200Ssklower #define FUNCTMAP(x)	(((x) << 6) | 077) /* Maps user function to NP funcs */
10526200Ssklower 
10626200Ssklower /*
10726200Ssklower  * Round up to a 16 byte boundary
10826200Ssklower  */
10926200Ssklower 
11026200Ssklower #define ROUND16(x)	(((x) + 15) & (~0x0F)) /* Round to 16 byte boundary */
11126200Ssklower #define ADDR24		1 /* Used by iomalloc() to specify 24 bit address */
11226200Ssklower 
11326200Ssklower #define NPERRSHIFT	8	/* Used in function ReqDone() */
11426200Ssklower #define NPOK		0
11526200Ssklower 
11626200Ssklower #define LOWORD(X)	(((ushort *)&(X))[0])
11726200Ssklower #define HIWORD(X)	(((ushort *)&(X))[1])
11826200Ssklower 
11926200Ssklower /* Everyday flag settings */
12026200Ssklower 
12126200Ssklower #define NPSET		1
12226200Ssklower #define NPCLEAR		0
12326200Ssklower 
12426200Ssklower /*
12526200Ssklower  * Command Queue Elements are the primary data structure for passing data
12626200Ssklower  * between the driver and the device.
12726200Ssklower  */
12826200Ssklower 
12926200Ssklower struct CQE {
13026200Ssklower 
13126200Ssklower 	struct npreq *cqe_reqid;/* Address of asssociated npreq */
132*30866Skarels 	union	{
133*30866Skarels 		unsign32 cqe_Famid;	/* Family ID (Process ID) - wn */
134*30866Skarels 		unsign16 cqe_PrtSig[2];	/* port and signal - tn */
135*30866Skarels 	} u1;
136*30866Skarels #define	cqe_famid	u1.cqe_Famid
137*30866Skarels #define	cqe_port	u1.cqe_PrtSig[0]
138*30866Skarels #define	cqe_signal	u1.cqe_PrtSig[1]
13926200Ssklower 	unsign16 cqe_func;	/* I/O function to be performed */
14026200Ssklower #ifdef mc68000
14126200Ssklower 	char cqe_prot;		/* Protocol type for I/O request */
14226200Ssklower 	char cqe_lenrpb;	/* Length of the RPB in bytes */
14326200Ssklower #else
14426200Ssklower 	char cqe_lenrpb;	/* Length of the RPB in bytes */
14526200Ssklower 	char cqe_prot;		/* Protocol type for I/O request */
14626200Ssklower #endif
147*30866Skarels 	union	{
148*30866Skarels 		unsign16 cqe_ustS[2];	/* Protocol status return */
149*30866Skarels 		unsign32 cqe_ustL;	/* Protocol status return */
150*30866Skarels 	} u2;
151*30866Skarels #define	cqe_ust0	u2.cqe_ustS[0]
152*30866Skarels #define	cqe_ust1	u2.cqe_ustS[1]
153*30866Skarels #define	cqe_usts	u2.cqe_ustL
15426200Ssklower 	unsign16 cqe_devrsv;	/* Reserved for use by device only! */
15526200Ssklower #ifdef mc68000
15626200Ssklower 	char cqe_char;		/* CQE characteristics */
15726200Ssklower 	char cqe_sts;		/* Status return from device to user */
15826200Ssklower 	char cqe_wind;		/* Buffer mapping window size (page units) */
15926200Ssklower 	char cqe_nbuf;		/* Number of data buffers for I/O */
16026200Ssklower #else
16126200Ssklower 	char cqe_sts;		/* Status return from device to user */
16226200Ssklower 	char cqe_char;		/* CQE characteristics */
16326200Ssklower 	char cqe_nbuf;		/* Number of data buffers for I/O */
16426200Ssklower 	char cqe_wind;		/* Buffer mapping window size (page units) */
16526200Ssklower #endif
16626200Ssklower 	unsign16 cqe_bcnt;	/* Total number of bytes in the data buffer */
167*30866Skarels 	union {
168*30866Skarels 		unsign16 cqe_Unused;	/* Unused */
169*30866Skarels 		struct {
170*30866Skarels 			char cqe_Maxbcnt;	/* Maximum size of buffer */
171*30866Skarels 			char cqe_Bflags;	/* Used by the SPI */
172*30866Skarels 		} s;
173*30866Skarels 	} u3;
174*30866Skarels #define cqe_unused	u3.cqe_Unused
175*30866Skarels #define cqe_maxbcnt	u3.s.cqe_Maxbcnt
176*30866Skarels #define cqe_bflags	u3.s.cqe_Bflags
17726200Ssklower 	unsign16 cqe_dma[2];	/* Address of the MULTIBUS data buffer */
17826200Ssklower 	unsign16 rpb1;		/* Word 1 of protocol parameters */
17926200Ssklower 	unsign16 rpb2;		/* Word 2 of protocol parameters */
18026200Ssklower 	unsign16 rpb3;		/* Word 3 of protocol parameters */
18126200Ssklower 	unsign16 rpb4;		/* Word 4 of protocol parameters */
18226200Ssklower 	unsign16 rpb5;		/* Word 5 of protocol parameters */
18326200Ssklower 	unsign16 rpb6;		/* Word 6 of protocol parameters */
18426200Ssklower 	unsign16 rpb7;		/* Word 7 of protocol parameters */
18526200Ssklower 	unsign16 rpb8;		/* Word 8 of protocol parameters */
18626200Ssklower 	unsign16 rpb9;		/* Word 9 of protocol parameters */
18726200Ssklower 	unsign16 rpb10;		/* Word 10 of protocol parameters */
18826200Ssklower 	unsign16 rpb11;		/* Word 11 of protocol parameters */
18926200Ssklower 	unsign16 rpb12;		/* Word 12 of protocol parameters */
19026200Ssklower 
19126200Ssklower };
19226200Ssklower 
19326200Ssklower /*
19426200Ssklower  * NP Driver Request structure contains information about a request
19526200Ssklower  * maintained solely by the driver. One per CQE, plus a header.
19626200Ssklower  */
19726200Ssklower 
198*30866Skarels  struct npreq {
19926200Ssklower 
20026200Ssklower 	struct npreq *forw;	/* Forward pointer for active list */
20126200Ssklower 	struct npreq *back;	/* Backward pointer for active list */
20226200Ssklower 	struct npreq *free;	/* Next member on free list */
20326200Ssklower 	struct CQE *element;	/* CQE associated with this request */
20426200Ssklower 	int flags;		/* Always useful */
20526200Ssklower 	int reqcnt;		/* Request count for reqtab */
20626200Ssklower 	int bufoffset;		/* Offset into buffer for turns */
20726200Ssklower 	int	bytecnt;	/* Number of bytes to transfer */
20826200Ssklower 	caddr_t	virtmem;	/* Virtual address of buffer */
20926200Ssklower 	int	mapbase;	/* Address of the mapping register */
21026200Ssklower 	int 	mapsize;	/* Size of mapped area */
21126200Ssklower 	caddr_t	bufaddr;	/* Address of the user buffer */
21226200Ssklower 	struct buf buf;		/* Buf structure needed for mem. mgmt */
21326200Ssklower 	struct proc *procp;	/* Pointer to process of requestor */
21426200Ssklower 	caddr_t user;		/* Structure passed by user from itpuser.h */
21526200Ssklower 	int	(*intr)();	/* Ptr to routine to call at interrupt time */
216*30866Skarels 	int 	int_param;      /* Paramater to be used by above routine */
21726200Ssklower };
21826200Ssklower 
21926200Ssklower /*
22026200Ssklower  * Npmaster structure, one per device, is used for boardwise centralization
22126200Ssklower  * of relevant information including queues, I/O addresses and request pools.
22226200Ssklower  */
22326200Ssklower 
22426200Ssklower struct npmaster {
22526200Ssklower 
22626200Ssklower 	struct npmaster *next; 	/* Linked list of these, NULL terminator */
22726200Ssklower 	struct npspace *shmemp;	/* Shared memory address (driver <-> device) */
22826200Ssklower 	struct uba_device *devp; /* UBA Device for this unit */
22926200Ssklower 	struct NPREG   *iobase;	/* I/O base address for this board */
23026200Ssklower 	struct npreq   *reqtab;	/* Header for pool of CQE requests */
23126200Ssklower 	int	iomapbase;	/* Base index of I/O map reg's allocated */
23226200Ssklower 	int flags;		/* State of the Board */
23326200Ssklower 	int unit;		/* Unit number of this device */
23426200Ssklower 	int vector;		/* Interrupt vector for this unit */
23526200Ssklower };
23626200Ssklower 
23726200Ssklower struct NPREG {
23826200Ssklower 	unsign16 CSR0;		/* Control Status Register 0 */
23926200Ssklower 	unsign16 CSR1;		/* Control Status Register 1 */
24026200Ssklower 	unsign16 CSR2;		/* Control Status Register 2 */
24126200Ssklower 	unsign16 CSR3;		/* Control Status Register 3 */
24226200Ssklower 
24326200Ssklower };
24426200Ssklower 
24526200Ssklower /*
24626200Ssklower  * The following structures are used for communicating with the
24726200Ssklower  * Intelligent Board and are located in Shared Memory.
24826200Ssklower  */
24926200Ssklower 
25026200Ssklower /*
25126200Ssklower  * Status Block
25226200Ssklower  */
25326200Ssklower 
25426200Ssklower struct NpStat{
25526200Ssklower 
25626200Ssklower 	unsign16 sb_drw;	/* Device Request Word */
25726200Ssklower 	unsign16 sb_hcw;	/* Host Configuration Word */
25826200Ssklower 	unsign16 sb_dcw;	/* Device Configuration Word */
25926200Ssklower 	unsign16 sb_dpm;	/* Device Protocol Mask */
26026200Ssklower 	unsign16 sb_dcq;	/* Offset to Device CQ */
26126200Ssklower 	unsign16 sb_hcq;	/* Offset to Host CQ */
26226200Ssklower };
26326200Ssklower 
26426200Ssklower /*
26526200Ssklower  * Command Queue, two per device. One is owned by the driver and the other
26626200Ssklower  * is owned by the device.
26726200Ssklower  */
26826200Ssklower 
26926200Ssklower struct CmdQue {
27026200Ssklower 
27126200Ssklower 	unsign16 scanflag;	/* Scan Flag, MSB set if being scanned */
27226200Ssklower 	unsign16 chngflag;	/* Change Flag, MSB set by initiator */
27326200Ssklower 	unsign16 cq_wrap;	/* Offset to last CQE entry +2 */
27426200Ssklower 	unsign16 cq_add;	/* Offset to add a CQE to the queue */
27526200Ssklower 	unsign16 cq_rem;	/* Offset to remove a CQE from the queue */
27626200Ssklower 	unsign16 cq_cqe[NUMCQE]; /* Command Queue Element Offsets */
27726200Ssklower };
27826200Ssklower 
27926200Ssklower /*
28026200Ssklower  * Structure of the shared memory area per board. Declared this way to avoid
28126200Ssklower  * compiler word alignment vagaries when computing offsets.
28226200Ssklower  */
28326200Ssklower 
28426200Ssklower struct npspace {
28526200Ssklower 
28626200Ssklower 	struct NpStat statblock;	/* Status Block */
28726200Ssklower 	struct CmdQue devcq;		/* Device's Command Queue */
28826200Ssklower 	struct CmdQue hostcq;		/* Host's Command Queue */
28926200Ssklower 	struct CQE elements[NUMCQE];	/* Shared Command Queue Elements */
29026200Ssklower 	unsign16 filler[8];		/* Here for 16 byte alignment */
29126200Ssklower };
29226200Ssklower 
29326200Ssklower /*
29426200Ssklower  * Structure of array of base addresses of I-Board controllers
29526200Ssklower  * (See global data definitions in np.c)
29626200Ssklower  */
29726200Ssklower 
29826200Ssklower struct npbase {
29926200Ssklower 	caddr_t baseaddr;
30026200Ssklower };
30126200Ssklower 
30226200Ssklower /* State of the NP Driver as kept in NpState */
30326200Ssklower 
30426200Ssklower #define ICPAVAIL	0x01 	/* ICP is waiting for a request */
30526200Ssklower 
30626200Ssklower /* Tells ICP Process that there are no more requests for this board */
30726200Ssklower 
30826200Ssklower #define BRDDONE 1
30926200Ssklower 
31026200Ssklower /* Flags used by the driver (npreq structure) to monitor status of requests */
31126200Ssklower 
31226200Ssklower #define REQDONE 0x01		/* Request completed */
31326200Ssklower #define IOIFC   0x02		/* Internal Function Code Request */
31426200Ssklower #define IOERR	0x04		/* Error on Request */
31526200Ssklower #define NPPEND	0x08		/* Unused at this time */
31626200Ssklower #define IOABORT 0x10		/* Request aborted by ICP */
31726200Ssklower #define KERNREQ	0x20		/* Request was from the kernel */
31826200Ssklower #define WANTREQ 0x40		/* Process is waiting for a npreq structure */
31926200Ssklower #define NPUIO	0x80		/* Process doing physio */
320*30866Skarels #define REQALOC 0x100           /* Request has been allocated */
321*30866Skarels #define REQUSE  0x200           /* Request is in request queue */
32226200Ssklower 
32326200Ssklower /* Service Request Commands from the Intelligent Board */
32426200Ssklower 
32526200Ssklower #define NOREQ	0x00		/* No service requested */
32626200Ssklower #define NPLOAD  0x01		/* Dump request */
32726200Ssklower #define NPDUMP	0x02		/* Load request */
32826200Ssklower #define NPPANIC	0x100		/* Panic request */
32926200Ssklower 
33026200Ssklower /* Definitions of Status returned from the I-Board */
33126200Ssklower 
33226200Ssklower #define NPDONE	0x01		/* Normal completion */
33326200Ssklower #define NPIFC	0x00		/* Internal Function Code request */
33426200Ssklower #define NPPERR  0x80		/* Protocol error */
33526200Ssklower #define NPMERR	0x82		/* Memory allocation failure on I-Board */
33626200Ssklower 
33726200Ssklower /* Definitions of IFC type requests from I-Board */
33826200Ssklower 
33926200Ssklower #define NPLOCK	0x64		/* Lock the process's data area */
34026200Ssklower #define NPUNLOCK 0xA4		/* Unlock the process */
34126200Ssklower #define NPREMAP	0x124		/* Window turn */
34226200Ssklower 
34326200Ssklower /* Definition of flags for the Npmaster structure */
34426200Ssklower 
34526200Ssklower #define CSRPEND		0x01		/* CSR0 command pending */
34626200Ssklower #define PANICREQ	0x02		/* Panic request */
34726200Ssklower #define DUMPREQ		0x04		/* Dump request */
34826200Ssklower #define LOADREQ		0x08		/* Load request */
34926200Ssklower #define BOARDREQ	0x10		/* Any request by the board */
35026200Ssklower #define BADBOARD	0x20		/* Board disabled */
35126200Ssklower #define AVAILABLE	0x40		/* Board available */
35226200Ssklower #define BRDRESET	0x80		/* Board is being reset */
35326200Ssklower #define	PANIC1	 	0x100		/* Driver wants panic address */
35426200Ssklower #define	PANIC2		0x200		/* Driver wants panic string */
35526200Ssklower #define PANIC3		0x400		/* Clear first byte of panic string */
356*30866Skarels #define LSTCMD          0x800           /* Clear last command during NPIO */
357*30866Skarels #define SCANNING        0x1000          /* We are scanning for cqe's */
35826200Ssklower 
35926200Ssklower /*
36026200Ssklower  * Debugging Constants
36126200Ssklower  */
36226200Ssklower 
36326200Ssklower #define	DEBENTRY	0x0001		/* debug entry points */
36426200Ssklower #define	DEBMEM		0x0002		/* debug memory */
36526200Ssklower #define	DEBREQ		0x0004		/* debug requests */
36626200Ssklower #define	DEBCQE		0x0008		/* debug cqe's */
36726200Ssklower #define	DEBCQ		0x0010		/* debug cq's */
36826200Ssklower #define	DEBMAINT	0x0020		/* debug maintainance requests */
36926200Ssklower #define	DEBINTR		0x0040		/* debug interrupt routines */
37026200Ssklower #define	DEBINIT		0x0080		/* debug initialization routines */
37126200Ssklower #define	DEBIFC		0x0100		/* debug Internal function codes */
37226200Ssklower #define	DEBIOCTL	0x0200		/* debug ioctl calls */
37326200Ssklower #define	DEBOPEN		0x0400		/* debug open calls */
37426200Ssklower #define	DEBIO		0x0800		/* debug read & write calls */
37526200Ssklower #define	DEBCSR		0x1000		/* debug CSR commands */
37626200Ssklower #define	DEBLOCK		0x2000		/* debug lock / unlock calls */
37726200Ssklower #define NOBOARD		0x4000		/* debug user/host interface */
378*30866Skarels #define DEBCANCEL       0x8000          /* debug cancel command */
379*30866Skarels 
380*30866Skarels /*
381*30866Skarels  *	npreg.h version 1.3
382*30866Skarels  *
383*30866Skarels  *	This version retrieved: 8/18/86 @ 18:58:46
384*30866Skarels  *	    This delta created: 8/18/86 @ 18:27:42
385*30866Skarels  */
386*30866Skarels 
387*30866Skarels /*
388*30866Skarels  *			NPREG.H
389*30866Skarels  *
390*30866Skarels  * This file contain definitions of specific hardware interest
391*30866Skarels  * to be used when communicating with the NI1510 Network Processor
392*30866Skarels  * Board. More complete information can be found in the NI1510
393*30866Skarels  * Multibus compatible Ethernet Communications Processor Hardware
394*30866Skarels  * Specification.
395*30866Skarels  */
396*30866Skarels 
397*30866Skarels /*
398*30866Skarels  *	npcmd.h version 1.3
399*30866Skarels  *
400*30866Skarels  *	This version retrieved: 8/18/86 @ 18:58:45
401*30866Skarels  *	    This delta created: 8/18/86 @ 18:27:38
402*30866Skarels  */
403*30866Skarels #ifndef IOC_VOID
404*30866Skarels #    ifdef KERNEL
405*30866Skarels #         include "../h/ioctl.h"
406*30866Skarels #    else
407*30866Skarels #         include <sys/ioctl.h>
408*30866Skarels #    endif
409*30866Skarels #endif
410*30866Skarels 
411*30866Skarels #ifdef KERNEL
412*30866Skarels #    define IoVOID 0
413*30866Skarels #else
414*30866Skarels #    define IoVOID IOC_VOID
415*30866Skarels #endif
416*30866Skarels 
417*30866Skarels #define NPRESET		(IoVOID|0x01)	/* reset the board */
418*30866Skarels #define	NPSTART		(IoVOID|0x04)	/* start board execution */
419*30866Skarels #define	NPGPANIC	(IoVOID|0x05)	/* Get panic message */
420*30866Skarels #define	NPINIT		(IoVOID|0x06)	/* initialize software on board */
421*30866Skarels #define NPSTATS 	(IoVOID|0x07)
422*30866Skarels #define	NPRCSR0		(IoVOID|0x08)	/* read CSR0 */
423*30866Skarels #define	NPRCSR1		(IoVOID|0x09)	/* read CSR1 */
424*30866Skarels #define	NPRCSR2		(IoVOID|0x0a)	/* read CSR2 */
425*30866Skarels #define	NPRCSR3		(IoVOID|0x0b)	/* read CSR3 */
426*30866Skarels #define	NPWCSR0		(IoVOID|0x0c)	/* write CSR0 */
427*30866Skarels #define	NPWCSR1		(IoVOID|0x0d)	/* write CSR1 */
428*30866Skarels #define	NPWCSR2		(IoVOID|0x0e)	/* write CSR2 */
429*30866Skarels #define	NPWCSR3		(IoVOID|0x0f)	/* write CSR3 */
430*30866Skarels #define NPPOLL  	(IoVOID|0x10)
431*30866Skarels #define NPKILL  	(IoVOID|0x11)
432*30866Skarels #define	NPSETPROT	(IoVOID|0x12)	/* set the protocol to use */
433*30866Skarels #define	NPSETBOARD	(IoVOID|0x13)	/* set board to use */
434*30866Skarels #define	NPSETNPDEB	(IoVOID|0x14)	/* set nc debuging level */
435*30866Skarels #define	NPSETADDR	(IoVOID|0x15)	/* set host address */
436*30866Skarels #define	NPNETBOOT	(IoVOID|0x16)	/* boot from the network */
437*30866Skarels #define NPSETLAST       (IoVOID|0x17)   /* set last command flag in NPIO */
438*30866Skarels #define NPCLRICNT       (IoVOID|0x18)   /* clear interupt count */
439*30866Skarels #define NPGETICNT       (IoVOID|0x19)   /* get interupt count */
440*30866Skarels #define NPGETIVEC       (IoVOID|0x1a)   /* get interupt vector */
441*30866Skarels #define NPMAPMEM        (IoVOID|0x1b)   /* map user memory to shmem */
442*30866Skarels 
443*30866Skarels #define NP_SET          1031            /* set memory mapping */
444*30866Skarels #define NP_USET         1032            /* unset memory mapping */
445*30866Skarels 
446*30866Skarels struct np_mem {
447*30866Skarels 	long mem_type;
448*30866Skarels 	char *mem_addr;
449*30866Skarels         long mem_count;
450*30866Skarels } ;
451*30866Skarels 
452*30866Skarels #define NNPCNN		4	/* Number of connections per board */
453*30866Skarels #define NPUNIT(a)	((minor(a) >> 4) & 0x0F)
454*30866Skarels #define NPCONN(a)	((minor(a)) & 0x03)
455*30866Skarels 
456*30866Skarels #define TRUE		1
457*30866Skarels #define FALSE		0
458*30866Skarels 
459*30866Skarels #define IBOOTADDR	0xF8000l	/* Addr of 80186 Boot ROM */
460*30866Skarels #define	INETBOOT	0xF8087l
461*30866Skarels #define IXEQADDR	0x400		/* Where to begin Board image XEQ */
462*30866Skarels #define DIAGTIME	1200		/* Time for timeout /HZ seconds */
463*30866Skarels 
464*30866Skarels #define	DELAYTIME	1000000L		/* delay count */
465*30866Skarels #define NPDELAY(N)	{register int n = (N) >> 1; while(--n > 0); }
466*30866Skarels 
467*30866Skarels /* Handy macros for talking to the Board */
468*30866Skarels 
469*30866Skarels #define RESET(x) 	(WCSR3(x->iobase,0xff))
470*30866Skarels #define CLEARINT(x)	{unsign16 y; y = RCSR2(x->iobase); }
471*30866Skarels #define INTNI(x)	(WCSR1(x->iobase,0xFF))
472*30866Skarels 
473*30866Skarels /* Command and Status Register (CSR) Definitions */
474*30866Skarels 
475*30866Skarels /*
476*30866Skarels  * CSR0 is the only direct means for data transfer between the host processor
477*30866Skarels  * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and
478*30866Skarels  * Ready bits to allow writing here. Writing to this register will always
479*30866Skarels  * result in an interrupt to the 80186.
480*30866Skarels  */
481*30866Skarels 
482*30866Skarels /*
483*30866Skarels  * Bit definitions for CSR1.
484*30866Skarels  */
485*30866Skarels 
486*30866Skarels #define NPRFU	0x01		/* Reserved for Future Use */
487*30866Skarels #define NPHOK	0x02		/* Hardware OK */
488*30866Skarels #define NPLAN	0x04		/* Logic 0 indicates operational LAN exists */
489*30866Skarels #define NP_IP	0x08		/* Interrupt pending from this board */
490*30866Skarels #define NP_IE	0x10		/* Interrupts enabled for this board */
491*30866Skarels #define NPRDR	0x20		/* Set when 80186 writes data into CSR0 */
492*30866Skarels #define NPRDY	0x40		/* CSR0 ready to accept data */
493*30866Skarels #define NPENB	0x80		/* CSR0 available for use by the host */
494*30866Skarels 
495*30866Skarels /*
496*30866Skarels  * Bit defintions for CSR0 Command Block
497*30866Skarels  */
498*30866Skarels 
499*30866Skarels #define NPLST	0x20		/* Last Command */
500*30866Skarels #define NPCMD	0x80		/* Shared Memory Address */
501*30866Skarels #define NPBGN	0x200		/* Begin Execution in On-Board Memory */
502*30866Skarels #define NPCBI	0x800		/* Interrupt at completion of Command Block */
503*30866Skarels #define NPDMP	0x2000		/* Dump 80186 On-Board Memory to Multibus */
504*30866Skarels #define NPLD	0x8000		/* Load 80186 On-board Memory from Multibus */
505*30866Skarels 
506*30866Skarels /*
507*30866Skarels  * CSR0 Count definitions. These are the lengths of the Command Blocks for the
508*30866Skarels  * CSR0 commands above (not counting the Command Word itself).
509*30866Skarels  */
510*30866Skarels 
511*30866Skarels #define LSTCNT	0
512*30866Skarels #define CMDCNT	2
513*30866Skarels #define BGNCNT	2
514*30866Skarels #define CBICNT	1
515*30866Skarels #define DMPCNT	5
516*30866Skarels #define LDCNT	5
517*30866Skarels #define IOCNT	5
518*30866Skarels 
519*30866Skarels /* Macros for reading and writing CSR's (Control and Status Registers) */
520*30866Skarels 
521*30866Skarels #define	WCSR0(x,y)	((x)->CSR0 = y)
522*30866Skarels #define	WCSR1(x,y)	((x)->CSR1 = y)
523*30866Skarels #define	WCSR2(x,y)	((x)->CSR2 = y)
524*30866Skarels #define	WCSR3(x,y)	((x)->CSR3 = y)
525*30866Skarels 
526*30866Skarels #define	RCSR0(x)	((x)->CSR0)
527*30866Skarels #define	RCSR1(x)	((x)->CSR1)
528*30866Skarels #define	RCSR2(x)	((x)->CSR2)
529*30866Skarels #define	RCSR3(x)	((x)->CSR3)
530*30866Skarels 
531*30866Skarels struct npconn {
532*30866Skarels 
533*30866Skarels 	struct npmaster *unit;	/* Unit number (board) of this connection */
534*30866Skarels 	unsign16 protocol;	/* Protocol used on this connection */
535*30866Skarels 	struct buf np_wbuf;	/* write buf structure for raw access */
536*30866Skarels 	struct buf np_rbuf;	/* read buf structure for raw access */
537*30866Skarels };
538*30866Skarels 
539*30866Skarels /* ICP Board Requests */
540*30866Skarels 
541*30866Skarels #define ICPLOAD  0x02
542*30866Skarels #define ICPDUMP  0x03
543*30866Skarels #define ICPPANIC 0x05
544*30866Skarels #define ICPPOLL  0x10
545*30866Skarels 
546*30866Skarels /*
547*30866Skarels  *	npdebug.h version 1.3
548*30866Skarels  *
549*30866Skarels  *	This version retrieved: 8/18/86 @ 18:58:46
550*30866Skarels  *	    This delta created: 8/18/86 @ 18:27:39
551*30866Skarels  */
552*30866Skarels 
553*30866Skarels /*
554*30866Skarels  * Debugging Constants
555*30866Skarels  */
556*30866Skarels 
557*30866Skarels #define	DEBENTRY	0x0001		/* debug entry points */
558*30866Skarels #define	DEBMEM		0x0002		/* debug memory */
559*30866Skarels #define	DEBREQ		0x0004		/* debug requests */
560*30866Skarels #define	DEBCQE		0x0008		/* debug cqe's */
561*30866Skarels #define	DEBCQ		0x0010		/* debug cq's */
562*30866Skarels #define	DEBMAINT	0x0020		/* debug maintainance requests */
563*30866Skarels #define	DEBINTR		0x0040		/* debug interrupt routines */
564*30866Skarels #define	DEBINIT		0x0080		/* debug initialization routines */
565*30866Skarels #define	DEBIFC		0x0100		/* debug Internal function codes */
566*30866Skarels #define	DEBIOCTL	0x0200		/* debug ioctl calls */
567*30866Skarels #define	DEBOPEN		0x0400		/* debug open calls */
568*30866Skarels #define	DEBIO		0x0800		/* debug read & write calls */
569*30866Skarels #define	DEBCSR		0x1000		/* debug CSR commands */
570*30866Skarels #define	DEBLOCK		0x2000		/* debug lock / unlock calls */
571