1*6938Ssam /* idcreg.h 4.1 82/05/26 */ 2*6938Ssam 3*6938Ssam #define NRB02SECT 40 /* RB02 sectors/track */ 4*6938Ssam #define NRB02TRK 2 /* RB02 tracks/cylinder */ 5*6938Ssam #define NRB02CYL 512 /* RB02 cylinders/disk */ 6*6938Ssam #define NRB80SECT 31 /* RB80 sectors/track */ 7*6938Ssam #define NRB80TRK 14 /* RB80 tracks/cylinder */ 8*6938Ssam #define NRB80CYL 559 /* RB80 cylinders/disk */ 9*6938Ssam 10*6938Ssam struct idcdevice 11*6938Ssam { 12*6938Ssam int idccsr; /* control status register */ 13*6938Ssam int idcbar; /* bus address register */ 14*6938Ssam int idcbcr; /* byte count register */ 15*6938Ssam int idcdar; /* disk address register */ 16*6938Ssam int idcmpr; /* multi-purpose register */ 17*6938Ssam int idceccpos; /* ecc position register */ 18*6938Ssam int idceccpat; /* ecc pattern register */ 19*6938Ssam int idcreset; /* master reset register */ 20*6938Ssam }; 21*6938Ssam 22*6938Ssam /* idccsr */ 23*6938Ssam #define IDC_TOI 0x10000000 /* time out inhibit */ 24*6938Ssam #define IDC_ASSI 0x08000000 /* automatic skip sector inhibit */ 25*6938Ssam #define IDC_R80 0x04000000 /* selected disk is R80 */ 26*6938Ssam #define IDC_MTN 0x02000000 /* maintenance */ 27*6938Ssam #define IDC_IR 0x01000000 /* interrupt request */ 28*6938Ssam #define IDC_SSE 0x00800000 /* R80 skip sector error */ 29*6938Ssam #define IDC_SSEI 0x00400000 /* R80 skip sector error inhibit */ 30*6938Ssam #define IDC_ECS 0x00300000 /* R80 ecc status */ 31*6938Ssam #define IDC_ECS_NONE 0x00000000 /* no data error */ 32*6938Ssam #define IDC_ECS_HARD 0x00200000 /* hard ecc error */ 33*6938Ssam #define IDC_ECS_SOFT 0x00300000 /* soft ecc error */ 34*6938Ssam #define IDC_ATTN 0x000f0000 /* attention bits */ 35*6938Ssam #define IDC_ERR 0x00008000 /* composite error */ 36*6938Ssam #define IDC_DE 0x00004000 /* drive error */ 37*6938Ssam #define IDC_NXM 0x00002000 /* non-existant memory */ 38*6938Ssam #define IDC_DLT 0x00001000 /* data late */ 39*6938Ssam #define IDC_HNF IDC_DLT /* header not found */ 40*6938Ssam #define IDC_DCK 0x00000800 /* data check */ 41*6938Ssam #define IDC_OPI 0x00000400 /* operation incomplete */ 42*6938Ssam #define IDC_DS 0x00000300 /* drive select bits */ 43*6938Ssam #define IDC_CRDY 0x00000080 /* controller ready */ 44*6938Ssam #define IDC_IE 0x00000040 /* interrupt enable */ 45*6938Ssam #define IDC_FUNC 0x0000000e /* function code */ 46*6938Ssam #define IDC_DRDY 0x00000001 /* drive ready */ 47*6938Ssam 48*6938Ssam #define IDC_HARD (IDC_NXM|IDC_DE) 49*6938Ssam 50*6938Ssam #define IDCCSR_BITS \ 51*6938Ssam "\20\35TOI\34ASSI\33R80\32MTN\31IR\30SSE\27SSEI\26ECS1\25ECS0\24ATN3\ 52*6938Ssam \23ATN2\22ATN1\21ATN0\20ERR\17DE\16NXM\15DLT\14DCK\13OPI\12DS1\11DS0\ 53*6938Ssam \10CRDY\7IE\4F2\3F1\2F0\1DRDY" 54*6938Ssam 55*6938Ssam /* function codes */ 56*6938Ssam #define IDC_NOP 000 /* no operation */ 57*6938Ssam #define IDC_WCHK 002 /* write check data */ 58*6938Ssam #define IDC_GETSTAT 004 /* get status */ 59*6938Ssam #define IDC_SEEK 006 /* seek */ 60*6938Ssam #define IDC_RHDR 010 /* read header */ 61*6938Ssam #define IDC_WRITE 012 /* write data */ 62*6938Ssam #define IDC_READ 014 /* read data */ 63*6938Ssam #define IDC_RNOHCHK 016 /* read data w/o header check */ 64*6938Ssam 65*6938Ssam /* idcmpr for RL02 get status command */ 66*6938Ssam #define IDCGS_RST 010 /* reset */ 67*6938Ssam #define IDCGS_GS 002 /* get status, must be 1 */ 68*6938Ssam #define IDCGS_M 001 /* mark, must be 1 */ 69*6938Ssam #define IDCGS_GETSTAT (IDCGS_RST|IDCGS_GS|IDCGS_M) 70*6938Ssam 71*6938Ssam /* RL02 status word */ 72*6938Ssam #define IDCDS_WDE 0100000 /* write data error */ 73*6938Ssam #define IDCDS_HCE 0040000 /* head current error */ 74*6938Ssam #define IDCDS_WL 0020000 /* write lock */ 75*6938Ssam #define IDCDS_SKTO 0010000 /* seek timeout */ 76*6938Ssam #define IDCDS_SPD 0004000 /* spindle error */ 77*6938Ssam #define IDCDS_WGE 0002000 /* write gate error */ 78*6938Ssam #define IDCDS_VC 0001000 /* volume check */ 79*6938Ssam #define IDCDS_DSE 0000400 /* drive select error */ 80*6938Ssam #define IDCDS_HS 0000100 /* head select */ 81*6938Ssam #define IDCDS_CO 0000040 /* cover open */ 82*6938Ssam #define IDCDS_HO 0000020 /* heads out */ 83*6938Ssam #define IDCDS_BH 0000010 /* brush home */ 84*6938Ssam #define IDCDS_STATE 0000007 /* drive state */ 85*6938Ssam 86*6938Ssam #define IDCRB02DS_BITS \ 87*6938Ssam "\10\20WDE\17HCE\16WL\15SKTO\14SPD\13WBE\12VC\11DSE\ 88*6938Ssam \7HS\6CO\5HO\4BH\3STC\2STB\1STA" 89*6938Ssam 90*6938Ssam /* R80 status word */ 91*6938Ssam #define IDCDS_WTP 0020000 /* write protect */ 92*6938Ssam #define IDCDS_DRDY 0010000 /* driver ready */ 93*6938Ssam #define IDCDS_ONCY 0004000 /* on cylinder */ 94*6938Ssam #define IDCDS_SKE 0002000 /* seek error */ 95*6938Ssam #define IDCDS_PLGV 0001000 /* plug valid */ 96*6938Ssam #define IDCDS_FLT 0000400 /* fault */ 97*6938Ssam 98*6938Ssam #define IDCRB80DS_BITS \ 99*6938Ssam "\10\16WTP\15DRDY\14ONCY\13SKE\12PLGV\11FLT\5SEC4\4SEC3\3SEC2\2SEC1\1SEC0" 100