xref: /csrg-svn/sys/vax/uba/idcreg.h (revision 29222)
123329Smckusick /*
2*29222Smckusick  * Copyright (c) 1982, 1986 Regents of the University of California.
323329Smckusick  * All rights reserved.  The Berkeley software License Agreement
423329Smckusick  * specifies the terms and conditions for redistribution.
523329Smckusick  *
6*29222Smckusick  *	@(#)idcreg.h	7.1 (Berkeley) 06/05/86
723329Smckusick  */
86938Ssam 
96938Ssam #define	NRB02SECT	40	/* RB02 sectors/track */
106938Ssam #define	NRB02TRK	2	/* RB02 tracks/cylinder */
116938Ssam #define	NRB02CYL	512	/* RB02 cylinders/disk */
126938Ssam #define	NRB80SECT	31	/* RB80 sectors/track */
136938Ssam #define	NRB80TRK	14	/* RB80 tracks/cylinder */
146938Ssam #define	NRB80CYL	559	/* RB80 cylinders/disk */
156938Ssam 
166938Ssam struct idcdevice
176938Ssam {
186938Ssam 	int	idccsr;		/* control status register */
196938Ssam 	int	idcbar;		/* bus address register */
206938Ssam 	int	idcbcr;		/* byte count register */
216938Ssam 	int	idcdar;		/* disk address register */
226938Ssam 	int	idcmpr;		/* multi-purpose register */
236938Ssam 	int	idceccpos;	/* ecc position register */
246938Ssam 	int	idceccpat;	/* ecc pattern register */
256938Ssam 	int	idcreset;	/* master reset register */
266938Ssam };
276938Ssam 
286938Ssam /* idccsr */
296938Ssam #define	IDC_TOI		0x10000000	/* time out inhibit */
306938Ssam #define	IDC_ASSI	0x08000000	/* automatic skip sector inhibit */
316938Ssam #define	IDC_R80		0x04000000	/* selected disk is R80 */
326938Ssam #define	IDC_MTN		0x02000000	/* maintenance */
336938Ssam #define	IDC_IR		0x01000000	/* interrupt request */
346938Ssam #define	IDC_SSE		0x00800000	/* R80 skip sector error */
356938Ssam #define	IDC_SSEI	0x00400000	/* R80 skip sector error inhibit */
366938Ssam #define	IDC_ECS		0x00300000	/* R80 ecc status */
376938Ssam #define	IDC_ECS_NONE	0x00000000	/*   no data error */
386938Ssam #define	IDC_ECS_HARD	0x00200000	/*   hard ecc error */
396938Ssam #define	IDC_ECS_SOFT	0x00300000	/*   soft ecc error */
406938Ssam #define	IDC_ATTN	0x000f0000	/* attention bits */
416938Ssam #define	IDC_ERR		0x00008000	/* composite error */
426938Ssam #define	IDC_DE		0x00004000	/* drive error */
436938Ssam #define	IDC_NXM		0x00002000	/* non-existant memory */
446938Ssam #define	IDC_DLT		0x00001000	/* data late */
456938Ssam #define	IDC_HNF		IDC_DLT		/* header not found */
466938Ssam #define	IDC_DCK		0x00000800	/* data check */
476938Ssam #define	IDC_OPI		0x00000400	/* operation incomplete */
486938Ssam #define	IDC_DS		0x00000300	/* drive select bits */
496938Ssam #define	IDC_CRDY	0x00000080	/* controller ready */
506938Ssam #define	IDC_IE		0x00000040	/* interrupt enable */
516938Ssam #define	IDC_FUNC	0x0000000e	/* function code */
526938Ssam #define	IDC_DRDY	0x00000001	/* drive ready */
536938Ssam 
546938Ssam #define	IDC_HARD	(IDC_NXM|IDC_DE)
556938Ssam 
566938Ssam #define	IDCCSR_BITS \
576938Ssam "\20\35TOI\34ASSI\33R80\32MTN\31IR\30SSE\27SSEI\26ECS1\25ECS0\24ATN3\
586938Ssam \23ATN2\22ATN1\21ATN0\20ERR\17DE\16NXM\15DLT\14DCK\13OPI\12DS1\11DS0\
596938Ssam \10CRDY\7IE\4F2\3F1\2F0\1DRDY"
606938Ssam 
616938Ssam /* function codes */
626938Ssam #define	IDC_NOP		000		/* no operation */
636938Ssam #define	IDC_WCHK	002		/* write check data */
646938Ssam #define	IDC_GETSTAT	004		/* get status */
656938Ssam #define	IDC_SEEK	006		/* seek */
666938Ssam #define	IDC_RHDR	010		/* read header */
676938Ssam #define	IDC_WRITE	012		/* write data */
686938Ssam #define	IDC_READ	014		/* read data */
696938Ssam #define	IDC_RNOHCHK	016		/* read data w/o header check */
706938Ssam 
716938Ssam /* idcmpr for RL02 get status command */
726938Ssam #define	IDCGS_RST	010		/* reset */
736938Ssam #define	IDCGS_GS	002		/* get status, must be 1 */
746938Ssam #define	IDCGS_M		001		/* mark, must be 1 */
756938Ssam #define	IDCGS_GETSTAT	(IDCGS_RST|IDCGS_GS|IDCGS_M)
766938Ssam 
776938Ssam /* RL02 status word */
786938Ssam #define	IDCDS_WDE	0100000		/* write data error */
796938Ssam #define	IDCDS_HCE	0040000		/* head current error */
806938Ssam #define	IDCDS_WL	0020000		/* write lock */
816938Ssam #define	IDCDS_SKTO	0010000		/* seek timeout */
826938Ssam #define	IDCDS_SPD	0004000		/* spindle error */
836938Ssam #define	IDCDS_WGE	0002000		/* write gate error */
846938Ssam #define	IDCDS_VC	0001000		/* volume check */
856938Ssam #define	IDCDS_DSE	0000400		/* drive select error */
866938Ssam #define	IDCDS_HS	0000100		/* head select */
876938Ssam #define	IDCDS_CO	0000040		/* cover open */
886938Ssam #define	IDCDS_HO	0000020		/* heads out */
896938Ssam #define	IDCDS_BH	0000010		/* brush home */
906938Ssam #define	IDCDS_STATE	0000007		/* drive state */
916938Ssam 
926938Ssam #define	IDCRB02DS_BITS \
936938Ssam "\10\20WDE\17HCE\16WL\15SKTO\14SPD\13WBE\12VC\11DSE\
946938Ssam \7HS\6CO\5HO\4BH\3STC\2STB\1STA"
956938Ssam 
966938Ssam /* R80 status word */
976938Ssam #define	IDCDS_WTP	0020000		/* write protect */
986938Ssam #define	IDCDS_DRDY	0010000		/* driver ready */
996938Ssam #define	IDCDS_ONCY	0004000		/* on cylinder */
1006938Ssam #define	IDCDS_SKE	0002000		/* seek error */
1016938Ssam #define	IDCDS_PLGV	0001000		/* plug valid */
1026938Ssam #define	IDCDS_FLT	0000400		/* fault */
1036938Ssam 
1046938Ssam #define	IDCRB80DS_BITS \
1056938Ssam "\10\16WTP\15DRDY\14ONCY\13SKE\12PLGV\11FLT\5SEC4\4SEC3\3SEC2\2SEC1\1SEC0"
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