1*38981Skarels /* 2*38981Skarels * Copyright (c) 1986 Regents of the University of California. 3*38981Skarels * All rights reserved. The Berkeley software License Agreement 4*38981Skarels * specifies the terms and conditions for redistribution. 5*38981Skarels * 6*38981Skarels * @(#)dmxreg.h 7.1 (Berkeley) 09/04/89 7*38981Skarels * 8*38981Skarels * Common structures and definitions 9*38981Skarels * for merged DMF and DMZ drivers. 10*38981Skarels */ 11*38981Skarels 12*38981Skarels /* 13*38981Skarels * Hardware registers per octet of asynchronous lines 14*38981Skarels */ 15*38981Skarels struct dmx_octet { 16*38981Skarels short csr; /* control-status register */ 17*38981Skarels short lpr; /* line parameter register */ 18*38981Skarels short rbuf; /* receiver buffer (ro) */ 19*38981Skarels union { 20*38981Skarels u_short irw; /* indirect register word */ 21*38981Skarels u_char irc[2]; /* " " bytes */ 22*38981Skarels } octun; 23*38981Skarels }; 24*38981Skarels 25*38981Skarels #define rsp rbuf /* receive silo parameter register (wo) */ 26*38981Skarels #define tbuf octun.irc[0] /* transmit buffer */ 27*38981Skarels #define tsc octun.irc[0] /* transmit silo count */ 28*38981Skarels #define rmstsc octun.irw /* rcv modem status, xmit silo count */ 29*38981Skarels #define rms octun.irc[1] /* receive modem status */ 30*38981Skarels #define lctms octun.irw /* line control, transmit modem status */ 31*38981Skarels #define tba octun.irw /* transmit buffer address */ 32*38981Skarels #define tcc octun.irw /* transmit character count */ 33*38981Skarels 34*38981Skarels /* bits in dmfcsr */ 35*38981Skarels #define DMF_TI 0100000 /* transmit interrupt */ 36*38981Skarels #define DMF_TIE 0040000 /* transmit interrupt enable */ 37*38981Skarels #define DMF_NXM 0030000 /* non-existent memory (which bit?) */ 38*38981Skarels #define DMF_LIN 0003400 /* transmit line number */ 39*38981Skarels #define DMF_RI 0000200 /* receiver interrupt */ 40*38981Skarels #define DMF_RIE 0000100 /* receiver interrupt enable */ 41*38981Skarels #define DMF_CLR 0000040 /* master reset */ 42*38981Skarels #define DMF_IAD 0000037 /* indirect address register */ 43*38981Skarels 44*38981Skarels #define DMF_IE (DMF_TIE|DMF_RIE) 45*38981Skarels 46*38981Skarels #define DMFIR_RMSTSC 000 /* select rmstsc indirect register */ 47*38981Skarels #define DMFIR_TBUF 000 /* select tbuf indirect register */ 48*38981Skarels #define DMFIR_LCR 010 /* select lcr indirect register */ 49*38981Skarels #define DMFIR_TBA 020 /* select tba indirect register */ 50*38981Skarels #define DMFIR_TCC 030 /* select tcc indirect register */ 51*38981Skarels 52*38981Skarels /* bits in dmflpr */ 53*38981Skarels #define BITS6 0010 /* 6 bits per character */ 54*38981Skarels #define BITS7 0020 /* 7 bits per character */ 55*38981Skarels #define BITS8 0030 /* 8 bits per character */ 56*38981Skarels #define PENABLE 0040 /* parity enable */ 57*38981Skarels #define EPAR 0100 /* even parity */ 58*38981Skarels #define TWOSB 0200 /* two stop bits */ 59*38981Skarels 60*38981Skarels #define DMF_SILOCNT 32 /* size of DMF output silo (per line) */ 61*38981Skarels 62*38981Skarels /* bits in dmfrbuf */ 63*38981Skarels #define DMF_DSC 0004000 /* data set change */ 64*38981Skarels #define DMF_PE 0010000 /* parity error */ 65*38981Skarels #define DMF_FE 0020000 /* framing error */ 66*38981Skarels #define DMF_DO 0040000 /* data overrun */ 67*38981Skarels 68*38981Skarels /* bits in dmfrmstsc */ 69*38981Skarels #define DMF_TSC 0x00ff /* transmit silo count */ 70*38981Skarels #define DMF_USRR 0x0400 /* user modem signal (pin 25) */ 71*38981Skarels #define DMF_SR 0x0800 /* secondary receive */ 72*38981Skarels #define DMF_CTS 0x1000 /* clear to send */ 73*38981Skarels #define DMF_CAR 0x2000 /* carrier detect */ 74*38981Skarels #define DMF_RNG 0x4000 /* ring */ 75*38981Skarels #define DMF_DSR 0x8000 /* data set ready */ 76*38981Skarels 77*38981Skarels /* bits in dmflctms (tms half) */ 78*38981Skarels #define DMF_USRW 0x0100 /* user modem signal (pin 18) */ 79*38981Skarels #define DMF_DTR 0x0200 /* data terminal ready */ 80*38981Skarels #define DMF_RATE 0x0400 /* data signal rate select */ 81*38981Skarels #define DMF_SRTS 0x0800 /* secondary request to send (dmf) */ 82*38981Skarels #define DMF_RTS 0x1000 /* request to send */ 83*38981Skarels #define DMF_PREEMPT 0x8000 /* preempt output */ 84*38981Skarels 85*38981Skarels /* bits in dmflctms (lc half) */ 86*38981Skarels #define DMF_MIE 0040 /* modem interrupt enable */ 87*38981Skarels #define DMF_FLUSH 0020 /* flush transmit silo */ 88*38981Skarels #define DMF_BRK 0010 /* send break bit */ 89*38981Skarels #define DMF_RE 0004 /* receive enable */ 90*38981Skarels #define DMF_AUTOX 0002 /* auto XON/XOFF */ 91*38981Skarels #define DMF_TE 0001 /* transmit enable */ 92*38981Skarels 93*38981Skarels #define DMF_ENA (DMF_MIE|DMF_RE|DMF_TE) 94*38981Skarels 95*38981Skarels /* flags for modem control */ 96*38981Skarels #define DMF_ON (DMF_DTR|DMF_RTS|DMF_ENA) 97*38981Skarels #define DMF_OFF 0 98*38981Skarels 99*38981Skarels /* bits added to dm lsr for DMGET/DMSET */ 100*38981Skarels #define DML_USR 0001000 /* usr modem sig, not a real DM bit */ 101*38981Skarels #define DML_DSR 0000400 /* data set ready, not a real DM bit */ 102