1*10014Ssam /* dhreg.h 4.1 82/12/30 */ 2*10014Ssam 3*10014Ssam /* 4*10014Ssam * DH-11 device register definitions. 5*10014Ssam */ 6*10014Ssam struct dhdevice { 7*10014Ssam union { 8*10014Ssam short dhcsr; /* control-status register */ 9*10014Ssam char dhcsrl; /* low byte for line select */ 10*10014Ssam } un; 11*10014Ssam short dhrcr; /* receive character register */ 12*10014Ssam short dhlpr; /* line parameter register */ 13*10014Ssam u_short dhcar; /* current address register */ 14*10014Ssam short dhbcr; /* byte count register */ 15*10014Ssam u_short dhbar; /* buffer active register */ 16*10014Ssam short dhbreak; /* break control register */ 17*10014Ssam short dhsilo; /* silo status register */ 18*10014Ssam }; 19*10014Ssam 20*10014Ssam /* Bits in dhcsr */ 21*10014Ssam #define DH_TI 0100000 /* transmit interrupt */ 22*10014Ssam #define DH_SI 0040000 /* storage interrupt */ 23*10014Ssam #define DH_TIE 0020000 /* transmit interrupt enable */ 24*10014Ssam #define DH_SIE 0010000 /* storage interrupt enable */ 25*10014Ssam #define DH_MC 0004000 /* master clear */ 26*10014Ssam #define DH_NXM 0002000 /* non-existant memory */ 27*10014Ssam #define DH_MM 0001000 /* maintenance mode */ 28*10014Ssam #define DH_CNI 0000400 /* clear non-existant memory interrupt */ 29*10014Ssam #define DH_RI 0000200 /* receiver interrupt */ 30*10014Ssam #define DH_RIE 0000100 /* receiver interrupt enable */ 31*10014Ssam 32*10014Ssam /* Bits in dhlpr */ 33*10014Ssam #define BITS6 01 34*10014Ssam #define BITS7 02 35*10014Ssam #define BITS8 03 36*10014Ssam #define TWOSB 04 37*10014Ssam #define PENABLE 020 38*10014Ssam /* DEC manuals incorrectly say this bit causes generation of even parity. */ 39*10014Ssam #define OPAR 040 40*10014Ssam #define HDUPLX 040000 41*10014Ssam 42*10014Ssam #define DH_IE (DH_TIE|DH_SIE|DH_RIE) 43*10014Ssam 44*10014Ssam /* Bits in dhrcr */ 45*10014Ssam #define DH_PE 0010000 /* parity error */ 46*10014Ssam #define DH_FE 0020000 /* framing error */ 47*10014Ssam #define DH_DO 0040000 /* data overrun */ 48