xref: /csrg-svn/sys/vax/uba/dhreg.h (revision 29210)
123321Smckusick /*
2*29210Smckusick  * Copyright (c) 1982, 1986 Regents of the University of California.
323321Smckusick  * All rights reserved.  The Berkeley software License Agreement
423321Smckusick  * specifies the terms and conditions for redistribution.
523321Smckusick  *
6*29210Smckusick  *	@(#)dhreg.h	7.1 (Berkeley) 06/05/86
723321Smckusick  */
810014Ssam 
910014Ssam /*
1010014Ssam  * DH-11 device register definitions.
1110014Ssam  */
1210014Ssam struct dhdevice {
1310014Ssam 	union {
1410014Ssam 		short	dhcsr;		/* control-status register */
1510014Ssam 		char	dhcsrl;		/* low byte for line select */
1610014Ssam 	} un;
1710014Ssam 	short	dhrcr;			/* receive character register */
1810014Ssam 	short	dhlpr;			/* line parameter register */
1910014Ssam 	u_short dhcar;			/* current address register */
2010014Ssam 	short	dhbcr;			/* byte count register */
2110014Ssam 	u_short	dhbar;			/* buffer active register */
2210014Ssam 	short	dhbreak;		/* break control register */
2310014Ssam 	short	dhsilo;			/* silo status register */
2410014Ssam };
2510014Ssam 
2610014Ssam /* Bits in dhcsr */
2710014Ssam #define	DH_TI	0100000		/* transmit interrupt */
2810014Ssam #define	DH_SI	0040000		/* storage interrupt */
2910014Ssam #define	DH_TIE	0020000		/* transmit interrupt enable */
3010014Ssam #define	DH_SIE	0010000		/* storage interrupt enable */
3110014Ssam #define	DH_MC	0004000		/* master clear */
3210014Ssam #define	DH_NXM	0002000		/* non-existant memory */
3310014Ssam #define	DH_MM	0001000		/* maintenance mode */
3410014Ssam #define	DH_CNI	0000400		/* clear non-existant memory interrupt */
3510014Ssam #define	DH_RI	0000200		/* receiver interrupt */
3610014Ssam #define	DH_RIE	0000100		/* receiver interrupt enable */
3710014Ssam 
3810014Ssam /* Bits in dhlpr */
3910014Ssam #define	BITS6	01
4010014Ssam #define	BITS7	02
4110014Ssam #define	BITS8	03
4210014Ssam #define	TWOSB	04
4310014Ssam #define	PENABLE	020
4410014Ssam /* DEC manuals incorrectly say this bit causes generation of even parity. */
4510014Ssam #define	OPAR	040
4610014Ssam #define	HDUPLX	040000
4710014Ssam 
4810014Ssam #define	DH_IE	(DH_TIE|DH_SIE|DH_RIE)
4910014Ssam 
5010014Ssam /* Bits in dhrcr */
5110014Ssam #define	DH_PE		0010000		/* parity error */
5210014Ssam #define	DH_FE		0020000		/* framing error */
5310014Ssam #define	DH_DO		0040000		/* data overrun */
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