1 /* dh.c 4.40 81/11/18 */ 2 3 #include "dh.h" 4 #if NDH > 0 5 /* 6 * DH-11/DM-11 driver 7 */ 8 #include "bk.h" 9 #include "../h/param.h" 10 #include "../h/conf.h" 11 #include "../h/dir.h" 12 #include "../h/user.h" 13 #include "../h/tty.h" 14 #include "../h/map.h" 15 #include "../h/pte.h" 16 #include "../h/buf.h" 17 #include "../h/vm.h" 18 #include "../h/ubareg.h" 19 #include "../h/ubavar.h" 20 #include "../h/bk.h" 21 #include "../h/clist.h" 22 #include "../h/file.h" 23 24 /* 25 * Definition of the driver for the auto-configuration program. 26 * There is one definition for the dh and one for the dm. 27 */ 28 int dhprobe(), dhattach(), dhrint(), dhxint(); 29 struct uba_device *dhinfo[NDH]; 30 u_short dhstd[] = { 0 }; 31 struct uba_driver dhdriver = 32 { dhprobe, 0, dhattach, 0, dhstd, "dh", dhinfo }; 33 34 int dmprobe(), dmattach(), dmintr(); 35 struct uba_device *dminfo[NDH]; 36 u_short dmstd[] = { 0 }; 37 struct uba_driver dmdriver = 38 { dmprobe, 0, dmattach, 0, dmstd, "dm", dminfo }; 39 40 struct dhdevice 41 { 42 union { 43 short dhcsr; /* control-status register */ 44 char dhcsrl; /* low byte for line select */ 45 } un; 46 short dhrcr; /* receive character register */ 47 short dhlpr; /* line parameter register */ 48 u_short dhcar; /* current address register */ 49 short dhbcr; /* byte count register */ 50 u_short dhbar; /* buffer active register */ 51 short dhbreak; /* break control register */ 52 short dhsilo; /* silo status register */ 53 }; 54 55 /* Bits in dhcsr */ 56 #define DH_TI 0100000 /* transmit interrupt */ 57 #define DH_SI 0040000 /* storage interrupt */ 58 #define DH_TIE 0020000 /* transmit interrupt enable */ 59 #define DH_SIE 0010000 /* storage interrupt enable */ 60 #define DH_MC 0004000 /* master clear */ 61 #define DH_NXM 0002000 /* non-existant memory */ 62 #define DH_MM 0001000 /* maintenance mode */ 63 #define DH_CNI 0000400 /* clear non-existant memory interrupt */ 64 #define DH_RI 0000200 /* receiver interrupt */ 65 #define DH_RIE 0000100 /* receiver interrupt enable */ 66 67 /* Bits in dhlpr */ 68 #define BITS6 01 69 #define BITS7 02 70 #define BITS8 03 71 #define TWOSB 04 72 #define PENABLE 020 73 /* DEC manuals incorrectly say this bit causes generation of even parity. */ 74 #define OPAR 040 75 #define HDUPLX 040000 76 77 #define DH_IE (DH_TIE|DH_SIE|DH_RIE) 78 79 /* Bits in dhrcr */ 80 #define DH_PE 0010000 /* parity error */ 81 #define DH_FE 0020000 /* framing error */ 82 #define DH_DO 0040000 /* data overrun */ 83 84 struct dmdevice 85 { 86 short dmcsr; /* control status register */ 87 short dmlstat; /* line status register */ 88 short dmpad1[2]; 89 }; 90 91 /* bits in dm csr */ 92 #define DM_RF 0100000 /* ring flag */ 93 #define DM_CF 0040000 /* carrier flag */ 94 #define DM_CTS 0020000 /* clear to send */ 95 #define DM_SRF 0010000 /* secondary receive flag */ 96 #define DM_CS 0004000 /* clear scan */ 97 #define DM_CM 0002000 /* clear multiplexor */ 98 #define DM_MM 0001000 /* maintenance mode */ 99 #define DM_STP 0000400 /* step */ 100 #define DM_DONE 0000200 /* scanner is done */ 101 #define DM_IE 0000100 /* interrupt enable */ 102 #define DM_SE 0000040 /* scan enable */ 103 #define DM_BUSY 0000020 /* scan busy */ 104 105 /* bits in dm lsr */ 106 #define DML_RNG 0000200 /* ring */ 107 #define DML_CAR 0000100 /* carrier detect */ 108 #define DML_CTS 0000040 /* clear to send */ 109 #define DML_SR 0000020 /* secondary receive */ 110 #define DML_ST 0000010 /* secondary transmit */ 111 #define DML_RTS 0000004 /* request to send */ 112 #define DML_DTR 0000002 /* data terminal ready */ 113 #define DML_LE 0000001 /* line enable */ 114 115 #define DML_ON (DML_DTR|DML_RTS|DML_LE) 116 #define DML_OFF (DML_LE) 117 118 /* 119 * Local variables for the driver 120 */ 121 short dhsar[NDH]; /* software copy of last bar */ 122 short dhsoftCAR[NDH]; 123 124 struct tty dh11[NDH*16]; 125 int ndh11 = NDH*16; 126 int dhact; /* mask of active dh's */ 127 int dhstart(), ttrstrt(); 128 129 /* 130 * The clist space is mapped by the driver onto each UNIBUS. 131 * The UBACVT macro converts a clist space address for unibus uban 132 * into an i/o space address for the DMA routine. 133 */ 134 int dh_ubinfo[MAXNUBA]; /* info about allocated unibus map */ 135 int cbase[MAXNUBA]; /* base address in unibus map */ 136 #define UBACVT(x, uban) (cbase[uban] + ((x)-(char *)cfree)) 137 138 /* 139 * Routine for configuration to force a dh to interrupt. 140 * Set to transmit at 9600 baud, and cause a transmitter interrupt. 141 */ 142 /*ARGSUSED*/ 143 dhprobe(reg) 144 caddr_t reg; 145 { 146 register int br, cvec; /* these are ``value-result'' */ 147 register struct dhdevice *dhaddr = (struct dhdevice *)reg; 148 149 #ifdef lint 150 br = 0; cvec = br; br = cvec; 151 dhrint(0); dhxint(0); 152 #endif 153 #ifndef notdef 154 dhaddr->un.dhcsr = DH_RIE|DH_MM|DH_RI; 155 DELAY(25); 156 dhaddr->un.dhcsr = 0; 157 #else 158 dhaddr->un.dhcsr = DH_TIE; 159 DELAY(5); 160 dhaddr->dhlpr = (B9600 << 10) | (B9600 << 6) | BITS7|PENABLE; 161 dhaddr->dhbcr = -1; 162 dhaddr->dhcar = 0; 163 dhaddr->dhbar = 1; 164 DELAY(100000); /* wait 1/10'th of a sec for interrupt */ 165 dhaddr->un.dhcsr = 0; 166 if (cvec && cvec != 0x200) 167 cvec -= 4; /* transmit -> receive */ 168 #endif 169 return (1); 170 } 171 172 /* 173 * Routine called to attach a dh. 174 */ 175 dhattach(ui) 176 struct uba_device *ui; 177 { 178 179 dhsoftCAR[ui->ui_unit] = ui->ui_flags; 180 } 181 182 /* 183 * Configuration routine to cause a dm to interrupt. 184 */ 185 dmprobe(reg) 186 caddr_t reg; 187 { 188 register int br, vec; /* value-result */ 189 register struct dmdevice *dmaddr = (struct dmdevice *)reg; 190 191 #ifdef lint 192 br = 0; vec = br; br = vec; 193 dmintr(); 194 #endif 195 dmaddr->dmcsr = DM_DONE|DM_IE; 196 DELAY(20); 197 dmaddr->dmcsr = 0; 198 return (1); 199 } 200 201 /*ARGSUSED*/ 202 dmattach(ui) 203 struct uba_device *ui; 204 { 205 206 /* no local state to set up */ 207 } 208 209 /* 210 * Open a DH11 line, mapping the clist onto the uba if this 211 * is the first dh on this uba. Turn on this dh if this is 212 * the first use of it. Also do a dmopen to wait for carrier. 213 */ 214 /*ARGSUSED*/ 215 dhopen(dev, flag) 216 dev_t dev; 217 { 218 register struct tty *tp; 219 register int unit, dh; 220 register struct dhdevice *addr; 221 register struct uba_device *ui; 222 int s; 223 224 unit = minor(dev); 225 dh = unit >> 4; 226 if (unit >= NDH*16 || (ui = dhinfo[dh])== 0 || ui->ui_alive == 0) { 227 u.u_error = ENXIO; 228 return; 229 } 230 tp = &dh11[unit]; 231 if (tp->t_state&XCLUDE && u.u_uid!=0) { 232 u.u_error = EBUSY; 233 return; 234 } 235 addr = (struct dhdevice *)ui->ui_addr; 236 tp->t_addr = (caddr_t)addr; 237 tp->t_oproc = dhstart; 238 tp->t_state |= WOPEN; 239 /* 240 * While setting up state for this uba and this dh, 241 * block uba resets which can clear the state. 242 */ 243 s = spl5(); 244 if (dh_ubinfo[ui->ui_ubanum] == 0) { 245 /* 512+ is a kludge to try to get around a hardware problem */ 246 dh_ubinfo[ui->ui_ubanum] = 247 uballoc(ui->ui_ubanum, (caddr_t)cfree, 248 512+nclist*sizeof(struct cblock), 0); 249 cbase[ui->ui_ubanum] = dh_ubinfo[ui->ui_ubanum]&0x3ffff; 250 } 251 if ((dhact&(1<<dh)) == 0) { 252 addr->un.dhcsr |= DH_IE; 253 dhact |= (1<<dh); 254 addr->dhsilo = 16; 255 } 256 splx(s); 257 /* 258 * If this is first open, initialze tty state to default. 259 */ 260 if ((tp->t_state&ISOPEN) == 0) { 261 ttychars(tp); 262 if (tp->t_ispeed == 0) { 263 tp->t_ispeed = B300; 264 tp->t_ospeed = B300; 265 tp->t_flags = ODDP|EVENP|ECHO; 266 } 267 dhparam(unit); 268 } 269 /* 270 * Wait for carrier, then process line discipline specific open. 271 */ 272 dmopen(dev); 273 (*linesw[tp->t_line].l_open)(dev, tp); 274 } 275 276 /* 277 * Close a DH11 line, turning off the DM11. 278 */ 279 /*ARGSUSED*/ 280 dhclose(dev, flag) 281 dev_t dev; 282 int flag; 283 { 284 register struct tty *tp; 285 register unit; 286 287 unit = minor(dev); 288 tp = &dh11[unit]; 289 (*linesw[tp->t_line].l_close)(tp); 290 ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); 291 if (tp->t_state&HUPCLS || (tp->t_state&ISOPEN)==0) 292 dmctl(unit, DML_OFF, DMSET); 293 ttyclose(tp); 294 } 295 296 dhread(dev) 297 dev_t dev; 298 { 299 register struct tty *tp; 300 301 tp = &dh11[minor(dev)]; 302 (*linesw[tp->t_line].l_read)(tp); 303 } 304 305 dhwrite(dev) 306 dev_t dev; 307 { 308 register struct tty *tp; 309 310 tp = &dh11[minor(dev)]; 311 (*linesw[tp->t_line].l_write)(tp); 312 } 313 314 /* 315 * DH11 receiver interrupt. 316 */ 317 dhrint(dh) 318 int dh; 319 { 320 register struct tty *tp; 321 register c; 322 register struct dhdevice *addr; 323 register struct tty *tp0; 324 register struct uba_device *ui; 325 int overrun = 0; 326 327 ui = dhinfo[dh]; 328 if (ui == 0 || ui->ui_alive == 0) 329 return; 330 addr = (struct dhdevice *)ui->ui_addr; 331 tp0 = &dh11[dh<<4]; 332 /* 333 * Loop fetching characters from the silo for this 334 * dh until there are no more in the silo. 335 */ 336 while ((c = addr->dhrcr) < 0) { 337 tp = tp0 + ((c>>8)&0xf); 338 if ((tp->t_state&ISOPEN)==0) { 339 wakeup((caddr_t)tp); 340 continue; 341 } 342 if (c & DH_PE) 343 if ((tp->t_flags&(EVENP|ODDP))==EVENP 344 || (tp->t_flags&(EVENP|ODDP))==ODDP ) 345 continue; 346 if ((c & DH_DO) && overrun == 0) { 347 printf("dh%d: silo overflow\n", dh); 348 overrun = 1; 349 } 350 if (c & DH_FE) 351 /* 352 * At framing error (break) generate 353 * a null (in raw mode, for getty), or a 354 * interrupt (in cooked/cbreak mode). 355 */ 356 if (tp->t_flags&RAW) 357 c = 0; 358 else 359 c = tun.t_intrc; 360 #if NBK > 0 361 if (tp->t_line == NETLDISC) { 362 c &= 0177; 363 BKINPUT(c, tp); 364 } else 365 #endif 366 (*linesw[tp->t_line].l_rint)(c, tp); 367 } 368 } 369 370 /* 371 * Ioctl for DH11. 372 */ 373 /*ARGSUSED*/ 374 dhioctl(dev, cmd, addr, flag) 375 caddr_t addr; 376 { 377 register struct tty *tp; 378 register unit = minor(dev); 379 380 tp = &dh11[unit]; 381 cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr); 382 if (cmd == 0) 383 return; 384 if (ttioctl(tp, cmd, addr, flag)) { 385 if (cmd==TIOCSETP || cmd==TIOCSETN) 386 dhparam(unit); 387 } else switch(cmd) { 388 case TIOCSBRK: 389 ((struct dhdevice *)(tp->t_addr))->dhbreak |= 1<<(unit&017); 390 break; 391 case TIOCCBRK: 392 ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); 393 break; 394 case TIOCSDTR: 395 dmctl(unit, DML_DTR|DML_RTS, DMBIS); 396 break; 397 case TIOCCDTR: 398 dmctl(unit, DML_DTR|DML_RTS, DMBIC); 399 break; 400 default: 401 u.u_error = ENOTTY; 402 } 403 } 404 405 /* 406 * Set parameters from open or stty into the DH hardware 407 * registers. 408 */ 409 dhparam(unit) 410 register int unit; 411 { 412 register struct tty *tp; 413 register struct dhdevice *addr; 414 register int lpar; 415 int s; 416 417 tp = &dh11[unit]; 418 addr = (struct dhdevice *)tp->t_addr; 419 /* 420 * Block interrupts so parameters will be set 421 * before the line interrupts. 422 */ 423 s = spl5(); 424 addr->un.dhcsrl = (unit&0xf) | DH_IE; 425 if ((tp->t_ispeed)==0) { 426 tp->t_state |= HUPCLS; 427 dmctl(unit, DML_OFF, DMSET); 428 return; 429 } 430 lpar = ((tp->t_ospeed)<<10) | ((tp->t_ispeed)<<6); 431 if ((tp->t_ispeed) == B134) 432 lpar |= BITS6|PENABLE|HDUPLX; 433 else if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT)) 434 lpar |= BITS8; 435 else 436 lpar |= BITS7|PENABLE; 437 if ((tp->t_flags&EVENP) == 0) 438 lpar |= OPAR; 439 if ((tp->t_ospeed) == B110) 440 lpar |= TWOSB; 441 addr->dhlpr = lpar; 442 splx(s); 443 } 444 445 /* 446 * DH11 transmitter interrupt. 447 * Restart each line which used to be active but has 448 * terminated transmission since the last interrupt. 449 */ 450 dhxint(dh) 451 int dh; 452 { 453 register struct tty *tp; 454 register struct dhdevice *addr; 455 short ttybit, bar, *sbar; 456 register struct uba_device *ui; 457 register int unit; 458 u_short cntr; 459 460 ui = dhinfo[dh]; 461 addr = (struct dhdevice *)ui->ui_addr; 462 if (addr->un.dhcsr & DH_NXM) { 463 addr->un.dhcsr |= DH_CNI; 464 printf("dh%d: NXM\n", dh); 465 } 466 sbar = &dhsar[dh]; 467 bar = *sbar & ~addr->dhbar; 468 unit = dh * 16; ttybit = 1; 469 addr->un.dhcsr &= (short)~DH_TI; 470 for (; bar; unit++, ttybit <<= 1) { 471 if (bar & ttybit) { 472 *sbar &= ~ttybit; 473 bar &= ~ttybit; 474 tp = &dh11[unit]; 475 tp->t_state &= ~BUSY; 476 if (tp->t_state&FLUSH) 477 tp->t_state &= ~FLUSH; 478 else { 479 addr->un.dhcsrl = (unit&017)|DH_IE; 480 /* 481 * Do arithmetic in a short to make up 482 * for lost 16&17 bits. 483 */ 484 cntr = addr->dhcar - 485 UBACVT(tp->t_outq.c_cf, ui->ui_ubanum); 486 ndflush(&tp->t_outq, (int)cntr); 487 } 488 if (tp->t_line) 489 (*linesw[tp->t_line].l_start)(tp); 490 else 491 dhstart(tp); 492 } 493 } 494 } 495 496 /* 497 * Start (restart) transmission on the given DH11 line. 498 */ 499 dhstart(tp) 500 register struct tty *tp; 501 { 502 register struct dhdevice *addr; 503 register int car, dh, unit, nch; 504 int s; 505 506 unit = minor(tp->t_dev); 507 dh = unit >> 4; 508 unit &= 0xf; 509 addr = (struct dhdevice *)tp->t_addr; 510 511 /* 512 * Must hold interrupts in following code to prevent 513 * state of the tp from changing. 514 */ 515 s = spl5(); 516 /* 517 * If it's currently active, or delaying, no need to do anything. 518 */ 519 if (tp->t_state&(TIMEOUT|BUSY|TTSTOP)) 520 goto out; 521 /* 522 * If there are sleepers, and output has drained below low 523 * water mark, wake up the sleepers. 524 */ 525 if ((tp->t_state&ASLEEP) && tp->t_outq.c_cc<=TTLOWAT(tp)) { 526 tp->t_state &= ~ASLEEP; 527 wakeup((caddr_t)&tp->t_outq); 528 } 529 /* 530 * Now restart transmission unless the output queue is 531 * empty. 532 */ 533 if (tp->t_outq.c_cc == 0) 534 goto out; 535 if (tp->t_flags&RAW || tp->t_local&LLITOUT) 536 nch = ndqb(&tp->t_outq, 0); 537 else { 538 nch = ndqb(&tp->t_outq, 0200); 539 /* 540 * If first thing on queue is a delay process it. 541 */ 542 if (nch == 0) { 543 nch = getc(&tp->t_outq); 544 timeout(ttrstrt, (caddr_t)tp, (nch&0x7f)+6); 545 tp->t_state |= TIMEOUT; 546 goto out; 547 } 548 } 549 /* 550 * If characters to transmit, restart transmission. 551 */ 552 if (nch) { 553 car = UBACVT(tp->t_outq.c_cf, dhinfo[dh]->ui_ubanum); 554 addr->un.dhcsrl = unit|((car>>12)&0x30)|DH_IE; 555 /* 556 * The following nonsense with short word 557 * is to make sure the dhbar |= word below 558 * is done with an interlocking bisw2 instruction. 559 */ 560 { short word = 1 << unit; 561 dhsar[dh] |= word; 562 addr->dhcar = car; 563 addr->dhbcr = -nch; 564 addr->dhbar |= word; 565 } 566 tp->t_state |= BUSY; 567 } 568 out: 569 splx(s); 570 } 571 572 /* 573 * Stop output on a line, e.g. for ^S/^Q or output flush. 574 */ 575 /*ARGSUSED*/ 576 dhstop(tp, flag) 577 register struct tty *tp; 578 { 579 register struct dhdevice *addr; 580 register int unit, s; 581 582 addr = (struct dhdevice *)tp->t_addr; 583 /* 584 * Block input/output interrupts while messing with state. 585 */ 586 s = spl5(); 587 if (tp->t_state & BUSY) { 588 /* 589 * Device is transmitting; stop output 590 * by selecting the line and setting the byte 591 * count to -1. We will clean up later 592 * by examining the address where the dh stopped. 593 */ 594 unit = minor(tp->t_dev); 595 addr->un.dhcsrl = (unit&017) | DH_IE; 596 if ((tp->t_state&TTSTOP)==0) 597 tp->t_state |= FLUSH; 598 addr->dhbcr = -1; 599 } 600 splx(s); 601 } 602 603 /* 604 * Reset state of driver if UBA reset was necessary. 605 * Reset the csrl and lpr registers on open lines, and 606 * restart transmitters. 607 */ 608 dhreset(uban) 609 int uban; 610 { 611 register int dh, unit; 612 register struct tty *tp; 613 register struct uba_device *ui; 614 int i; 615 616 if (dh_ubinfo[uban] == 0) 617 return; 618 ubarelse(uban, &dh_ubinfo[uban]); 619 dh_ubinfo[uban] = uballoc(uban, (caddr_t)cfree, 620 512+nclist*sizeof (struct cblock), 0); 621 cbase[uban] = dh_ubinfo[uban]&0x3ffff; 622 dh = 0; 623 for (dh = 0; dh < NDH; dh++) { 624 ui = dhinfo[dh]; 625 if (ui == 0 || ui->ui_alive == 0 || ui->ui_ubanum != uban) 626 continue; 627 printf(" dh%d", dh); 628 ((struct dhdevice *)ui->ui_addr)->un.dhcsr |= DH_IE; 629 ((struct dhdevice *)ui->ui_addr)->dhsilo = 16; 630 unit = dh * 16; 631 for (i = 0; i < 16; i++) { 632 tp = &dh11[unit]; 633 if (tp->t_state & (ISOPEN|WOPEN)) { 634 dhparam(unit); 635 dmctl(unit, DML_ON, DMSET); 636 tp->t_state &= ~BUSY; 637 dhstart(tp); 638 } 639 unit++; 640 } 641 } 642 dhtimer(); 643 } 644 645 /* 646 * At software clock interrupt time or after a UNIBUS reset 647 * empty all the dh silos. 648 */ 649 dhtimer() 650 { 651 register int dh; 652 653 for (dh = 0; dh < NDH; dh++) 654 dhrint(dh); 655 } 656 657 /* 658 * Turn on the line associated with dh dev. 659 */ 660 dmopen(dev) 661 dev_t dev; 662 { 663 register struct tty *tp; 664 register struct dmdevice *addr; 665 register struct uba_device *ui; 666 register int unit; 667 register int dm; 668 int s; 669 670 unit = minor(dev); 671 dm = unit >> 4; 672 tp = &dh11[unit]; 673 unit &= 0xf; 674 if (dm >= NDH || (ui = dminfo[dm]) == 0 || ui->ui_alive == 0 || 675 (dhsoftCAR[dm]&(1<<unit))) { 676 tp->t_state |= CARR_ON; 677 return; 678 } 679 addr = (struct dmdevice *)ui->ui_addr; 680 s = spl5(); 681 addr->dmcsr &= ~DM_SE; 682 while (addr->dmcsr & DM_BUSY) 683 ; 684 addr->dmcsr = unit; 685 addr->dmlstat = DML_ON; 686 if (addr->dmlstat&DML_CAR) 687 tp->t_state |= CARR_ON; 688 addr->dmcsr = DM_IE|DM_SE; 689 while ((tp->t_state&CARR_ON)==0) 690 sleep((caddr_t)&tp->t_rawq, TTIPRI); 691 splx(s); 692 } 693 694 /* 695 * Dump control bits into the DM registers. 696 */ 697 dmctl(dev, bits, how) 698 dev_t dev; 699 int bits, how; 700 { 701 register struct uba_device *ui; 702 register struct dmdevice *addr; 703 register int unit, s; 704 int dm; 705 706 unit = minor(dev); 707 dm = unit >> 4; 708 if ((ui = dminfo[dm]) == 0 || ui->ui_alive == 0) 709 return; 710 addr = (struct dmdevice *)ui->ui_addr; 711 s = spl5(); 712 addr->dmcsr &= ~DM_SE; 713 while (addr->dmcsr & DM_BUSY) 714 ; 715 addr->dmcsr = unit & 0xf; 716 switch(how) { 717 case DMSET: 718 addr->dmlstat = bits; 719 break; 720 case DMBIS: 721 addr->dmlstat |= bits; 722 break; 723 case DMBIC: 724 addr->dmlstat &= ~bits; 725 break; 726 } 727 addr->dmcsr = DM_IE|DM_SE; 728 splx(s); 729 } 730 731 /* 732 * DM11 interrupt; deal with carrier transitions. 733 */ 734 dmintr(dm) 735 register int dm; 736 { 737 register struct uba_device *ui; 738 register struct tty *tp; 739 register struct dmdevice *addr; 740 741 ui = dminfo[dm]; 742 if (ui == 0) 743 return; 744 addr = (struct dmdevice *)ui->ui_addr; 745 if (addr->dmcsr&DM_DONE) { 746 if (addr->dmcsr&DM_CF) { 747 tp = &dh11[(dm<<4)+(addr->dmcsr&0xf)]; 748 wakeup((caddr_t)&tp->t_rawq); 749 if ((tp->t_state&WOPEN)==0 && 750 (tp->t_local&LMDMBUF)) { 751 if (addr->dmlstat & DML_CAR) { 752 tp->t_state &= ~TTSTOP; 753 ttstart(tp); 754 } else if ((tp->t_state&TTSTOP) == 0) { 755 tp->t_state |= TTSTOP; 756 dhstop(tp, 0); 757 } 758 } else if ((addr->dmlstat&DML_CAR)==0) { 759 if ((tp->t_state&WOPEN)==0 && 760 (tp->t_local&LNOHANG)==0) { 761 gsignal(tp->t_pgrp, SIGHUP); 762 gsignal(tp->t_pgrp, SIGCONT); 763 addr->dmlstat = 0; 764 flushtty(tp, FREAD|FWRITE); 765 } 766 tp->t_state &= ~CARR_ON; 767 } else 768 tp->t_state |= CARR_ON; 769 } 770 addr->dmcsr = DM_IE|DM_SE; 771 } 772 } 773 #endif 774