1 /* ct.c 4.3 81/03/09 */ 2 3 #include "cat.h" 4 #if NCT > 0 5 /* 6 * GP DR11C driver used for C/A/T 7 */ 8 9 #include "../h/param.h" 10 #include "../h/tty.h" 11 #include "../h/pte.h" 12 #include "../h/map.h" 13 #include "../h/uba.h" 14 #include "../h/buf.h" 15 #include "../h/conf.h" 16 #include "../h/dir.h" 17 #include "../h/user.h" 18 19 #define PCAT (PZERO+9) 20 #define CATHIWAT 100 21 #define CATLOWAT 30 22 23 struct { 24 int catlock; 25 struct clist oq; 26 } cat; 27 28 struct device { 29 short catcsr; 30 short catbuf; 31 }; 32 33 int ctintr(); 34 35 ctopen(dev) 36 { 37 if (cat.catlock==0) { 38 cat.catlock++; 39 CATADDR->catcsr |= IENABLE; 40 } else 41 u.u_error = ENXIO; 42 } 43 44 ctclose() 45 { 46 cat.catlock = 0; 47 ctintr(); 48 } 49 50 ctwrite(dev) 51 { 52 register c; 53 extern lbolt; 54 55 while ((c=cpass()) >= 0) { 56 (void) spl5(); 57 while (cat.oq.c_cc > CATHIWAT) 58 sleep((caddr_t)&cat.oq, PCAT); 59 while (putc(c, &cat.oq) < 0) 60 sleep((caddr_t)&lbolt, PCAT); 61 ctintr(); 62 (void) spl0(); 63 } 64 } 65 66 ctintr() 67 { 68 register int c; 69 70 if (CATADDR->catcsr&DONE) { 71 if ((c = getc(&cat.oq)) >= 0) { 72 #if MH135A 73 c |= (c & 01) << 8; /* for dr11c bug */ 74 #endif 75 CATADDR->catbuf = c; 76 if (cat.oq.c_cc==0 || cat.oq.c_cc==CATLOWAT) 77 wakeup(&cat.oq); 78 } else { 79 if (cat.catlock==0) 80 CATADDR->catcsr = 0; 81 } 82 } 83 84 } 85 #endif 86