1*3217Swnj /* ct.c 4.5 81/03/11 */ 22621Swnj 33201Swnj #include "ct.h" 42621Swnj #if NCT > 0 52621Swnj /* 62621Swnj * GP DR11C driver used for C/A/T 72621Swnj */ 82621Swnj 92621Swnj #include "../h/param.h" 103201Swnj #include "../h/systm.h" 112621Swnj #include "../h/tty.h" 122621Swnj #include "../h/pte.h" 132621Swnj #include "../h/map.h" 142621Swnj #include "../h/buf.h" 153201Swnj #include "../h/ubareg.h" 163201Swnj #include "../h/ubavar.h" 172621Swnj #include "../h/conf.h" 182621Swnj #include "../h/dir.h" 192621Swnj #include "../h/user.h" 202621Swnj 212621Swnj #define PCAT (PZERO+9) 222621Swnj #define CATHIWAT 100 232621Swnj #define CATLOWAT 30 242621Swnj 253201Swnj struct ct_softc { 263201Swnj int sc_openf; 273201Swnj struct clist sc_oq; 283201Swnj } ct_softc[NCT]; 292621Swnj 303201Swnj struct ctdevice { 313201Swnj short ctcsr; 323201Swnj short ctbuf; 332621Swnj }; 342621Swnj 353201Swnj int ctprobe(), ctattach(), ctintr(); 363201Swnj struct uba_device *ctdinfo[NCT]; 373201Swnj u_short ctstd[] = { 0 }; 383201Swnj struct uba_driver ctdriver = 393201Swnj { ctprobe, 0, ctattach, 0, ctstd, "ct", ctdinfo }; 402621Swnj 41*3217Swnj #define CTUNIT(dev) (minor(dev)) 42*3217Swnj 433201Swnj ctprobe(reg) 443201Swnj caddr_t reg; 453201Swnj { 463201Swnj register struct ctdevice *ctaddr = (struct ctdevice *)reg; 473201Swnj 483201Swnj ctaddr->ctcsr = IENABLE; 493201Swnj DELAY(10000); 503201Swnj ctaddr->ctcsr = 0; 513201Swnj } 523201Swnj 53*3217Swnj /*ARGSUSED*/ 54*3217Swnj ctattach(ui) 55*3217Swnj register struct uba_device *ui; 56*3217Swnj { 57*3217Swnj 58*3217Swnj } 59*3217Swnj 602621Swnj ctopen(dev) 613201Swnj dev_t dev; 622621Swnj { 633201Swnj register struct ct_softc *sc; 643201Swnj register struct uba_device *ui; 653201Swnj register struct ctdevice *ctaddr; 663201Swnj 673201Swnj if (CTUNIT(dev) >= NCT || (ui = ctdinfo[CTUNIT(dev)]) == 0 || 683201Swnj ui->ui_alive == 0 || (sc = &ct_softc[CTUNIT(dev)])->sc_openf) { 692621Swnj u.u_error = ENXIO; 703201Swnj return; 713201Swnj } 723201Swnj sc->sc_openf = 1; 733201Swnj ctaddr->ctcsr |= IENABLE; 742621Swnj } 752621Swnj 763201Swnj ctclose(dev) 773201Swnj dev_t dev; 782621Swnj { 793201Swnj 803201Swnj ct_softc[CTUNIT(dev)].sc_openf = 0; 813201Swnj ctintr(dev); 822621Swnj } 832621Swnj 842621Swnj ctwrite(dev) 853201Swnj dev_t dev; 862621Swnj { 873201Swnj register struct ct_softc *sc = &ct_softc[CTUNIT(dev)]; 883201Swnj register int c; 892621Swnj 902621Swnj while ((c=cpass()) >= 0) { 913101Swnj (void) spl5(); 923201Swnj while (sc->sc_oq.c_cc > CATHIWAT) 933201Swnj sleep((caddr_t)&sc->sc_oq, PCAT); 943201Swnj while (putc(c, &sc->sc_oq) < 0) 952621Swnj sleep((caddr_t)&lbolt, PCAT); 963201Swnj ctintr(dev); 973101Swnj (void) spl0(); 982621Swnj } 992621Swnj } 1002621Swnj 1013201Swnj ctintr(dev) 1023201Swnj dev_t dev; 1032621Swnj { 1042621Swnj register int c; 1053201Swnj register struct ct_softc *sc = &ct_softc[CTUNIT(dev)]; 1063201Swnj register struct ctdevice *ctaddr = 1073201Swnj (struct ctdevice *)ctdinfo[CTUNIT(dev)]->ui_addr; 1082621Swnj 1093201Swnj if (ctaddr->ctcsr&DONE) { 1103201Swnj if ((c = getc(&sc->sc_oq)) >= 0) { 1112621Swnj #if MH135A 1122621Swnj c |= (c & 01) << 8; /* for dr11c bug */ 1132621Swnj #endif 1143201Swnj ctaddr->ctbuf = c; 1153201Swnj if (sc->sc_oq.c_cc==0 || sc->sc_oq.c_cc==CATLOWAT) 1163201Swnj wakeup(&sc->sc_oq); 1172621Swnj } else { 1183201Swnj if (sc->sc_openf==0) 1193201Swnj ctaddr->ctcsr = 0; 1202621Swnj } 1212621Swnj } 1222621Swnj 1232621Swnj } 1242621Swnj #endif 125