1*9803Ssam /* autoconf.c 4.7 82/12/17 */ 23264Swnj 3*9803Ssam #include "../machine/pte.h" 4*9803Ssam 53264Swnj #include "../h/param.h" 69186Ssam 79186Ssam #include "../vax/cpu.h" 89186Ssam #include "../vax/nexus.h" 99186Ssam #include "../vaxuba/ubareg.h" 109186Ssam #include "../vaxmba/mbareg.h" 119186Ssam #include "../vax/mtpr.h" 129186Ssam 133264Swnj #include "savax.h" 143264Swnj 153264Swnj #define UTR(i) ((struct uba_regs *)(NEX780+(i))) 163264Swnj #define UMA(i) ((caddr_t)UMEM780(i)) 173264Swnj #define MTR(i) ((struct mba_regs *)(NEX780+(i))) 183264Swnj 193264Swnj struct uba_regs *ubaddr780[] = { UTR(3), UTR(4), UTR(5), UTR(6) }; 203264Swnj caddr_t umaddr780[] = { UMA(0), UMA(1), UMA(2), UMA(3) }; 213264Swnj struct mba_regs *mbaddr780[] = { MTR(8), MTR(9), MTR(10), MTR(11) }; 223264Swnj 233264Swnj #undef UTR 243264Swnj #undef UMA 253264Swnj #undef MTR 263264Swnj 273264Swnj #define UTR(i) ((struct uba_regs *)(NEX750+(i))) 283264Swnj #define UMA(i) ((caddr_t)UMEM750(i)) 293264Swnj #define MTR(i) ((struct mba_regs *)(NEX750+(i))) 303264Swnj 313264Swnj struct uba_regs *ubaddr750[] = { UTR(8), UTR(9) }; 323264Swnj caddr_t umaddr750[] = { UMA(0), UMA(1) }; 333341Swnj struct mba_regs *mbaddr750[] = { MTR(4), MTR(5), MTR(6), MTR(7) }; 343264Swnj 353264Swnj #undef UTR 363264Swnj #undef UMA 373264Swnj #undef MTR 383264Swnj 397444Sroot #define UTR(i) ((struct uba_regs *)(NEX730+(i))) 407444Sroot #define UMA ((caddr_t)UMEM730) 413341Swnj 427444Sroot struct uba_regs *ubaddr730[] = { UTR(3) }; 437444Sroot caddr_t umaddr730[] = { UMA }; 443341Swnj 453341Swnj #undef UTR 463341Swnj #undef UMA 473341Swnj 483264Swnj configure() 493264Swnj { 503264Swnj union cpusid cpusid; 513348Swnj int nmba, nuba, i; 523264Swnj 533264Swnj cpusid.cpusid = mfpr(SID); 543264Swnj cpu = cpusid.cpuany.cp_type; 553264Swnj switch (cpu) { 563264Swnj 573264Swnj case VAX_780: 583264Swnj mbaddr = mbaddr780; 593264Swnj ubaddr = ubaddr780; 603264Swnj umaddr = umaddr780; 613348Swnj nmba = sizeof (mbaddr780) / sizeof (mbaddr780[0]); 623348Swnj nuba = sizeof (ubaddr780) / sizeof (ubaddr780[0]); 633264Swnj break; 643264Swnj 653264Swnj case VAX_750: 663264Swnj mbaddr = mbaddr750; 673264Swnj ubaddr = ubaddr750; 683264Swnj umaddr = umaddr750; 693348Swnj nmba = sizeof (mbaddr750) / sizeof (mbaddr750[0]); 703348Swnj nuba = 0; 713264Swnj break; 723341Swnj 737444Sroot case VAX_730: 747444Sroot ubaddr = ubaddr730; 757444Sroot umaddr = umaddr730; 763348Swnj nmba = nuba = 0; 773341Swnj break; 783264Swnj } 793348Swnj /* 803348Swnj * Forward into the past... 813348Swnj */ 827444Sroot /* 833348Swnj for (i = 0; i < nmba; i++) 843348Swnj if (!badloc(mbaddr[i])) 853348Swnj mbaddr[i]->mba_cr = MBCR_INIT; 867444Sroot */ 873348Swnj for (i = 0; i < nuba; i++) 883348Swnj if (!badloc(ubaddr[i])) 893348Swnj ubaddr[i]->uba_cr = UBACR_ADINIT; 907444Sroot if (cpu != VAX_780) 917444Sroot mtpr(IUR, 0); 923348Swnj /* give unibus devices a chance to recover... */ 933348Swnj if (nuba > 0) 943348Swnj DELAY(2000000); 953264Swnj } 96