1*9186Ssam /* autoconf.c 4.6 82/11/13 */ 23264Swnj 33264Swnj #include "../h/param.h" 43264Swnj #include "../h/pte.h" 5*9186Ssam 6*9186Ssam #include "../vax/cpu.h" 7*9186Ssam #include "../vax/nexus.h" 8*9186Ssam #include "../vaxuba/ubareg.h" 9*9186Ssam #include "../vaxmba/mbareg.h" 10*9186Ssam #include "../vax/mtpr.h" 11*9186Ssam 123264Swnj #include "savax.h" 133264Swnj 143264Swnj #define UTR(i) ((struct uba_regs *)(NEX780+(i))) 153264Swnj #define UMA(i) ((caddr_t)UMEM780(i)) 163264Swnj #define MTR(i) ((struct mba_regs *)(NEX780+(i))) 173264Swnj 183264Swnj struct uba_regs *ubaddr780[] = { UTR(3), UTR(4), UTR(5), UTR(6) }; 193264Swnj caddr_t umaddr780[] = { UMA(0), UMA(1), UMA(2), UMA(3) }; 203264Swnj struct mba_regs *mbaddr780[] = { MTR(8), MTR(9), MTR(10), MTR(11) }; 213264Swnj 223264Swnj #undef UTR 233264Swnj #undef UMA 243264Swnj #undef MTR 253264Swnj 263264Swnj #define UTR(i) ((struct uba_regs *)(NEX750+(i))) 273264Swnj #define UMA(i) ((caddr_t)UMEM750(i)) 283264Swnj #define MTR(i) ((struct mba_regs *)(NEX750+(i))) 293264Swnj 303264Swnj struct uba_regs *ubaddr750[] = { UTR(8), UTR(9) }; 313264Swnj caddr_t umaddr750[] = { UMA(0), UMA(1) }; 323341Swnj struct mba_regs *mbaddr750[] = { MTR(4), MTR(5), MTR(6), MTR(7) }; 333264Swnj 343264Swnj #undef UTR 353264Swnj #undef UMA 363264Swnj #undef MTR 373264Swnj 387444Sroot #define UTR(i) ((struct uba_regs *)(NEX730+(i))) 397444Sroot #define UMA ((caddr_t)UMEM730) 403341Swnj 417444Sroot struct uba_regs *ubaddr730[] = { UTR(3) }; 427444Sroot caddr_t umaddr730[] = { UMA }; 433341Swnj 443341Swnj #undef UTR 453341Swnj #undef UMA 463341Swnj 473264Swnj configure() 483264Swnj { 493264Swnj union cpusid cpusid; 503348Swnj int nmba, nuba, i; 513264Swnj 523264Swnj cpusid.cpusid = mfpr(SID); 533264Swnj cpu = cpusid.cpuany.cp_type; 543264Swnj switch (cpu) { 553264Swnj 563264Swnj case VAX_780: 573264Swnj mbaddr = mbaddr780; 583264Swnj ubaddr = ubaddr780; 593264Swnj umaddr = umaddr780; 603348Swnj nmba = sizeof (mbaddr780) / sizeof (mbaddr780[0]); 613348Swnj nuba = sizeof (ubaddr780) / sizeof (ubaddr780[0]); 623264Swnj break; 633264Swnj 643264Swnj case VAX_750: 653264Swnj mbaddr = mbaddr750; 663264Swnj ubaddr = ubaddr750; 673264Swnj umaddr = umaddr750; 683348Swnj nmba = sizeof (mbaddr750) / sizeof (mbaddr750[0]); 693348Swnj nuba = 0; 703264Swnj break; 713341Swnj 727444Sroot case VAX_730: 737444Sroot ubaddr = ubaddr730; 747444Sroot umaddr = umaddr730; 753348Swnj nmba = nuba = 0; 763341Swnj break; 773264Swnj } 783348Swnj /* 793348Swnj * Forward into the past... 803348Swnj */ 817444Sroot /* 823348Swnj for (i = 0; i < nmba; i++) 833348Swnj if (!badloc(mbaddr[i])) 843348Swnj mbaddr[i]->mba_cr = MBCR_INIT; 857444Sroot */ 863348Swnj for (i = 0; i < nuba; i++) 873348Swnj if (!badloc(ubaddr[i])) 883348Swnj ubaddr[i]->uba_cr = UBACR_ADINIT; 897444Sroot if (cpu != VAX_780) 907444Sroot mtpr(IUR, 0); 913348Swnj /* give unibus devices a chance to recover... */ 923348Swnj if (nuba > 0) 933348Swnj DELAY(2000000); 943264Swnj } 95