1*7444Sroot /* autoconf.c 4.5 82/07/15 */ 23264Swnj 33264Swnj #include "../h/param.h" 43264Swnj #include "../h/cpu.h" 53264Swnj #include "../h/nexus.h" 63264Swnj #include "../h/pte.h" 73264Swnj #include "../h/ubareg.h" 83264Swnj #include "../h/mbareg.h" 93264Swnj #include "../h/mtpr.h" 103264Swnj #include "savax.h" 113264Swnj 123264Swnj #define UTR(i) ((struct uba_regs *)(NEX780+(i))) 133264Swnj #define UMA(i) ((caddr_t)UMEM780(i)) 143264Swnj #define MTR(i) ((struct mba_regs *)(NEX780+(i))) 153264Swnj 163264Swnj struct uba_regs *ubaddr780[] = { UTR(3), UTR(4), UTR(5), UTR(6) }; 173264Swnj caddr_t umaddr780[] = { UMA(0), UMA(1), UMA(2), UMA(3) }; 183264Swnj struct mba_regs *mbaddr780[] = { MTR(8), MTR(9), MTR(10), MTR(11) }; 193264Swnj 203264Swnj #undef UTR 213264Swnj #undef UMA 223264Swnj #undef MTR 233264Swnj 243264Swnj #define UTR(i) ((struct uba_regs *)(NEX750+(i))) 253264Swnj #define UMA(i) ((caddr_t)UMEM750(i)) 263264Swnj #define MTR(i) ((struct mba_regs *)(NEX750+(i))) 273264Swnj 283264Swnj struct uba_regs *ubaddr750[] = { UTR(8), UTR(9) }; 293264Swnj caddr_t umaddr750[] = { UMA(0), UMA(1) }; 303341Swnj struct mba_regs *mbaddr750[] = { MTR(4), MTR(5), MTR(6), MTR(7) }; 313264Swnj 323264Swnj #undef UTR 333264Swnj #undef UMA 343264Swnj #undef MTR 353264Swnj 36*7444Sroot #define UTR(i) ((struct uba_regs *)(NEX730+(i))) 37*7444Sroot #define UMA ((caddr_t)UMEM730) 383341Swnj 39*7444Sroot struct uba_regs *ubaddr730[] = { UTR(3) }; 40*7444Sroot caddr_t umaddr730[] = { UMA }; 413341Swnj 423341Swnj #undef UTR 433341Swnj #undef UMA 443341Swnj 453264Swnj configure() 463264Swnj { 473264Swnj union cpusid cpusid; 483348Swnj int nmba, nuba, i; 493264Swnj 503264Swnj cpusid.cpusid = mfpr(SID); 513264Swnj cpu = cpusid.cpuany.cp_type; 523264Swnj switch (cpu) { 533264Swnj 543264Swnj case VAX_780: 553264Swnj mbaddr = mbaddr780; 563264Swnj ubaddr = ubaddr780; 573264Swnj umaddr = umaddr780; 583348Swnj nmba = sizeof (mbaddr780) / sizeof (mbaddr780[0]); 593348Swnj nuba = sizeof (ubaddr780) / sizeof (ubaddr780[0]); 603264Swnj break; 613264Swnj 623264Swnj case VAX_750: 633264Swnj mbaddr = mbaddr750; 643264Swnj ubaddr = ubaddr750; 653264Swnj umaddr = umaddr750; 663348Swnj nmba = sizeof (mbaddr750) / sizeof (mbaddr750[0]); 673348Swnj nuba = 0; 683264Swnj break; 693341Swnj 70*7444Sroot case VAX_730: 71*7444Sroot ubaddr = ubaddr730; 72*7444Sroot umaddr = umaddr730; 733348Swnj nmba = nuba = 0; 743341Swnj break; 753264Swnj } 763348Swnj /* 773348Swnj * Forward into the past... 783348Swnj */ 79*7444Sroot /* 803348Swnj for (i = 0; i < nmba; i++) 813348Swnj if (!badloc(mbaddr[i])) 823348Swnj mbaddr[i]->mba_cr = MBCR_INIT; 83*7444Sroot */ 843348Swnj for (i = 0; i < nuba; i++) 853348Swnj if (!badloc(ubaddr[i])) 863348Swnj ubaddr[i]->uba_cr = UBACR_ADINIT; 87*7444Sroot if (cpu != VAX_780) 88*7444Sroot mtpr(IUR, 0); 893348Swnj /* give unibus devices a chance to recover... */ 903348Swnj if (nuba > 0) 913348Swnj DELAY(2000000); 923264Swnj } 93