xref: /csrg-svn/sys/vax/stand/autoconf.c (revision 30547)
123218Smckusick /*
229291Smckusick  * Copyright (c) 1982, 1986 Regents of the University of California.
323218Smckusick  * All rights reserved.  The Berkeley software License Agreement
423218Smckusick  * specifies the terms and conditions for redistribution.
523218Smckusick  *
6*30547Skarels  *	@(#)autoconf.c	7.2 (Berkeley) 02/21/87
723218Smckusick  */
83264Swnj 
99803Ssam #include "../machine/pte.h"
109803Ssam 
113264Swnj #include "../h/param.h"
129186Ssam 
139186Ssam #include "../vax/cpu.h"
149186Ssam #include "../vax/nexus.h"
159186Ssam #include "../vaxuba/ubareg.h"
169186Ssam #include "../vaxmba/mbareg.h"
179186Ssam #include "../vax/mtpr.h"
189186Ssam 
193264Swnj #include "savax.h"
203264Swnj 
213264Swnj #define	UTR(i)	((struct uba_regs *)(NEX780+(i)))
223264Swnj #define	UMA(i)	((caddr_t)UMEM780(i))
233264Swnj #define	MTR(i)	((struct mba_regs *)(NEX780+(i)))
24*30547Skarels #define	UTRB(i)	((struct uba_regs *)(NEXB8600+(i)))
25*30547Skarels #define	UMAB(i)	((caddr_t)UMEMB8600(i))
26*30547Skarels #define	MTRB(i)	((struct mba_regs *)(NEXB8600+(i)))
273264Swnj 
28*30547Skarels struct	uba_regs *ubaddr780[] = {
29*30547Skarels 	UTR(3), UTR(4), UTR(5), UTR(6),
30*30547Skarels #if VAX8600
31*30547Skarels 	UTRB(3), UTRB(4), UTRB(5), UTRB(6),
32*30547Skarels #endif
33*30547Skarels };
34*30547Skarels caddr_t	umaddr780[] = {
35*30547Skarels 	UMA(0), UMA(1), UMA(2), UMA(3),
36*30547Skarels #if VAX8600
37*30547Skarels 	UMAB(0), UMAB(1), UMAB(2), UMAB(3),
38*30547Skarels #endif
39*30547Skarels };
40*30547Skarels struct	mba_regs *mbaddr780[] = {
41*30547Skarels 	MTR(8), MTR(9), MTR(10), MTR(11),
42*30547Skarels #if VAX8600
43*30547Skarels 	MTRB(8), MTRB(9), MTRB(10), MTRB(11),
44*30547Skarels #endif
45*30547Skarels };
463264Swnj 
473264Swnj #undef	UTR
483264Swnj #undef	UMA
493264Swnj #undef	MTR
503264Swnj 
513264Swnj #define	UTR(i)	((struct uba_regs *)(NEX750+(i)))
523264Swnj #define	UMA(i)	((caddr_t)UMEM750(i))
533264Swnj #define	MTR(i)	((struct mba_regs *)(NEX750+(i)))
543264Swnj 
553264Swnj struct	uba_regs *ubaddr750[] = { UTR(8), UTR(9) };
563264Swnj caddr_t	umaddr750[] = { UMA(0), UMA(1) };
573341Swnj struct	mba_regs *mbaddr750[] = { MTR(4), MTR(5), MTR(6), MTR(7) };
583264Swnj 
593264Swnj #undef	UTR
603264Swnj #undef	UMA
613264Swnj #undef	MTR
623264Swnj 
637444Sroot #define	UTR(i)	((struct uba_regs *)(NEX730+(i)))
647444Sroot #define	UMA	((caddr_t)UMEM730)
653341Swnj 
667444Sroot struct	uba_regs *ubaddr730[] = { UTR(3) };
677444Sroot caddr_t	umaddr730[] = { UMA };
683341Swnj 
693341Swnj #undef	UTR
703341Swnj #undef	UMA
713341Swnj 
723264Swnj configure()
733264Swnj {
743264Swnj 	union cpusid cpusid;
753348Swnj 	int nmba, nuba, i;
763264Swnj 
773264Swnj 	cpusid.cpusid = mfpr(SID);
783264Swnj 	cpu = cpusid.cpuany.cp_type;
793264Swnj 	switch (cpu) {
803264Swnj 
8124151Sbloom 	case VAX_8600:
823264Swnj 	case VAX_780:
833264Swnj 		mbaddr = mbaddr780;
843264Swnj 		ubaddr = ubaddr780;
853264Swnj 		umaddr = umaddr780;
86*30547Skarels 		if (cpu == VAX_8600) {
87*30547Skarels 			nmba = sizeof (mbaddr780) / sizeof (mbaddr780[0]);
88*30547Skarels 			nuba = sizeof (ubaddr780) / sizeof (ubaddr780[0]);
89*30547Skarels 		} else {
90*30547Skarels 			nmba = 4;
91*30547Skarels 			nuba = 4;
92*30547Skarels 		}
933264Swnj 		break;
943264Swnj 
953264Swnj 	case VAX_750:
963264Swnj 		mbaddr = mbaddr750;
973264Swnj 		ubaddr = ubaddr750;
983264Swnj 		umaddr = umaddr750;
993348Swnj 		nmba = sizeof (mbaddr750) / sizeof (mbaddr750[0]);
1003348Swnj 		nuba = 0;
1013264Swnj 		break;
1023341Swnj 
1037444Sroot 	case VAX_730:
1047444Sroot 		ubaddr = ubaddr730;
1057444Sroot 		umaddr = umaddr730;
1063348Swnj 		nmba = nuba = 0;
1073341Swnj 		break;
1083264Swnj 	}
1093348Swnj 	/*
1103348Swnj 	 * Forward into the past...
1113348Swnj 	 */
1127444Sroot /*
1133348Swnj 	for (i = 0; i < nmba; i++)
114*30547Skarels 		if (!badaddr(mbaddr[i], sizeof(long)))
1153348Swnj 			mbaddr[i]->mba_cr = MBCR_INIT;
1167444Sroot */
1173348Swnj 	for (i = 0; i < nuba; i++)
118*30547Skarels 		if (!badaddr(ubaddr[i], sizeof(long)))
1193348Swnj 			ubaddr[i]->uba_cr = UBACR_ADINIT;
12024151Sbloom 	if ((cpu != VAX_780) && (cpu != VAX_8600))
1217444Sroot 		mtpr(IUR, 0);
1223348Swnj 	/* give unibus devices a chance to recover... */
1233348Swnj 	if (nuba > 0)
1243348Swnj 		DELAY(2000000);
1253264Swnj }
126