1*23218Smckusick /* 2*23218Smckusick * Copyright (c) 1982 Regents of the University of California. 3*23218Smckusick * All rights reserved. The Berkeley software License Agreement 4*23218Smckusick * specifies the terms and conditions for redistribution. 5*23218Smckusick * 6*23218Smckusick * @(#)autoconf.c 6.2 (Berkeley) 06/08/85 7*23218Smckusick */ 83264Swnj 99803Ssam #include "../machine/pte.h" 109803Ssam 113264Swnj #include "../h/param.h" 129186Ssam 139186Ssam #include "../vax/cpu.h" 149186Ssam #include "../vax/nexus.h" 159186Ssam #include "../vaxuba/ubareg.h" 169186Ssam #include "../vaxmba/mbareg.h" 179186Ssam #include "../vax/mtpr.h" 189186Ssam 193264Swnj #include "savax.h" 203264Swnj 213264Swnj #define UTR(i) ((struct uba_regs *)(NEX780+(i))) 223264Swnj #define UMA(i) ((caddr_t)UMEM780(i)) 233264Swnj #define MTR(i) ((struct mba_regs *)(NEX780+(i))) 243264Swnj 253264Swnj struct uba_regs *ubaddr780[] = { UTR(3), UTR(4), UTR(5), UTR(6) }; 263264Swnj caddr_t umaddr780[] = { UMA(0), UMA(1), UMA(2), UMA(3) }; 273264Swnj struct mba_regs *mbaddr780[] = { MTR(8), MTR(9), MTR(10), MTR(11) }; 283264Swnj 293264Swnj #undef UTR 303264Swnj #undef UMA 313264Swnj #undef MTR 323264Swnj 333264Swnj #define UTR(i) ((struct uba_regs *)(NEX750+(i))) 343264Swnj #define UMA(i) ((caddr_t)UMEM750(i)) 353264Swnj #define MTR(i) ((struct mba_regs *)(NEX750+(i))) 363264Swnj 373264Swnj struct uba_regs *ubaddr750[] = { UTR(8), UTR(9) }; 383264Swnj caddr_t umaddr750[] = { UMA(0), UMA(1) }; 393341Swnj struct mba_regs *mbaddr750[] = { MTR(4), MTR(5), MTR(6), MTR(7) }; 403264Swnj 413264Swnj #undef UTR 423264Swnj #undef UMA 433264Swnj #undef MTR 443264Swnj 457444Sroot #define UTR(i) ((struct uba_regs *)(NEX730+(i))) 467444Sroot #define UMA ((caddr_t)UMEM730) 473341Swnj 487444Sroot struct uba_regs *ubaddr730[] = { UTR(3) }; 497444Sroot caddr_t umaddr730[] = { UMA }; 503341Swnj 513341Swnj #undef UTR 523341Swnj #undef UMA 533341Swnj 543264Swnj configure() 553264Swnj { 563264Swnj union cpusid cpusid; 573348Swnj int nmba, nuba, i; 583264Swnj 593264Swnj cpusid.cpusid = mfpr(SID); 603264Swnj cpu = cpusid.cpuany.cp_type; 613264Swnj switch (cpu) { 623264Swnj 633264Swnj case VAX_780: 643264Swnj mbaddr = mbaddr780; 653264Swnj ubaddr = ubaddr780; 663264Swnj umaddr = umaddr780; 673348Swnj nmba = sizeof (mbaddr780) / sizeof (mbaddr780[0]); 683348Swnj nuba = sizeof (ubaddr780) / sizeof (ubaddr780[0]); 693264Swnj break; 703264Swnj 713264Swnj case VAX_750: 723264Swnj mbaddr = mbaddr750; 733264Swnj ubaddr = ubaddr750; 743264Swnj umaddr = umaddr750; 753348Swnj nmba = sizeof (mbaddr750) / sizeof (mbaddr750[0]); 763348Swnj nuba = 0; 773264Swnj break; 783341Swnj 797444Sroot case VAX_730: 807444Sroot ubaddr = ubaddr730; 817444Sroot umaddr = umaddr730; 823348Swnj nmba = nuba = 0; 833341Swnj break; 843264Swnj } 853348Swnj /* 863348Swnj * Forward into the past... 873348Swnj */ 887444Sroot /* 893348Swnj for (i = 0; i < nmba; i++) 903348Swnj if (!badloc(mbaddr[i])) 913348Swnj mbaddr[i]->mba_cr = MBCR_INIT; 927444Sroot */ 933348Swnj for (i = 0; i < nuba; i++) 943348Swnj if (!badloc(ubaddr[i])) 953348Swnj ubaddr[i]->uba_cr = UBACR_ADINIT; 967444Sroot if (cpu != VAX_780) 977444Sroot mtpr(IUR, 0); 983348Swnj /* give unibus devices a chance to recover... */ 993348Swnj if (nuba > 0) 1003348Swnj DELAY(2000000); 1013264Swnj } 102