1*4740Swnj /* mtreg.h 4.1 81/11/04 */ 2*4740Swnj 3*4740Swnj /* 4*4740Swnj * TU78 registers. 5*4740Swnj */ 6*4740Swnj 7*4740Swnj struct mtdevice { 8*4740Swnj int mtcs; /* control status register */ 9*4740Swnj int mter; /* error register */ 10*4740Swnj int mtca; /* command address, rec cnt, skp cnt reg */ 11*4740Swnj int mtmr1; /* maintenance register */ 12*4740Swnj int mtas; /* attention summary register */ 13*4740Swnj int mtbc; /* byte count register */ 14*4740Swnj int mtdt; /* drive type register */ 15*4740Swnj int mtds; /* drive status register */ 16*4740Swnj int mtsn; /* serial number register */ 17*4740Swnj int mtmr2; /* maintenance register */ 18*4740Swnj int mtmr3; /* maintenance register */ 19*4740Swnj int mtner; /* non-data transfer error register */ 20*4740Swnj int mtncs[4]; /* non-data transfer command registers */ 21*4740Swnj int mtia; /* internal address */ 22*4740Swnj int mtid; /* internal data */ 23*4740Swnj }; 24*4740Swnj 25*4740Swnj /* mtcs */ 26*4740Swnj #define MT_GO 000001 /* go bit */ 27*4740Swnj #define MT_NOOP 000002 /* no operation */ 28*4740Swnj #define MT_UNLOAD 000004 /* unload tape */ 29*4740Swnj #define MT_REW 000006 /* rewind */ 30*4740Swnj #define MT_SENSE 000010 /* sense */ 31*4740Swnj #define MT_DSE 000012 /* data security erase */ 32*4740Swnj #define MT_WTMPE 000014 /* write phase encoded tape mark */ 33*4740Swnj #define MT_WTM MT_WTMPE /* generic write tape mark */ 34*4740Swnj #define MT_WTMGCR 000016 /* write GCR tape mark */ 35*4740Swnj #define MT_SFORW 000020 /* space forward record */ 36*4740Swnj #define MT_SREV 000022 /* space reverse record */ 37*4740Swnj #define MT_SFORWF 000024 /* space forward file */ 38*4740Swnj #define MT_SREVF 000026 /* space reverse file */ 39*4740Swnj #define MT_SFORWE 000030 /* space forward either */ 40*4740Swnj #define MT_SREVE 000032 /* space reverse either */ 41*4740Swnj #define MT_ERGPE 000034 /* erase tape, set PE */ 42*4740Swnj #define MT_ERASE MT_ERGPE /* generic erase tape */ 43*4740Swnj #define MT_ERGGCR 000036 /* erase tape, set GCR */ 44*4740Swnj #define MT_CLSPE 000040 /* close file PE */ 45*4740Swnj #define MT_CLS MT_CLSPE /* generic close file */ 46*4740Swnj #define MT_CLSGCR 000042 /* close file GCR */ 47*4740Swnj #define MT_SLEOT 000044 /* space to logical EOT */ 48*4740Swnj #define MT_SFLEOT 000046 /* space forward file, stop on LEOT */ 49*4740Swnj #define MT_WCHFWD 000050 /* write check forward */ 50*4740Swnj #define MT_WCHREV 000056 /* write check reverse */ 51*4740Swnj #define MT_WRITEPE 000060 /* write phase encoded */ 52*4740Swnj #define MT_WRITE MT_WRITEPE /* generic write */ 53*4740Swnj #define MT_WRITEGCR 000062 /* write group coded */ 54*4740Swnj #define MT_READ 000070 /* read forward */ 55*4740Swnj #define MT_EXSNS 000072 /* read extended sense error log */ 56*4740Swnj #define MT_READREV 000076 /* read reverse */ 57*4740Swnj #define MT_GCR 000002 /* make generic ops GCR ops */ 58*4740Swnj 59*4740Swnj /* mtds */ 60*4740Swnj #define MTDS_RDY 0100000 /* tape ready */ 61*4740Swnj #define MTDS_PRES 0040000 /* tape unit has power */ 62*4740Swnj #define MTDS_ONL 0020000 /* online */ 63*4740Swnj #define MTDS_REW 0010000 /* tape rewinding */ 64*4740Swnj #define MTDS_PE 0004000 /* tape set for phase encoded */ 65*4740Swnj #define MTDS_BOT 0002000 /* tape at BOT */ 66*4740Swnj #define MTDS_EOT 0001000 /* tape at EOT */ 67*4740Swnj #define MTDS_FPT 0000400 /* write protected */ 68*4740Swnj #define MTDS_AVAIL 0000200 /* unit available */ 69*4740Swnj #define MTDS_SHR 0000100 /* unit is shared */ 70*4740Swnj #define MTDS_MAINT 0000040 /* maintenance mode */ 71*4740Swnj #define MTDS_DSE 0000020 /* DSE in progress */ 72*4740Swnj 73*4740Swnj #define MTDS_BITS \ 74*4740Swnj "\10\20RDY\17PRES\16ONL\15REW\14PE\13BOT\12EOT\11FPT\10AVAIL\ 75*4740Swnj \7SHR\6MAINT\5DSE" 76*4740Swnj 77*4740Swnj /* mter */ 78*4740Swnj #define MTER_INTCODE 0377 /* mask for interrupt code */ 79*4740Swnj 80*4740Swnj /* interrupt codes */ 81*4740Swnj #define MTER_DONE 001 /* operation complete */ 82*4740Swnj #define MTER_TM 002 /* unexpected tape mark */ 83*4740Swnj #define MTER_BOT 003 /* unexpected BOT detected */ 84*4740Swnj #define MTER_EOT 004 /* tape positioned beyond EOT */ 85*4740Swnj #define MTER_LEOT 005 /* unexpected LEOT detected */ 86*4740Swnj #define MTER_NOOP 006 /* no-op completed */ 87*4740Swnj #define MTER_RWDING 007 /* rewinding */ 88*4740Swnj #define MTER_FPT 010 /* write protect error */ 89*4740Swnj #define MTER_NOTRDY 011 /* not ready */ 90*4740Swnj #define MTER_NOTAVL 012 /* not available */ 91*4740Swnj #define MTER_OFFLINE 013 /* offline */ 92*4740Swnj #define MTER_NONEX 014 /* unit does not exist */ 93*4740Swnj #define MTER_NOTCAP 015 /* not capable */ 94*4740Swnj #define MTER_ONLINE 017 /* tape came online */ 95*4740Swnj #define MTER_LONGREC 020 /* long tape record */ 96*4740Swnj #define MTER_SHRTREC 021 /* short tape record */ 97*4740Swnj #define MTER_RETRY 022 /* retry */ 98*4740Swnj #define MTER_RDOPP 023 /* read opposite */ 99*4740Swnj #define MTER_UNREAD 024 /* unreadable */ 100*4740Swnj #define MTER_ERROR 025 /* error */ 101*4740Swnj #define MTER_EOTERR 026 /* EOT error */ 102*4740Swnj #define MTER_BADTAPE 027 /* tape position lost */ 103*4740Swnj #define MTER_TMFLTA 030 /* TM fault A */ 104*4740Swnj #define MTER_TUFLTA 031 /* TU fault A */ 105*4740Swnj #define MTER_TMFLTB 032 /* TM fault B */ 106*4740Swnj #define MTER_MBFLT 034 /* Massbus fault */ 107*4740Swnj #define MTER_KEYFAIL 077 /* keypad entry error */ 108*4740Swnj 109*4740Swnj /* mtdt */ 110*4740Swnj #define MTDT_NSA 0100000 /* not sector addressed; always 1 */ 111*4740Swnj #define MTDT_TAP 0040000 /* tape; always 1 */ 112*4740Swnj #define MTDT_MOH 0020000 /* moving head; always 0 */ 113*4740Swnj #define MTDT_7CH 0010000 /* 7 channel; always 0 */ 114*4740Swnj #define MTDT_DRQ 0004000 /* drive request required */ 115*4740Swnj #define MTDT_SPR 0002000 /* slave present; always 1 ??? */ 116*4740Swnj /* bit 9 is spare */ 117*4740Swnj /* bits 8-0 are formatter/transport type */ 118*4740Swnj 119*4740Swnj /* mtid */ 120*4740Swnj #define MTID_RDY 0100000 /* controller ready */ 121*4740Swnj #define MTID_CLR 0040000 /* controller clear */ 122*4740Swnj 123*4740Swnj #define b_repcnt b_bcount 124*4740Swnj #define b_command b_resid 125