xref: /csrg-svn/sys/vax/mba/mt.c (revision 9789)
1*9789Ssam /*	mt.c	4.15	82/12/17	*/
24736Swnj 
34736Swnj #include "mu.h"
44736Swnj #if NMT > 0
54736Swnj /*
64736Swnj  * TM78/TU78 tape driver
74736Swnj  *
84736Swnj  *	Behavior in complex error situations is uncertain...
94736Swnj  *
104736Swnj  * TODO:
114736Swnj  *	test error recovery
124736Swnj  *	add odd byte count kludge from VMS driver
134736Swnj  *	write dump routine
144736Swnj  */
15*9789Ssam #include "../machine/pte.h"
16*9789Ssam 
174736Swnj #include "../h/param.h"
184736Swnj #include "../h/systm.h"
194736Swnj #include "../h/buf.h"
204736Swnj #include "../h/conf.h"
214736Swnj #include "../h/dir.h"
224736Swnj #include "../h/file.h"
234736Swnj #include "../h/user.h"
244736Swnj #include "../h/map.h"
257637Ssam #include "../h/ioctl.h"
264736Swnj #include "../h/mtio.h"
274736Swnj #include "../h/cmap.h"
287740Sroot #include "../h/uio.h"
294736Swnj 
308471Sroot #include "../vax/cpu.h"
318471Sroot #include "../vaxmba/mbareg.h"
328471Sroot #include "../vaxmba/mbavar.h"
338471Sroot #include "../vaxmba/mtreg.h"
344736Swnj 
354736Swnj struct	buf	rmtbuf[NMT];
364736Swnj struct	buf	cmtbuf[NMT];
374736Swnj 
384736Swnj short	mttypes[] =
394736Swnj 	{ MBDT_TU78, 0 };
404736Swnj struct	mba_device *mtinfo[NMT];
414736Swnj int	mtattach(), mtslave(), mtustart(), mtstart(), mtndtint(), mtdtint();
424736Swnj struct	mba_driver mtdriver =
434736Swnj     { mtattach, mtslave, mtustart, mtstart, mtdtint, mtndtint,
444736Swnj       mttypes, "mt", "mu", mtinfo };
454736Swnj 
464736Swnj #define MASKREG(r)	((r) & 0xffff)
474736Swnj 
484736Swnj /* bits in minor device */
494736Swnj #define	MUUNIT(dev)	(minor(dev)&03)
504736Swnj #define	H_NOREWIND	04
514736Swnj #define	H_6250BPI	08
524736Swnj 
534736Swnj #define MTUNIT(dev)	(mutomt[MUUNIT(dev)])
544736Swnj 
554736Swnj #define	INF	(daddr_t)1000000L	/* a block number that wont exist */
564736Swnj 
574736Swnj struct	mu_softc {
584736Swnj 	char	sc_openf;
594736Swnj 	char	sc_flags;
604736Swnj 	daddr_t	sc_blkno;
614736Swnj 	daddr_t	sc_nxrec;
624736Swnj 	u_short	sc_erreg;
634736Swnj 	u_short	sc_dsreg;
644736Swnj 	short	sc_resid;
654736Swnj 	short	sc_dens;
664736Swnj 	struct	mba_device *sc_mi;
674736Swnj 	int	sc_slave;
684736Swnj } mu_softc[NMU];
694736Swnj short	mutomt[NMU];
704736Swnj 
714736Swnj /*
724736Swnj  * Bits for sc_flags.
734736Swnj  */
744736Swnj #define	H_WRITTEN 1	/* last operation was a write */
754736Swnj 
764736Swnj char	mtds_bits[] = MTDS_BITS;
774736Swnj 
784736Swnj /*ARGSUSED*/
794736Swnj mtattach(mi)
804736Swnj 	struct mba_device *mi;
814736Swnj {
828652Sroot 
834736Swnj }
844736Swnj 
857431Skre mtslave(mi, ms, sn)
864736Swnj 	struct mba_device *mi;
874736Swnj 	struct mba_slave *ms;
887431Skre 	int sn;
894736Swnj {
904736Swnj 	register struct mu_softc *sc = &mu_softc[ms->ms_unit];
914736Swnj 	register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv;
924736Swnj 	int s = spl7(), rtn = 0;
934736Swnj 
944736Swnj 	mtaddr->mtas = -1;
957431Skre 	mtaddr->mtncs[sn] = MT_SENSE|MT_GO;
964736Swnj 	while (mtaddr->mtas == 0)
974736Swnj 		;
984736Swnj 	if ((mtaddr->mtner & MTER_INTCODE) == MTER_DONE &&
994736Swnj 	    (mtaddr->mtds & MTDS_PRES)) {
1004736Swnj 		sc->sc_mi = mi;
1017431Skre 		sc->sc_slave = sn;
1024736Swnj 		mutomt[ms->ms_unit] = mi->mi_unit;
1034736Swnj 		rtn = 1;
1044736Swnj 	}
1054736Swnj 	mtaddr->mtas = mtaddr->mtas;
1064736Swnj 	splx(s);
1074736Swnj 	return (rtn);
1084736Swnj }
1094736Swnj 
1104736Swnj mtopen(dev, flag)
1114736Swnj 	dev_t dev;
1124736Swnj 	int flag;
1134736Swnj {
1144736Swnj 	register int muunit;
1154736Swnj 	register struct mba_device *mi;
1164736Swnj 	register struct mu_softc *sc;
1174736Swnj 	int olddens, dens;
1184736Swnj 
1194736Swnj 	muunit = MUUNIT(dev);
1204736Swnj 	if (muunit >= NMU || (sc = &mu_softc[muunit])->sc_openf ||
1218581Sroot 	    (mi = mtinfo[MTUNIT(dev)]) == 0 || mi->mi_alive == 0)
1228581Sroot 		return (ENXIO);
1234736Swnj 	olddens = sc->sc_dens;
1244736Swnj 	dens = sc->sc_dens = (minor(dev)&H_6250BPI) ? MT_GCR : 0;
1254736Swnj 	mtcommand(dev, MT_SENSE, 1);
1264736Swnj 	sc->sc_dens = olddens;
1274736Swnj 	if ((sc->sc_dsreg & MTDS_ONL) == 0) {
1284736Swnj 		uprintf("mu%d: not online\n", muunit);
1298581Sroot 		return (EIO);
1304736Swnj 	}
1314736Swnj 	if ((flag&FWRITE) && (sc->sc_dsreg&MTDS_FPT)) {
1324736Swnj 		uprintf("mu%d: no write ring\n", muunit);
1338581Sroot 		return (EIO);
1344736Swnj 	}
1354736Swnj 	if ((sc->sc_dsreg & MTDS_BOT) == 0 && (flag&FWRITE) &&
1364736Swnj 	    dens != sc->sc_dens) {
1374736Swnj 		uprintf("mu%d: can't change density in mid-tape\n", muunit);
1388581Sroot 		return (EIO);
1394736Swnj 	}
1404736Swnj 	sc->sc_openf = 1;
1414736Swnj 	sc->sc_blkno = (daddr_t)0;
1424736Swnj 	sc->sc_nxrec = INF;
1434736Swnj 	sc->sc_flags = 0;
1444736Swnj 	sc->sc_dens = dens;
1458581Sroot 	return (0);
1464736Swnj }
1474736Swnj 
1484736Swnj mtclose(dev, flag)
1494736Swnj 	register dev_t dev;
1504736Swnj 	register flag;
1514736Swnj {
1524736Swnj 	register struct mu_softc *sc = &mu_softc[MUUNIT(dev)];
1534736Swnj 
1544736Swnj 	if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN)))
1554736Swnj 		mtcommand(dev, MT_CLS|sc->sc_dens, 1);
1564736Swnj 	if ((minor(dev)&H_NOREWIND) == 0)
1574736Swnj 		mtcommand(dev, MT_REW, 0);
1584736Swnj 	sc->sc_openf = 0;
1594736Swnj }
1604736Swnj 
1614736Swnj mtcommand(dev, com, count)
1624736Swnj 	dev_t dev;
1634736Swnj 	int com, count;
1644736Swnj {
1654736Swnj 	register struct buf *bp;
1665437Sroot 	register int s;
1674736Swnj 
1684736Swnj 	bp = &cmtbuf[MTUNIT(dev)];
1695437Sroot 	s = spl5();
1704736Swnj 	while (bp->b_flags&B_BUSY) {
1714736Swnj 		if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE))
1724736Swnj 			break;
1734736Swnj 		bp->b_flags |= B_WANTED;
1744736Swnj 		sleep((caddr_t)bp, PRIBIO);
1754736Swnj 	}
1764736Swnj 	bp->b_flags = B_BUSY|B_READ;
1775437Sroot 	splx(s);
1784736Swnj 	bp->b_dev = dev;
1794736Swnj 	bp->b_command = com;
1804736Swnj 	bp->b_repcnt = count;
1814736Swnj 	bp->b_blkno = 0;
1824736Swnj 	mtstrategy(bp);
1834736Swnj 	if (count == 0)
1844736Swnj 		return;
1854736Swnj 	iowait(bp);
1864736Swnj 	if (bp->b_flags&B_WANTED)
1874736Swnj 		wakeup((caddr_t)bp);
1884736Swnj 	bp->b_flags &= B_ERROR;
1894736Swnj }
1904736Swnj 
1914736Swnj mtstrategy(bp)
1924736Swnj 	register struct buf *bp;
1934736Swnj {
1944736Swnj 	register struct mba_device *mi = mtinfo[MTUNIT(bp->b_dev)];
1954736Swnj 	register struct buf *dp;
1965437Sroot 	register int s;
1974736Swnj 
1984736Swnj 	bp->av_forw = NULL;
1994736Swnj 	dp = &mi->mi_tab;
2005437Sroot 	s = spl5();
2014736Swnj 	if (dp->b_actf == NULL)
2024736Swnj 		dp->b_actf = bp;
2034736Swnj 	else
2044736Swnj 		dp->b_actl->av_forw = bp;
2054736Swnj 	dp->b_actl = bp;
2064736Swnj 	if (dp->b_active == 0)
2074736Swnj 		mbustart(mi);
2085437Sroot 	splx(s);
2094736Swnj }
2104736Swnj 
2114736Swnj mtustart(mi)
2124736Swnj 	register struct mba_device *mi;
2134736Swnj {
2144736Swnj 	register struct mtdevice *mtaddr =
2154736Swnj 	    (struct mtdevice *)mi->mi_drv;
2164736Swnj 	register struct buf *bp = mi->mi_tab.b_actf;
2174736Swnj 	register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)];
2184736Swnj 	daddr_t blkno;
2194736Swnj 
2204736Swnj 	sc->sc_flags &= ~H_WRITTEN;
2214736Swnj 	if (sc->sc_openf < 0) {
2224736Swnj 		bp->b_flags |= B_ERROR;
2234736Swnj 		return (MBU_NEXT);
2244736Swnj 	}
2254736Swnj 	if (bp != &cmtbuf[MTUNIT(bp->b_dev)]) {
2267380Ssam 		if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) {
2274736Swnj 			bp->b_flags |= B_ERROR;
2284736Swnj 			bp->b_error = ENXIO;
2294736Swnj 			return (MBU_NEXT);
2304736Swnj 		}
2317380Ssam 		if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec &&
2324736Swnj 		    bp->b_flags&B_READ) {
2334736Swnj 			bp->b_resid = bp->b_bcount;
2344736Swnj 			clrbuf(bp);
2354736Swnj 			return (MBU_NEXT);
2364736Swnj 		}
2374736Swnj 		if ((bp->b_flags&B_READ)==0)
2387380Ssam 			sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1;
2394736Swnj 	} else {
2404736Swnj 		mtaddr->mtncs[MUUNIT(bp->b_dev)] =
2414736Swnj 			(bp->b_repcnt<<8)|bp->b_command|MT_GO;
2424736Swnj 		return (MBU_STARTED);
2434736Swnj 	}
2447380Ssam 	if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) {
2454736Swnj 		if (mi->mi_tab.b_errcnt == 2) {
2464736Swnj 			mtaddr->mtca = MUUNIT(bp->b_dev);
2474736Swnj 		} else {
2484736Swnj 			mtaddr->mtbc = bp->b_bcount;
2494736Swnj 			mtaddr->mtca = (1<<2)|MUUNIT(bp->b_dev);
2504736Swnj 		}
2514736Swnj 		return (MBU_DODATA);
2524736Swnj 	}
2537380Ssam 	if (blkno < bdbtofsb(bp->b_blkno))
2544736Swnj 		mtaddr->mtncs[MUUNIT(bp->b_dev)] =
2557380Ssam 		  (min((unsigned)(bdbtofsb(bp->b_blkno) - blkno), 0377) << 8) |
2566186Ssam 			MT_SFORW|MT_GO;
2574736Swnj 	else
2584736Swnj 		mtaddr->mtncs[MUUNIT(bp->b_dev)] =
2597380Ssam 		  (min((unsigned)(blkno - bdbtofsb(bp->b_blkno)), 0377) << 8) |
2606186Ssam 			MT_SREV|MT_GO;
2614736Swnj 	return (MBU_STARTED);
2624736Swnj }
2634736Swnj 
2644736Swnj mtstart(mi)
2654736Swnj 	register struct mba_device *mi;
2664736Swnj {
2674736Swnj 	register struct buf *bp = mi->mi_tab.b_actf;
2684736Swnj 	register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)];
2694736Swnj 
2704736Swnj 	if (bp->b_flags & B_READ)
2714736Swnj 		if (mi->mi_tab.b_errcnt == 2)
2724736Swnj 			return(MT_READREV|MT_GO);
2734736Swnj 		else
2744736Swnj 			return(MT_READ|MT_GO);
2754736Swnj 	else
2764736Swnj 		return(MT_WRITE|sc->sc_dens|MT_GO);
2774736Swnj }
2784736Swnj 
2794736Swnj mtdtint(mi, mbsr)
2804736Swnj 	register struct mba_device *mi;
2814736Swnj 	int mbsr;
2824736Swnj {
2834736Swnj 	register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv;
2844736Swnj 	register struct buf *bp = mi->mi_tab.b_actf;
2854736Swnj 	register struct mu_softc *sc;
2864736Swnj 
2874736Swnj 	/* I'M NOT SURE IF THIS SHOULD ALWAYS BE THE CASE SO FOR NOW... */
2884736Swnj 	if ((mtaddr->mtca&3) != MUUNIT(bp->b_dev)) {
2894736Swnj 		printf("mt: wrong unit!\n");
2904736Swnj 		mtaddr->mtca = MUUNIT(bp->b_dev);
2914736Swnj 	}
2924736Swnj 	sc = &mu_softc[MUUNIT(bp->b_dev)];
2934736Swnj 	sc->sc_erreg = mtaddr->mter;
2944736Swnj 	if((bp->b_flags & B_READ) == 0)
2954736Swnj 		sc->sc_flags |= H_WRITTEN;
2964736Swnj 	switch (sc->sc_erreg & MTER_INTCODE) {
2974736Swnj 	case MTER_DONE:
2984736Swnj 	case MTER_LONGREC:
2994736Swnj 		if (mi->mi_tab.b_errcnt != 2)
3004736Swnj 			sc->sc_blkno++;
3014736Swnj 		bp->b_resid = 0;
3024736Swnj 		break;
3034736Swnj 
3044736Swnj 	case MTER_NOTCAP:
3054736Swnj 		printf("mu%d: blank tape\n", MUUNIT(bp->b_dev));
3064736Swnj 		goto err;
3074736Swnj 
3084736Swnj 	case MTER_TM:
3094736Swnj 	case MTER_EOT:
3104736Swnj 		sc->sc_blkno++;
3114736Swnj 	err:
3124736Swnj 		bp->b_resid = bp->b_bcount;
3137380Ssam 		sc->sc_nxrec = bdbtofsb(bp->b_blkno);
3144736Swnj 		break;
3154736Swnj 
3164736Swnj 	case MTER_SHRTREC:
3174736Swnj 		sc->sc_blkno++;
3184736Swnj 		if (bp != &rmtbuf[MTUNIT(bp->b_dev)])
3194736Swnj 			bp->b_flags |= B_ERROR;
3204736Swnj 		if (mi->mi_tab.b_errcnt == 2)
3214736Swnj 			bp->b_bcount = bp->b_resid;	/* restore saved value */
3224736Swnj 		bp->b_resid = bp->b_bcount - mtaddr->mtbc;
3234736Swnj 		break;
3244736Swnj 
3254736Swnj 	case MTER_RDOPP:
3264736Swnj 		mi->mi_tab.b_errcnt = 2;	/* indicate "read opposite" */
3274736Swnj 		bp->b_resid = bp->b_bcount;	/* save it */
3284736Swnj 		bp->b_bcount = mtaddr->mtbc;	/* use this instead */
3294736Swnj 		return(MBD_RETRY);
3304736Swnj 
3314736Swnj 	case MTER_RETRY:
3324736Swnj 		mi->mi_tab.b_errcnt = 1;	/* indicate simple retry */
3334736Swnj 		return(MBD_RETRY);
3344736Swnj 
3354736Swnj 	case MTER_OFFLINE:
3364736Swnj 		if (sc->sc_openf > 0) {
3374736Swnj 			sc->sc_openf = -1;
3384736Swnj 			printf("mu%d: offline\n", MUUNIT(bp->b_dev));
3394736Swnj 		}
3404736Swnj 		bp->b_flags |= B_ERROR;
3414736Swnj 		break;
3424736Swnj 
3434736Swnj 	case MTER_FPT:
3444736Swnj 		printf("mu%d: no write ring\n", MUUNIT(bp->b_dev));
3454736Swnj 		bp->b_flags |= B_ERROR;
3464736Swnj 		break;
3474736Swnj 
3484736Swnj 	default:
3494736Swnj 		printf("mu%d: hard error bn%d mbsr=%b er=%x ds=%b\n",
3504736Swnj 		    MUUNIT(bp->b_dev), bp->b_blkno,
3514736Swnj 		    mbsr, mbsr_bits, sc->sc_erreg,
3524736Swnj 		    sc->sc_dsreg, mtds_bits);
3534736Swnj 		bp->b_flags |= B_ERROR;
3544736Swnj 		mtaddr->mtid = MTID_CLR;		/* reset the TM78 */
3554736Swnj 		DELAY(250);
3564736Swnj 		while ((mtaddr->mtid & MTID_RDY) == 0)	/* wait for it */
3574736Swnj 			;
3584736Swnj 		return (MBD_DONE);
3594736Swnj 	}
3604736Swnj 	/* CHECK FOR MBA ERROR WHEN NO OTHER ERROR INDICATED? */
3614736Swnj 	return (MBD_DONE);
3624736Swnj }
3634736Swnj 
3644736Swnj mtndtint(mi)
3654736Swnj 	register struct mba_device *mi;
3664736Swnj {
3674736Swnj 	register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv;
3684736Swnj 	register struct buf *bp = mi->mi_tab.b_actf;
3694736Swnj 	register struct mu_softc *sc;
3704736Swnj 	int er, fc, unit;
3714736Swnj 
3724736Swnj 	unit = (mtaddr->mtner >> 8) & 3;
3734736Swnj 	er = MASKREG(mtaddr->mtner);
3744736Swnj 	/* WILL THIS OCCUR IF ANOTHER DRIVE COMES ONLINE? */
3754736Swnj 	if (bp == 0 || unit != MUUNIT(bp->b_dev)) {	/* consistency check */
3764736Swnj 		if ((er & MTER_INTCODE) != MTER_ONLINE)
3774736Swnj 			printf("mt: unit %d random interrupt\n", unit);
3784736Swnj 		return (MBN_SKIP);
3794736Swnj 	}
3804736Swnj 	if (bp == 0)
3814736Swnj 		return (MBN_SKIP);
3824736Swnj 	fc = (mtaddr->mtncs[unit] >> 8) & 0xff;
3834736Swnj 	sc = &mu_softc[unit];
3844736Swnj 	sc->sc_erreg = er;
3854736Swnj 	sc->sc_resid = fc;
3864736Swnj 	switch (er & MTER_INTCODE) {
3874736Swnj 	case MTER_DONE:
3884736Swnj 		if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) {
3894736Swnj 	done:
3904736Swnj 			if (bp->b_command == MT_SENSE)
3914736Swnj 				sc->sc_dsreg = MASKREG(mtaddr->mtds);
3924736Swnj 			bp->b_resid = fc;
3934736Swnj 			return (MBN_DONE);
3944736Swnj 		}
3954736Swnj 		/* this is UGLY!  (but is it correct?) */
3967380Ssam 		if ((fc = bdbtofsb(bp->b_blkno) - sc->sc_blkno) < 0)
3976186Ssam 			sc->sc_blkno -= MIN(0377, -fc);
3984736Swnj 		else
3996186Ssam 			sc->sc_blkno += MIN(0377, fc);
4004736Swnj 		return (MBN_RETRY);
4014736Swnj 
4024736Swnj 	case MTER_RWDING:
4034736Swnj 		return (MBN_SKIP);	/* ignore "rewind started" interrupt */
4044736Swnj 
4054736Swnj 	case MTER_NOTCAP:
4064736Swnj 		printf("mu%d: blank tape\n", MUUNIT(bp->b_dev));
4074736Swnj 
4084736Swnj 	case MTER_TM:
4094736Swnj 	case MTER_EOT:
4104736Swnj 	case MTER_LEOT:
4117380Ssam 		if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) {
4127380Ssam 			sc->sc_nxrec = bdbtofsb(bp->b_blkno) + fc;
4134736Swnj 			sc->sc_blkno = sc->sc_nxrec;
4144736Swnj 		} else {
4157380Ssam 			sc->sc_blkno = bdbtofsb(bp->b_blkno) - fc;
4164736Swnj 			sc->sc_nxrec = sc->sc_blkno - 1;
4174736Swnj 		}
4184736Swnj 		return (MBN_RETRY);
4194736Swnj 
4204736Swnj 	case MTER_FPT:
4214736Swnj 		printf("mu%d: no write ring\n", MUUNIT(bp->b_dev));
4224736Swnj 		bp->b_flags |= B_ERROR;
4234736Swnj 		return (MBN_DONE);
4244736Swnj 
4254736Swnj 	case MTER_OFFLINE:
4264736Swnj 		if (sc->sc_openf > 0) {
4274736Swnj 			sc->sc_openf = -1;
4284736Swnj 			printf("mu%d: offline\n", MUUNIT(bp->b_dev));
4294736Swnj 		}
4304736Swnj 		bp->b_flags |= B_ERROR;
4314736Swnj 		return (MBN_DONE);
4324736Swnj 
4334736Swnj 	case MTER_BOT:
4344736Swnj 		if (bp == &cmtbuf[MTUNIT(bp->b_dev)])
4354736Swnj 			goto done;
4364736Swnj 		/* FALL THROUGH */
4374736Swnj 
4384736Swnj 	default:
4394736Swnj 		printf("mu%d: hard error bn%d er=%o ds=%b\n",
4404736Swnj 		    MUUNIT(bp->b_dev), bp->b_blkno,
4414736Swnj 		    sc->sc_erreg, sc->sc_dsreg, mtds_bits);
4424736Swnj 		mtaddr->mtid = MTID_CLR;		/* reset the TM78 */
4434736Swnj 		DELAY(250);
4444736Swnj 		while ((mtaddr->mtid & MTID_RDY) == 0)	/* wait for it */
4454736Swnj 			;
4464736Swnj 		bp->b_flags |= B_ERROR;
4474736Swnj 		return (MBN_DONE);
4484736Swnj 	}
4494736Swnj 	/* NOTREACHED */
4504736Swnj }
4514736Swnj 
4527740Sroot mtread(dev, uio)
4534736Swnj 	dev_t dev;
4547740Sroot 	struct uio *uio;
4554736Swnj {
4568158Sroot 	int errno;
4574736Swnj 
4588158Sroot 	errno = mtphys(dev, uio);
4598158Sroot 	if (errno)
4608158Sroot 		return (errno);
4618158Sroot 	return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_READ, minphys, uio));
4624736Swnj }
4634736Swnj 
4647833Sroot mtwrite(dev, uio)
4657833Sroot 	dev_t dev;
4667833Sroot 	struct uio *uio;
4674736Swnj {
4688158Sroot 	int errno;
4694736Swnj 
4708158Sroot 	errno = mtphys(dev, uio);
4718158Sroot 	if (errno)
4728158Sroot 		return (errno);
4738158Sroot 	return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_WRITE, minphys, uio));
4744736Swnj }
4754736Swnj 
4767740Sroot mtphys(dev, uio)
4774736Swnj 	dev_t dev;
4787740Sroot 	struct uio *uio;
4794736Swnj {
4804736Swnj 	register int mtunit;
4814736Swnj 	register struct mu_softc *sc;
4824736Swnj 	register struct mba_device *mi;
4834736Swnj 	daddr_t a;
4844736Swnj 
4854736Swnj 	mtunit = MTUNIT(dev);
4867833Sroot 	if (mtunit >= NMT || (mi = mtinfo[mtunit]) == 0 || mi->mi_alive == 0)
4877740Sroot 		return (ENXIO);
4887833Sroot 	a = uio->uio_offset >> 9;
4894736Swnj 	sc = &mu_softc[MUUNIT(dev)];
4907380Ssam 	sc->sc_blkno = bdbtofsb(a);
4917380Ssam 	sc->sc_nxrec = bdbtofsb(a)+1;
4927740Sroot 	return (0);
4934736Swnj }
4944736Swnj 
4954736Swnj /*ARGSUSED*/
4967637Ssam mtioctl(dev, cmd, data, flag)
4974736Swnj 	dev_t dev;
4984736Swnj 	int cmd;
4997637Ssam 	caddr_t data;
5004736Swnj 	int flag;
5014736Swnj {
5024736Swnj 	register struct mu_softc *sc = &mu_softc[MUUNIT(dev)];
5034736Swnj 	register struct buf *bp = &cmtbuf[MTUNIT(dev)];
5044736Swnj 	register callcount;
5056186Ssam 	register int op;
5064736Swnj 	int fcount;
5077637Ssam 	struct mtop *mtop;
5087637Ssam 	struct mtget *mtget;
5094736Swnj 	/* we depend of the values and order of the MT codes here */
5104736Swnj 	static mtops[] =
5114736Swnj 	{MT_WTM,MT_SFORWF,MT_SREVF,MT_SFORW,MT_SREV,MT_REW,MT_UNLOAD,MT_SENSE};
5124736Swnj 
5134736Swnj 	switch (cmd) {
5147637Ssam 
5157637Ssam 	case MTIOCTOP:	/* tape operation */
5168606Sroot 		mtop = (struct mtop *)data;
5178606Sroot 		switch (mtop->mt_op) {
5187637Ssam 
5194736Swnj 		case MTWEOF:
5207637Ssam 			callcount = mtop->mt_count;
5214736Swnj 			fcount = 1;
5224736Swnj 			break;
5237637Ssam 
5244736Swnj 		case MTFSF: case MTBSF:
5257637Ssam 			callcount = mtop->mt_count;
5264736Swnj 			fcount = 1;
5274736Swnj 			break;
5287637Ssam 
5294736Swnj 		case MTFSR: case MTBSR:
5304736Swnj 			callcount = 1;
5317637Ssam 			fcount = mtop->mt_count;
5324736Swnj 			break;
5337637Ssam 
5344736Swnj 		case MTREW: case MTOFFL:
5354736Swnj 			callcount = 1;
5364736Swnj 			fcount = 1;
5374736Swnj 			break;
5387637Ssam 
5394736Swnj 		default:
5408581Sroot 			return (ENXIO);
5414736Swnj 		}
5428581Sroot 		if (callcount <= 0 || fcount <= 0)
5438581Sroot 			return (EINVAL);
5447637Ssam 		op = mtops[mtop->mt_op];
5454736Swnj 		if (op == MT_WTM)
5464736Swnj 			op |= sc->sc_dens;
5474736Swnj 		while (--callcount >= 0) {
5484736Swnj 			register int n;
5494736Swnj 
5504736Swnj 			do {
5516186Ssam 				n = MIN(fcount, 0xff);
5524736Swnj 				mtcommand(dev, op, n);
5534736Swnj 				fcount -= n;
5544736Swnj 			} while (fcount);
5557637Ssam 			if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) &&
5568581Sroot 			    bp->b_resid)
5578581Sroot 				return (EIO);
5584736Swnj 			if (bp->b_flags&B_ERROR)
5594736Swnj 				break;
5604736Swnj 		}
5618712Sroot 		return (geterror(bp));
5627637Ssam 
5634736Swnj 	case MTIOCGET:
5647637Ssam 		mtget = (struct mtget *)data;
5657637Ssam 		mtget->mt_erreg = sc->sc_erreg;
5667637Ssam 		mtget->mt_resid = sc->sc_resid;
5674736Swnj 		mtcommand(dev, MT_SENSE, 1);	/* update drive status */
5687637Ssam 		mtget->mt_dsreg = sc->sc_dsreg;
5697637Ssam 		mtget->mt_type = MT_ISMT;
5708581Sroot 		break;
5717637Ssam 
5724736Swnj 	default:
5738581Sroot 		return (ENXIO);
5744736Swnj 	}
5758581Sroot 	return (0);
5764736Swnj }
5774736Swnj 
5784736Swnj #define	DBSIZE	20
5794736Swnj 
5804736Swnj mtdump()
5814736Swnj {
5824736Swnj 	register struct mba_device *mi;
5834736Swnj 	register struct mba_regs *mp;
5844736Swnj 	int blk, num;
5854736Swnj 	int start;
5864736Swnj 
5874736Swnj 	start = 0;
5884736Swnj 	num = maxfree;
5894736Swnj #define	phys(a,b)		((b)((int)(a)&0x7fffffff))
5904736Swnj 	if (mtinfo[0] == 0)
5914736Swnj 		return (ENXIO);
5924736Swnj 	mi = phys(mtinfo[0], struct mba_device *);
5934736Swnj 	mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba;
5944736Swnj 	mp->mba_cr = MBCR_IE;
5956186Ssam #if lint
5968606Sroot 	blk = 0; num = blk; start = num; blk = start;
5976186Ssam 	return (0);
5986186Ssam #endif
5996186Ssam #ifdef notyet
6004736Swnj 	mtaddr = (struct mtdevice *)&mp->mba_drv[mi->mi_drive];
6014736Swnj 	mtaddr->mttc = MTTC_PDP11|MTTC_1600BPI;
6024736Swnj 	mtaddr->mtcs1 = MT_DCLR|MT_GO;
6034736Swnj 	while (num > 0) {
6044736Swnj 		blk = num > DBSIZE ? DBSIZE : num;
6054736Swnj 		mtdwrite(start, blk, mtaddr, mp);
6064736Swnj 		start += blk;
6074736Swnj 		num -= blk;
6084736Swnj 	}
6094736Swnj 	mteof(mtaddr);
6104736Swnj 	mteof(mtaddr);
6114736Swnj 	mtwait(mtaddr);
6124736Swnj 	if (mtaddr->mtds&MTDS_ERR)
6134736Swnj 		return (EIO);
6144736Swnj 	mtaddr->mtcs1 = MT_REW|MT_GO;
6154736Swnj 	return (0);
6164736Swnj }
6174736Swnj 
6184736Swnj mtdwrite(dbuf, num, mtaddr, mp)
6194736Swnj 	register dbuf, num;
6204736Swnj 	register struct mtdevice *mtaddr;
6214736Swnj 	struct mba_regs *mp;
6224736Swnj {
6234736Swnj 	register struct pte *io;
6244736Swnj 	register int i;
6254736Swnj 
6264736Swnj 	mtwait(mtaddr);
6274736Swnj 	io = mp->mba_map;
6284736Swnj 	for (i = 0; i < num; i++)
6294736Swnj 		*(int *)io++ = dbuf++ | PG_V;
6304736Swnj 	mtaddr->mtfc = -(num*NBPG);
6314736Swnj 	mp->mba_sr = -1;
6324736Swnj 	mp->mba_bcr = -(num*NBPG);
6334736Swnj 	mp->mba_var = 0;
6344736Swnj 	mtaddr->mtcs1 = MT_WCOM|MT_GO;
6354736Swnj }
6364736Swnj 
6374736Swnj mtwait(mtaddr)
6384736Swnj 	struct mtdevice *mtaddr;
6394736Swnj {
6404736Swnj 	register s;
6414736Swnj 
6424736Swnj 	do
6434736Swnj 		s = mtaddr->mtds;
6444736Swnj 	while ((s & MTDS_DRY) == 0);
6454736Swnj }
6464736Swnj 
6474736Swnj mteof(mtaddr)
6484736Swnj 	struct mtdevice *mtaddr;
6494736Swnj {
6504736Swnj 
6514736Swnj 	mtwait(mtaddr);
6524736Swnj 	mtaddr->mtcs1 = MT_WEOF|MT_GO;
6534736Swnj #endif notyet
6544736Swnj }
6554736Swnj #endif
656