1*8712Sroot /* mt.c 4.14 82/10/20 */ 24736Swnj 34736Swnj #include "mu.h" 44736Swnj #if NMT > 0 54736Swnj /* 64736Swnj * TM78/TU78 tape driver 74736Swnj * 84736Swnj * Behavior in complex error situations is uncertain... 94736Swnj * 104736Swnj * TODO: 114736Swnj * test error recovery 124736Swnj * add odd byte count kludge from VMS driver 134736Swnj * write dump routine 144736Swnj */ 154736Swnj #include "../h/param.h" 164736Swnj #include "../h/systm.h" 174736Swnj #include "../h/buf.h" 184736Swnj #include "../h/conf.h" 194736Swnj #include "../h/dir.h" 204736Swnj #include "../h/file.h" 214736Swnj #include "../h/user.h" 224736Swnj #include "../h/map.h" 234736Swnj #include "../h/pte.h" 247637Ssam #include "../h/ioctl.h" 254736Swnj #include "../h/mtio.h" 264736Swnj #include "../h/cmap.h" 277740Sroot #include "../h/uio.h" 284736Swnj 298471Sroot #include "../vax/cpu.h" 308471Sroot #include "../vaxmba/mbareg.h" 318471Sroot #include "../vaxmba/mbavar.h" 328471Sroot #include "../vaxmba/mtreg.h" 334736Swnj 344736Swnj struct buf rmtbuf[NMT]; 354736Swnj struct buf cmtbuf[NMT]; 364736Swnj 374736Swnj short mttypes[] = 384736Swnj { MBDT_TU78, 0 }; 394736Swnj struct mba_device *mtinfo[NMT]; 404736Swnj int mtattach(), mtslave(), mtustart(), mtstart(), mtndtint(), mtdtint(); 414736Swnj struct mba_driver mtdriver = 424736Swnj { mtattach, mtslave, mtustart, mtstart, mtdtint, mtndtint, 434736Swnj mttypes, "mt", "mu", mtinfo }; 444736Swnj 454736Swnj #define MASKREG(r) ((r) & 0xffff) 464736Swnj 474736Swnj /* bits in minor device */ 484736Swnj #define MUUNIT(dev) (minor(dev)&03) 494736Swnj #define H_NOREWIND 04 504736Swnj #define H_6250BPI 08 514736Swnj 524736Swnj #define MTUNIT(dev) (mutomt[MUUNIT(dev)]) 534736Swnj 544736Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 554736Swnj 564736Swnj struct mu_softc { 574736Swnj char sc_openf; 584736Swnj char sc_flags; 594736Swnj daddr_t sc_blkno; 604736Swnj daddr_t sc_nxrec; 614736Swnj u_short sc_erreg; 624736Swnj u_short sc_dsreg; 634736Swnj short sc_resid; 644736Swnj short sc_dens; 654736Swnj struct mba_device *sc_mi; 664736Swnj int sc_slave; 674736Swnj } mu_softc[NMU]; 684736Swnj short mutomt[NMU]; 694736Swnj 704736Swnj /* 714736Swnj * Bits for sc_flags. 724736Swnj */ 734736Swnj #define H_WRITTEN 1 /* last operation was a write */ 744736Swnj 754736Swnj char mtds_bits[] = MTDS_BITS; 764736Swnj 774736Swnj /*ARGSUSED*/ 784736Swnj mtattach(mi) 794736Swnj struct mba_device *mi; 804736Swnj { 818652Sroot 824736Swnj } 834736Swnj 847431Skre mtslave(mi, ms, sn) 854736Swnj struct mba_device *mi; 864736Swnj struct mba_slave *ms; 877431Skre int sn; 884736Swnj { 894736Swnj register struct mu_softc *sc = &mu_softc[ms->ms_unit]; 904736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 914736Swnj int s = spl7(), rtn = 0; 924736Swnj 934736Swnj mtaddr->mtas = -1; 947431Skre mtaddr->mtncs[sn] = MT_SENSE|MT_GO; 954736Swnj while (mtaddr->mtas == 0) 964736Swnj ; 974736Swnj if ((mtaddr->mtner & MTER_INTCODE) == MTER_DONE && 984736Swnj (mtaddr->mtds & MTDS_PRES)) { 994736Swnj sc->sc_mi = mi; 1007431Skre sc->sc_slave = sn; 1014736Swnj mutomt[ms->ms_unit] = mi->mi_unit; 1024736Swnj rtn = 1; 1034736Swnj } 1044736Swnj mtaddr->mtas = mtaddr->mtas; 1054736Swnj splx(s); 1064736Swnj return (rtn); 1074736Swnj } 1084736Swnj 1094736Swnj mtopen(dev, flag) 1104736Swnj dev_t dev; 1114736Swnj int flag; 1124736Swnj { 1134736Swnj register int muunit; 1144736Swnj register struct mba_device *mi; 1154736Swnj register struct mu_softc *sc; 1164736Swnj int olddens, dens; 1174736Swnj 1184736Swnj muunit = MUUNIT(dev); 1194736Swnj if (muunit >= NMU || (sc = &mu_softc[muunit])->sc_openf || 1208581Sroot (mi = mtinfo[MTUNIT(dev)]) == 0 || mi->mi_alive == 0) 1218581Sroot return (ENXIO); 1224736Swnj olddens = sc->sc_dens; 1234736Swnj dens = sc->sc_dens = (minor(dev)&H_6250BPI) ? MT_GCR : 0; 1244736Swnj mtcommand(dev, MT_SENSE, 1); 1254736Swnj sc->sc_dens = olddens; 1264736Swnj if ((sc->sc_dsreg & MTDS_ONL) == 0) { 1274736Swnj uprintf("mu%d: not online\n", muunit); 1288581Sroot return (EIO); 1294736Swnj } 1304736Swnj if ((flag&FWRITE) && (sc->sc_dsreg&MTDS_FPT)) { 1314736Swnj uprintf("mu%d: no write ring\n", muunit); 1328581Sroot return (EIO); 1334736Swnj } 1344736Swnj if ((sc->sc_dsreg & MTDS_BOT) == 0 && (flag&FWRITE) && 1354736Swnj dens != sc->sc_dens) { 1364736Swnj uprintf("mu%d: can't change density in mid-tape\n", muunit); 1378581Sroot return (EIO); 1384736Swnj } 1394736Swnj sc->sc_openf = 1; 1404736Swnj sc->sc_blkno = (daddr_t)0; 1414736Swnj sc->sc_nxrec = INF; 1424736Swnj sc->sc_flags = 0; 1434736Swnj sc->sc_dens = dens; 1448581Sroot return (0); 1454736Swnj } 1464736Swnj 1474736Swnj mtclose(dev, flag) 1484736Swnj register dev_t dev; 1494736Swnj register flag; 1504736Swnj { 1514736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 1524736Swnj 1534736Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) 1544736Swnj mtcommand(dev, MT_CLS|sc->sc_dens, 1); 1554736Swnj if ((minor(dev)&H_NOREWIND) == 0) 1564736Swnj mtcommand(dev, MT_REW, 0); 1574736Swnj sc->sc_openf = 0; 1584736Swnj } 1594736Swnj 1604736Swnj mtcommand(dev, com, count) 1614736Swnj dev_t dev; 1624736Swnj int com, count; 1634736Swnj { 1644736Swnj register struct buf *bp; 1655437Sroot register int s; 1664736Swnj 1674736Swnj bp = &cmtbuf[MTUNIT(dev)]; 1685437Sroot s = spl5(); 1694736Swnj while (bp->b_flags&B_BUSY) { 1704736Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1714736Swnj break; 1724736Swnj bp->b_flags |= B_WANTED; 1734736Swnj sleep((caddr_t)bp, PRIBIO); 1744736Swnj } 1754736Swnj bp->b_flags = B_BUSY|B_READ; 1765437Sroot splx(s); 1774736Swnj bp->b_dev = dev; 1784736Swnj bp->b_command = com; 1794736Swnj bp->b_repcnt = count; 1804736Swnj bp->b_blkno = 0; 1814736Swnj mtstrategy(bp); 1824736Swnj if (count == 0) 1834736Swnj return; 1844736Swnj iowait(bp); 1854736Swnj if (bp->b_flags&B_WANTED) 1864736Swnj wakeup((caddr_t)bp); 1874736Swnj bp->b_flags &= B_ERROR; 1884736Swnj } 1894736Swnj 1904736Swnj mtstrategy(bp) 1914736Swnj register struct buf *bp; 1924736Swnj { 1934736Swnj register struct mba_device *mi = mtinfo[MTUNIT(bp->b_dev)]; 1944736Swnj register struct buf *dp; 1955437Sroot register int s; 1964736Swnj 1974736Swnj bp->av_forw = NULL; 1984736Swnj dp = &mi->mi_tab; 1995437Sroot s = spl5(); 2004736Swnj if (dp->b_actf == NULL) 2014736Swnj dp->b_actf = bp; 2024736Swnj else 2034736Swnj dp->b_actl->av_forw = bp; 2044736Swnj dp->b_actl = bp; 2054736Swnj if (dp->b_active == 0) 2064736Swnj mbustart(mi); 2075437Sroot splx(s); 2084736Swnj } 2094736Swnj 2104736Swnj mtustart(mi) 2114736Swnj register struct mba_device *mi; 2124736Swnj { 2134736Swnj register struct mtdevice *mtaddr = 2144736Swnj (struct mtdevice *)mi->mi_drv; 2154736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2164736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2174736Swnj daddr_t blkno; 2184736Swnj 2194736Swnj sc->sc_flags &= ~H_WRITTEN; 2204736Swnj if (sc->sc_openf < 0) { 2214736Swnj bp->b_flags |= B_ERROR; 2224736Swnj return (MBU_NEXT); 2234736Swnj } 2244736Swnj if (bp != &cmtbuf[MTUNIT(bp->b_dev)]) { 2257380Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2264736Swnj bp->b_flags |= B_ERROR; 2274736Swnj bp->b_error = ENXIO; 2284736Swnj return (MBU_NEXT); 2294736Swnj } 2307380Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 2314736Swnj bp->b_flags&B_READ) { 2324736Swnj bp->b_resid = bp->b_bcount; 2334736Swnj clrbuf(bp); 2344736Swnj return (MBU_NEXT); 2354736Swnj } 2364736Swnj if ((bp->b_flags&B_READ)==0) 2377380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 2384736Swnj } else { 2394736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2404736Swnj (bp->b_repcnt<<8)|bp->b_command|MT_GO; 2414736Swnj return (MBU_STARTED); 2424736Swnj } 2437380Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 2444736Swnj if (mi->mi_tab.b_errcnt == 2) { 2454736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2464736Swnj } else { 2474736Swnj mtaddr->mtbc = bp->b_bcount; 2484736Swnj mtaddr->mtca = (1<<2)|MUUNIT(bp->b_dev); 2494736Swnj } 2504736Swnj return (MBU_DODATA); 2514736Swnj } 2527380Ssam if (blkno < bdbtofsb(bp->b_blkno)) 2534736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2547380Ssam (min((unsigned)(bdbtofsb(bp->b_blkno) - blkno), 0377) << 8) | 2556186Ssam MT_SFORW|MT_GO; 2564736Swnj else 2574736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2587380Ssam (min((unsigned)(blkno - bdbtofsb(bp->b_blkno)), 0377) << 8) | 2596186Ssam MT_SREV|MT_GO; 2604736Swnj return (MBU_STARTED); 2614736Swnj } 2624736Swnj 2634736Swnj mtstart(mi) 2644736Swnj register struct mba_device *mi; 2654736Swnj { 2664736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2674736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2684736Swnj 2694736Swnj if (bp->b_flags & B_READ) 2704736Swnj if (mi->mi_tab.b_errcnt == 2) 2714736Swnj return(MT_READREV|MT_GO); 2724736Swnj else 2734736Swnj return(MT_READ|MT_GO); 2744736Swnj else 2754736Swnj return(MT_WRITE|sc->sc_dens|MT_GO); 2764736Swnj } 2774736Swnj 2784736Swnj mtdtint(mi, mbsr) 2794736Swnj register struct mba_device *mi; 2804736Swnj int mbsr; 2814736Swnj { 2824736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 2834736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2844736Swnj register struct mu_softc *sc; 2854736Swnj 2864736Swnj /* I'M NOT SURE IF THIS SHOULD ALWAYS BE THE CASE SO FOR NOW... */ 2874736Swnj if ((mtaddr->mtca&3) != MUUNIT(bp->b_dev)) { 2884736Swnj printf("mt: wrong unit!\n"); 2894736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2904736Swnj } 2914736Swnj sc = &mu_softc[MUUNIT(bp->b_dev)]; 2924736Swnj sc->sc_erreg = mtaddr->mter; 2934736Swnj if((bp->b_flags & B_READ) == 0) 2944736Swnj sc->sc_flags |= H_WRITTEN; 2954736Swnj switch (sc->sc_erreg & MTER_INTCODE) { 2964736Swnj case MTER_DONE: 2974736Swnj case MTER_LONGREC: 2984736Swnj if (mi->mi_tab.b_errcnt != 2) 2994736Swnj sc->sc_blkno++; 3004736Swnj bp->b_resid = 0; 3014736Swnj break; 3024736Swnj 3034736Swnj case MTER_NOTCAP: 3044736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 3054736Swnj goto err; 3064736Swnj 3074736Swnj case MTER_TM: 3084736Swnj case MTER_EOT: 3094736Swnj sc->sc_blkno++; 3104736Swnj err: 3114736Swnj bp->b_resid = bp->b_bcount; 3127380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 3134736Swnj break; 3144736Swnj 3154736Swnj case MTER_SHRTREC: 3164736Swnj sc->sc_blkno++; 3174736Swnj if (bp != &rmtbuf[MTUNIT(bp->b_dev)]) 3184736Swnj bp->b_flags |= B_ERROR; 3194736Swnj if (mi->mi_tab.b_errcnt == 2) 3204736Swnj bp->b_bcount = bp->b_resid; /* restore saved value */ 3214736Swnj bp->b_resid = bp->b_bcount - mtaddr->mtbc; 3224736Swnj break; 3234736Swnj 3244736Swnj case MTER_RDOPP: 3254736Swnj mi->mi_tab.b_errcnt = 2; /* indicate "read opposite" */ 3264736Swnj bp->b_resid = bp->b_bcount; /* save it */ 3274736Swnj bp->b_bcount = mtaddr->mtbc; /* use this instead */ 3284736Swnj return(MBD_RETRY); 3294736Swnj 3304736Swnj case MTER_RETRY: 3314736Swnj mi->mi_tab.b_errcnt = 1; /* indicate simple retry */ 3324736Swnj return(MBD_RETRY); 3334736Swnj 3344736Swnj case MTER_OFFLINE: 3354736Swnj if (sc->sc_openf > 0) { 3364736Swnj sc->sc_openf = -1; 3374736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 3384736Swnj } 3394736Swnj bp->b_flags |= B_ERROR; 3404736Swnj break; 3414736Swnj 3424736Swnj case MTER_FPT: 3434736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 3444736Swnj bp->b_flags |= B_ERROR; 3454736Swnj break; 3464736Swnj 3474736Swnj default: 3484736Swnj printf("mu%d: hard error bn%d mbsr=%b er=%x ds=%b\n", 3494736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 3504736Swnj mbsr, mbsr_bits, sc->sc_erreg, 3514736Swnj sc->sc_dsreg, mtds_bits); 3524736Swnj bp->b_flags |= B_ERROR; 3534736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 3544736Swnj DELAY(250); 3554736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 3564736Swnj ; 3574736Swnj return (MBD_DONE); 3584736Swnj } 3594736Swnj /* CHECK FOR MBA ERROR WHEN NO OTHER ERROR INDICATED? */ 3604736Swnj return (MBD_DONE); 3614736Swnj } 3624736Swnj 3634736Swnj mtndtint(mi) 3644736Swnj register struct mba_device *mi; 3654736Swnj { 3664736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 3674736Swnj register struct buf *bp = mi->mi_tab.b_actf; 3684736Swnj register struct mu_softc *sc; 3694736Swnj int er, fc, unit; 3704736Swnj 3714736Swnj unit = (mtaddr->mtner >> 8) & 3; 3724736Swnj er = MASKREG(mtaddr->mtner); 3734736Swnj /* WILL THIS OCCUR IF ANOTHER DRIVE COMES ONLINE? */ 3744736Swnj if (bp == 0 || unit != MUUNIT(bp->b_dev)) { /* consistency check */ 3754736Swnj if ((er & MTER_INTCODE) != MTER_ONLINE) 3764736Swnj printf("mt: unit %d random interrupt\n", unit); 3774736Swnj return (MBN_SKIP); 3784736Swnj } 3794736Swnj if (bp == 0) 3804736Swnj return (MBN_SKIP); 3814736Swnj fc = (mtaddr->mtncs[unit] >> 8) & 0xff; 3824736Swnj sc = &mu_softc[unit]; 3834736Swnj sc->sc_erreg = er; 3844736Swnj sc->sc_resid = fc; 3854736Swnj switch (er & MTER_INTCODE) { 3864736Swnj case MTER_DONE: 3874736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) { 3884736Swnj done: 3894736Swnj if (bp->b_command == MT_SENSE) 3904736Swnj sc->sc_dsreg = MASKREG(mtaddr->mtds); 3914736Swnj bp->b_resid = fc; 3924736Swnj return (MBN_DONE); 3934736Swnj } 3944736Swnj /* this is UGLY! (but is it correct?) */ 3957380Ssam if ((fc = bdbtofsb(bp->b_blkno) - sc->sc_blkno) < 0) 3966186Ssam sc->sc_blkno -= MIN(0377, -fc); 3974736Swnj else 3986186Ssam sc->sc_blkno += MIN(0377, fc); 3994736Swnj return (MBN_RETRY); 4004736Swnj 4014736Swnj case MTER_RWDING: 4024736Swnj return (MBN_SKIP); /* ignore "rewind started" interrupt */ 4034736Swnj 4044736Swnj case MTER_NOTCAP: 4054736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 4064736Swnj 4074736Swnj case MTER_TM: 4084736Swnj case MTER_EOT: 4094736Swnj case MTER_LEOT: 4107380Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4117380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + fc; 4124736Swnj sc->sc_blkno = sc->sc_nxrec; 4134736Swnj } else { 4147380Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno) - fc; 4154736Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4164736Swnj } 4174736Swnj return (MBN_RETRY); 4184736Swnj 4194736Swnj case MTER_FPT: 4204736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 4214736Swnj bp->b_flags |= B_ERROR; 4224736Swnj return (MBN_DONE); 4234736Swnj 4244736Swnj case MTER_OFFLINE: 4254736Swnj if (sc->sc_openf > 0) { 4264736Swnj sc->sc_openf = -1; 4274736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 4284736Swnj } 4294736Swnj bp->b_flags |= B_ERROR; 4304736Swnj return (MBN_DONE); 4314736Swnj 4324736Swnj case MTER_BOT: 4334736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) 4344736Swnj goto done; 4354736Swnj /* FALL THROUGH */ 4364736Swnj 4374736Swnj default: 4384736Swnj printf("mu%d: hard error bn%d er=%o ds=%b\n", 4394736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 4404736Swnj sc->sc_erreg, sc->sc_dsreg, mtds_bits); 4414736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 4424736Swnj DELAY(250); 4434736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 4444736Swnj ; 4454736Swnj bp->b_flags |= B_ERROR; 4464736Swnj return (MBN_DONE); 4474736Swnj } 4484736Swnj /* NOTREACHED */ 4494736Swnj } 4504736Swnj 4517740Sroot mtread(dev, uio) 4524736Swnj dev_t dev; 4537740Sroot struct uio *uio; 4544736Swnj { 4558158Sroot int errno; 4564736Swnj 4578158Sroot errno = mtphys(dev, uio); 4588158Sroot if (errno) 4598158Sroot return (errno); 4608158Sroot return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_READ, minphys, uio)); 4614736Swnj } 4624736Swnj 4637833Sroot mtwrite(dev, uio) 4647833Sroot dev_t dev; 4657833Sroot struct uio *uio; 4664736Swnj { 4678158Sroot int errno; 4684736Swnj 4698158Sroot errno = mtphys(dev, uio); 4708158Sroot if (errno) 4718158Sroot return (errno); 4728158Sroot return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_WRITE, minphys, uio)); 4734736Swnj } 4744736Swnj 4757740Sroot mtphys(dev, uio) 4764736Swnj dev_t dev; 4777740Sroot struct uio *uio; 4784736Swnj { 4794736Swnj register int mtunit; 4804736Swnj register struct mu_softc *sc; 4814736Swnj register struct mba_device *mi; 4824736Swnj daddr_t a; 4834736Swnj 4844736Swnj mtunit = MTUNIT(dev); 4857833Sroot if (mtunit >= NMT || (mi = mtinfo[mtunit]) == 0 || mi->mi_alive == 0) 4867740Sroot return (ENXIO); 4877833Sroot a = uio->uio_offset >> 9; 4884736Swnj sc = &mu_softc[MUUNIT(dev)]; 4897380Ssam sc->sc_blkno = bdbtofsb(a); 4907380Ssam sc->sc_nxrec = bdbtofsb(a)+1; 4917740Sroot return (0); 4924736Swnj } 4934736Swnj 4944736Swnj /*ARGSUSED*/ 4957637Ssam mtioctl(dev, cmd, data, flag) 4964736Swnj dev_t dev; 4974736Swnj int cmd; 4987637Ssam caddr_t data; 4994736Swnj int flag; 5004736Swnj { 5014736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 5024736Swnj register struct buf *bp = &cmtbuf[MTUNIT(dev)]; 5034736Swnj register callcount; 5046186Ssam register int op; 5054736Swnj int fcount; 5067637Ssam struct mtop *mtop; 5077637Ssam struct mtget *mtget; 5084736Swnj /* we depend of the values and order of the MT codes here */ 5094736Swnj static mtops[] = 5104736Swnj {MT_WTM,MT_SFORWF,MT_SREVF,MT_SFORW,MT_SREV,MT_REW,MT_UNLOAD,MT_SENSE}; 5114736Swnj 5124736Swnj switch (cmd) { 5137637Ssam 5147637Ssam case MTIOCTOP: /* tape operation */ 5158606Sroot mtop = (struct mtop *)data; 5168606Sroot switch (mtop->mt_op) { 5177637Ssam 5184736Swnj case MTWEOF: 5197637Ssam callcount = mtop->mt_count; 5204736Swnj fcount = 1; 5214736Swnj break; 5227637Ssam 5234736Swnj case MTFSF: case MTBSF: 5247637Ssam callcount = mtop->mt_count; 5254736Swnj fcount = 1; 5264736Swnj break; 5277637Ssam 5284736Swnj case MTFSR: case MTBSR: 5294736Swnj callcount = 1; 5307637Ssam fcount = mtop->mt_count; 5314736Swnj break; 5327637Ssam 5334736Swnj case MTREW: case MTOFFL: 5344736Swnj callcount = 1; 5354736Swnj fcount = 1; 5364736Swnj break; 5377637Ssam 5384736Swnj default: 5398581Sroot return (ENXIO); 5404736Swnj } 5418581Sroot if (callcount <= 0 || fcount <= 0) 5428581Sroot return (EINVAL); 5437637Ssam op = mtops[mtop->mt_op]; 5444736Swnj if (op == MT_WTM) 5454736Swnj op |= sc->sc_dens; 5464736Swnj while (--callcount >= 0) { 5474736Swnj register int n; 5484736Swnj 5494736Swnj do { 5506186Ssam n = MIN(fcount, 0xff); 5514736Swnj mtcommand(dev, op, n); 5524736Swnj fcount -= n; 5534736Swnj } while (fcount); 5547637Ssam if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) && 5558581Sroot bp->b_resid) 5568581Sroot return (EIO); 5574736Swnj if (bp->b_flags&B_ERROR) 5584736Swnj break; 5594736Swnj } 560*8712Sroot return (geterror(bp)); 5617637Ssam 5624736Swnj case MTIOCGET: 5637637Ssam mtget = (struct mtget *)data; 5647637Ssam mtget->mt_erreg = sc->sc_erreg; 5657637Ssam mtget->mt_resid = sc->sc_resid; 5664736Swnj mtcommand(dev, MT_SENSE, 1); /* update drive status */ 5677637Ssam mtget->mt_dsreg = sc->sc_dsreg; 5687637Ssam mtget->mt_type = MT_ISMT; 5698581Sroot break; 5707637Ssam 5714736Swnj default: 5728581Sroot return (ENXIO); 5734736Swnj } 5748581Sroot return (0); 5754736Swnj } 5764736Swnj 5774736Swnj #define DBSIZE 20 5784736Swnj 5794736Swnj mtdump() 5804736Swnj { 5814736Swnj register struct mba_device *mi; 5824736Swnj register struct mba_regs *mp; 5834736Swnj int blk, num; 5844736Swnj int start; 5854736Swnj 5864736Swnj start = 0; 5874736Swnj num = maxfree; 5884736Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5894736Swnj if (mtinfo[0] == 0) 5904736Swnj return (ENXIO); 5914736Swnj mi = phys(mtinfo[0], struct mba_device *); 5924736Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5934736Swnj mp->mba_cr = MBCR_IE; 5946186Ssam #if lint 5958606Sroot blk = 0; num = blk; start = num; blk = start; 5966186Ssam return (0); 5976186Ssam #endif 5986186Ssam #ifdef notyet 5994736Swnj mtaddr = (struct mtdevice *)&mp->mba_drv[mi->mi_drive]; 6004736Swnj mtaddr->mttc = MTTC_PDP11|MTTC_1600BPI; 6014736Swnj mtaddr->mtcs1 = MT_DCLR|MT_GO; 6024736Swnj while (num > 0) { 6034736Swnj blk = num > DBSIZE ? DBSIZE : num; 6044736Swnj mtdwrite(start, blk, mtaddr, mp); 6054736Swnj start += blk; 6064736Swnj num -= blk; 6074736Swnj } 6084736Swnj mteof(mtaddr); 6094736Swnj mteof(mtaddr); 6104736Swnj mtwait(mtaddr); 6114736Swnj if (mtaddr->mtds&MTDS_ERR) 6124736Swnj return (EIO); 6134736Swnj mtaddr->mtcs1 = MT_REW|MT_GO; 6144736Swnj return (0); 6154736Swnj } 6164736Swnj 6174736Swnj mtdwrite(dbuf, num, mtaddr, mp) 6184736Swnj register dbuf, num; 6194736Swnj register struct mtdevice *mtaddr; 6204736Swnj struct mba_regs *mp; 6214736Swnj { 6224736Swnj register struct pte *io; 6234736Swnj register int i; 6244736Swnj 6254736Swnj mtwait(mtaddr); 6264736Swnj io = mp->mba_map; 6274736Swnj for (i = 0; i < num; i++) 6284736Swnj *(int *)io++ = dbuf++ | PG_V; 6294736Swnj mtaddr->mtfc = -(num*NBPG); 6304736Swnj mp->mba_sr = -1; 6314736Swnj mp->mba_bcr = -(num*NBPG); 6324736Swnj mp->mba_var = 0; 6334736Swnj mtaddr->mtcs1 = MT_WCOM|MT_GO; 6344736Swnj } 6354736Swnj 6364736Swnj mtwait(mtaddr) 6374736Swnj struct mtdevice *mtaddr; 6384736Swnj { 6394736Swnj register s; 6404736Swnj 6414736Swnj do 6424736Swnj s = mtaddr->mtds; 6434736Swnj while ((s & MTDS_DRY) == 0); 6444736Swnj } 6454736Swnj 6464736Swnj mteof(mtaddr) 6474736Swnj struct mtdevice *mtaddr; 6484736Swnj { 6494736Swnj 6504736Swnj mtwait(mtaddr); 6514736Swnj mtaddr->mtcs1 = MT_WEOF|MT_GO; 6524736Swnj #endif notyet 6534736Swnj } 6544736Swnj #endif 655