1*8581Sroot /* mt.c 4.11 82/10/17 */ 24736Swnj 34736Swnj #include "mu.h" 44736Swnj #if NMT > 0 54736Swnj /* 64736Swnj * TM78/TU78 tape driver 74736Swnj * 84736Swnj * Behavior in complex error situations is uncertain... 94736Swnj * 104736Swnj * TODO: 114736Swnj * test error recovery 124736Swnj * add odd byte count kludge from VMS driver 134736Swnj * write dump routine 144736Swnj */ 154736Swnj #include "../h/param.h" 164736Swnj #include "../h/systm.h" 174736Swnj #include "../h/buf.h" 184736Swnj #include "../h/conf.h" 194736Swnj #include "../h/dir.h" 204736Swnj #include "../h/file.h" 214736Swnj #include "../h/user.h" 224736Swnj #include "../h/map.h" 234736Swnj #include "../h/pte.h" 247637Ssam #include "../h/ioctl.h" 254736Swnj #include "../h/mtio.h" 264736Swnj #include "../h/cmap.h" 277740Sroot #include "../h/uio.h" 284736Swnj 298471Sroot #include "../vax/cpu.h" 308471Sroot #include "../vaxmba/mbareg.h" 318471Sroot #include "../vaxmba/mbavar.h" 328471Sroot #include "../vaxmba/mtreg.h" 334736Swnj 344736Swnj struct buf rmtbuf[NMT]; 354736Swnj struct buf cmtbuf[NMT]; 364736Swnj 374736Swnj short mttypes[] = 384736Swnj { MBDT_TU78, 0 }; 394736Swnj struct mba_device *mtinfo[NMT]; 404736Swnj int mtattach(), mtslave(), mtustart(), mtstart(), mtndtint(), mtdtint(); 414736Swnj struct mba_driver mtdriver = 424736Swnj { mtattach, mtslave, mtustart, mtstart, mtdtint, mtndtint, 434736Swnj mttypes, "mt", "mu", mtinfo }; 444736Swnj 454736Swnj #define MASKREG(r) ((r) & 0xffff) 464736Swnj 474736Swnj /* bits in minor device */ 484736Swnj #define MUUNIT(dev) (minor(dev)&03) 494736Swnj #define H_NOREWIND 04 504736Swnj #define H_6250BPI 08 514736Swnj 524736Swnj #define MTUNIT(dev) (mutomt[MUUNIT(dev)]) 534736Swnj 544736Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 554736Swnj 564736Swnj struct mu_softc { 574736Swnj char sc_openf; 584736Swnj char sc_flags; 594736Swnj daddr_t sc_blkno; 604736Swnj daddr_t sc_nxrec; 614736Swnj u_short sc_erreg; 624736Swnj u_short sc_dsreg; 634736Swnj short sc_resid; 644736Swnj short sc_dens; 654736Swnj struct mba_device *sc_mi; 664736Swnj int sc_slave; 674736Swnj } mu_softc[NMU]; 684736Swnj short mutomt[NMU]; 694736Swnj 704736Swnj /* 714736Swnj * Bits for sc_flags. 724736Swnj */ 734736Swnj #define H_WRITTEN 1 /* last operation was a write */ 744736Swnj 754736Swnj char mtds_bits[] = MTDS_BITS; 764736Swnj 774736Swnj /*ARGSUSED*/ 784736Swnj mtattach(mi) 794736Swnj struct mba_device *mi; 804736Swnj { 816186Ssam #ifdef lint 827740Sroot mtread(0, 0); mtwrite(0); mtioctl(0, 0, 0, 0); 836186Ssam #endif 844736Swnj } 854736Swnj 867431Skre mtslave(mi, ms, sn) 874736Swnj struct mba_device *mi; 884736Swnj struct mba_slave *ms; 897431Skre int sn; 904736Swnj { 914736Swnj register struct mu_softc *sc = &mu_softc[ms->ms_unit]; 924736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 934736Swnj int s = spl7(), rtn = 0; 944736Swnj 954736Swnj mtaddr->mtas = -1; 967431Skre mtaddr->mtncs[sn] = MT_SENSE|MT_GO; 974736Swnj while (mtaddr->mtas == 0) 984736Swnj ; 994736Swnj if ((mtaddr->mtner & MTER_INTCODE) == MTER_DONE && 1004736Swnj (mtaddr->mtds & MTDS_PRES)) { 1014736Swnj sc->sc_mi = mi; 1027431Skre sc->sc_slave = sn; 1034736Swnj mutomt[ms->ms_unit] = mi->mi_unit; 1044736Swnj rtn = 1; 1054736Swnj } 1064736Swnj mtaddr->mtas = mtaddr->mtas; 1074736Swnj splx(s); 1084736Swnj return (rtn); 1094736Swnj } 1104736Swnj 1114736Swnj mtopen(dev, flag) 1124736Swnj dev_t dev; 1134736Swnj int flag; 1144736Swnj { 1154736Swnj register int muunit; 1164736Swnj register struct mba_device *mi; 1174736Swnj register struct mu_softc *sc; 1184736Swnj int olddens, dens; 1194736Swnj 1204736Swnj muunit = MUUNIT(dev); 1214736Swnj if (muunit >= NMU || (sc = &mu_softc[muunit])->sc_openf || 122*8581Sroot (mi = mtinfo[MTUNIT(dev)]) == 0 || mi->mi_alive == 0) 123*8581Sroot return (ENXIO); 1244736Swnj olddens = sc->sc_dens; 1254736Swnj dens = sc->sc_dens = (minor(dev)&H_6250BPI) ? MT_GCR : 0; 1264736Swnj mtcommand(dev, MT_SENSE, 1); 1274736Swnj sc->sc_dens = olddens; 1284736Swnj if ((sc->sc_dsreg & MTDS_ONL) == 0) { 1294736Swnj uprintf("mu%d: not online\n", muunit); 130*8581Sroot return (EIO); 1314736Swnj } 1324736Swnj if ((flag&FWRITE) && (sc->sc_dsreg&MTDS_FPT)) { 1334736Swnj uprintf("mu%d: no write ring\n", muunit); 134*8581Sroot return (EIO); 1354736Swnj } 1364736Swnj if ((sc->sc_dsreg & MTDS_BOT) == 0 && (flag&FWRITE) && 1374736Swnj dens != sc->sc_dens) { 1384736Swnj uprintf("mu%d: can't change density in mid-tape\n", muunit); 139*8581Sroot return (EIO); 1404736Swnj } 1414736Swnj sc->sc_openf = 1; 1424736Swnj sc->sc_blkno = (daddr_t)0; 1434736Swnj sc->sc_nxrec = INF; 1444736Swnj sc->sc_flags = 0; 1454736Swnj sc->sc_dens = dens; 146*8581Sroot return (0); 1474736Swnj } 1484736Swnj 1494736Swnj mtclose(dev, flag) 1504736Swnj register dev_t dev; 1514736Swnj register flag; 1524736Swnj { 1534736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 1544736Swnj 1554736Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) 1564736Swnj mtcommand(dev, MT_CLS|sc->sc_dens, 1); 1574736Swnj if ((minor(dev)&H_NOREWIND) == 0) 1584736Swnj mtcommand(dev, MT_REW, 0); 1594736Swnj sc->sc_openf = 0; 1604736Swnj } 1614736Swnj 1624736Swnj mtcommand(dev, com, count) 1634736Swnj dev_t dev; 1644736Swnj int com, count; 1654736Swnj { 1664736Swnj register struct buf *bp; 1675437Sroot register int s; 1684736Swnj 1694736Swnj bp = &cmtbuf[MTUNIT(dev)]; 1705437Sroot s = spl5(); 1714736Swnj while (bp->b_flags&B_BUSY) { 1724736Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1734736Swnj break; 1744736Swnj bp->b_flags |= B_WANTED; 1754736Swnj sleep((caddr_t)bp, PRIBIO); 1764736Swnj } 1774736Swnj bp->b_flags = B_BUSY|B_READ; 1785437Sroot splx(s); 1794736Swnj bp->b_dev = dev; 1804736Swnj bp->b_command = com; 1814736Swnj bp->b_repcnt = count; 1824736Swnj bp->b_blkno = 0; 1834736Swnj mtstrategy(bp); 1844736Swnj if (count == 0) 1854736Swnj return; 1864736Swnj iowait(bp); 1874736Swnj if (bp->b_flags&B_WANTED) 1884736Swnj wakeup((caddr_t)bp); 1894736Swnj bp->b_flags &= B_ERROR; 1904736Swnj } 1914736Swnj 1924736Swnj mtstrategy(bp) 1934736Swnj register struct buf *bp; 1944736Swnj { 1954736Swnj register struct mba_device *mi = mtinfo[MTUNIT(bp->b_dev)]; 1964736Swnj register struct buf *dp; 1975437Sroot register int s; 1984736Swnj 1994736Swnj bp->av_forw = NULL; 2004736Swnj dp = &mi->mi_tab; 2015437Sroot s = spl5(); 2024736Swnj if (dp->b_actf == NULL) 2034736Swnj dp->b_actf = bp; 2044736Swnj else 2054736Swnj dp->b_actl->av_forw = bp; 2064736Swnj dp->b_actl = bp; 2074736Swnj if (dp->b_active == 0) 2084736Swnj mbustart(mi); 2095437Sroot splx(s); 2104736Swnj } 2114736Swnj 2124736Swnj mtustart(mi) 2134736Swnj register struct mba_device *mi; 2144736Swnj { 2154736Swnj register struct mtdevice *mtaddr = 2164736Swnj (struct mtdevice *)mi->mi_drv; 2174736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2184736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2194736Swnj daddr_t blkno; 2204736Swnj 2214736Swnj sc->sc_flags &= ~H_WRITTEN; 2224736Swnj if (sc->sc_openf < 0) { 2234736Swnj bp->b_flags |= B_ERROR; 2244736Swnj return (MBU_NEXT); 2254736Swnj } 2264736Swnj if (bp != &cmtbuf[MTUNIT(bp->b_dev)]) { 2277380Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2284736Swnj bp->b_flags |= B_ERROR; 2294736Swnj bp->b_error = ENXIO; 2304736Swnj return (MBU_NEXT); 2314736Swnj } 2327380Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 2334736Swnj bp->b_flags&B_READ) { 2344736Swnj bp->b_resid = bp->b_bcount; 2354736Swnj clrbuf(bp); 2364736Swnj return (MBU_NEXT); 2374736Swnj } 2384736Swnj if ((bp->b_flags&B_READ)==0) 2397380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 2404736Swnj } else { 2414736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2424736Swnj (bp->b_repcnt<<8)|bp->b_command|MT_GO; 2434736Swnj return (MBU_STARTED); 2444736Swnj } 2457380Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 2464736Swnj if (mi->mi_tab.b_errcnt == 2) { 2474736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2484736Swnj } else { 2494736Swnj mtaddr->mtbc = bp->b_bcount; 2504736Swnj mtaddr->mtca = (1<<2)|MUUNIT(bp->b_dev); 2514736Swnj } 2524736Swnj return (MBU_DODATA); 2534736Swnj } 2547380Ssam if (blkno < bdbtofsb(bp->b_blkno)) 2554736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2567380Ssam (min((unsigned)(bdbtofsb(bp->b_blkno) - blkno), 0377) << 8) | 2576186Ssam MT_SFORW|MT_GO; 2584736Swnj else 2594736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2607380Ssam (min((unsigned)(blkno - bdbtofsb(bp->b_blkno)), 0377) << 8) | 2616186Ssam MT_SREV|MT_GO; 2624736Swnj return (MBU_STARTED); 2634736Swnj } 2644736Swnj 2654736Swnj mtstart(mi) 2664736Swnj register struct mba_device *mi; 2674736Swnj { 2684736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2694736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2704736Swnj 2714736Swnj if (bp->b_flags & B_READ) 2724736Swnj if (mi->mi_tab.b_errcnt == 2) 2734736Swnj return(MT_READREV|MT_GO); 2744736Swnj else 2754736Swnj return(MT_READ|MT_GO); 2764736Swnj else 2774736Swnj return(MT_WRITE|sc->sc_dens|MT_GO); 2784736Swnj } 2794736Swnj 2804736Swnj mtdtint(mi, mbsr) 2814736Swnj register struct mba_device *mi; 2824736Swnj int mbsr; 2834736Swnj { 2844736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 2854736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2864736Swnj register struct mu_softc *sc; 2874736Swnj 2884736Swnj /* I'M NOT SURE IF THIS SHOULD ALWAYS BE THE CASE SO FOR NOW... */ 2894736Swnj if ((mtaddr->mtca&3) != MUUNIT(bp->b_dev)) { 2904736Swnj printf("mt: wrong unit!\n"); 2914736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2924736Swnj } 2934736Swnj sc = &mu_softc[MUUNIT(bp->b_dev)]; 2944736Swnj sc->sc_erreg = mtaddr->mter; 2954736Swnj if((bp->b_flags & B_READ) == 0) 2964736Swnj sc->sc_flags |= H_WRITTEN; 2974736Swnj switch (sc->sc_erreg & MTER_INTCODE) { 2984736Swnj case MTER_DONE: 2994736Swnj case MTER_LONGREC: 3004736Swnj if (mi->mi_tab.b_errcnt != 2) 3014736Swnj sc->sc_blkno++; 3024736Swnj bp->b_resid = 0; 3034736Swnj break; 3044736Swnj 3054736Swnj case MTER_NOTCAP: 3064736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 3074736Swnj goto err; 3084736Swnj 3094736Swnj case MTER_TM: 3104736Swnj case MTER_EOT: 3114736Swnj sc->sc_blkno++; 3124736Swnj err: 3134736Swnj bp->b_resid = bp->b_bcount; 3147380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 3154736Swnj break; 3164736Swnj 3174736Swnj case MTER_SHRTREC: 3184736Swnj sc->sc_blkno++; 3194736Swnj if (bp != &rmtbuf[MTUNIT(bp->b_dev)]) 3204736Swnj bp->b_flags |= B_ERROR; 3214736Swnj if (mi->mi_tab.b_errcnt == 2) 3224736Swnj bp->b_bcount = bp->b_resid; /* restore saved value */ 3234736Swnj bp->b_resid = bp->b_bcount - mtaddr->mtbc; 3244736Swnj break; 3254736Swnj 3264736Swnj case MTER_RDOPP: 3274736Swnj mi->mi_tab.b_errcnt = 2; /* indicate "read opposite" */ 3284736Swnj bp->b_resid = bp->b_bcount; /* save it */ 3294736Swnj bp->b_bcount = mtaddr->mtbc; /* use this instead */ 3304736Swnj return(MBD_RETRY); 3314736Swnj 3324736Swnj case MTER_RETRY: 3334736Swnj mi->mi_tab.b_errcnt = 1; /* indicate simple retry */ 3344736Swnj return(MBD_RETRY); 3354736Swnj 3364736Swnj case MTER_OFFLINE: 3374736Swnj if (sc->sc_openf > 0) { 3384736Swnj sc->sc_openf = -1; 3394736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 3404736Swnj } 3414736Swnj bp->b_flags |= B_ERROR; 3424736Swnj break; 3434736Swnj 3444736Swnj case MTER_FPT: 3454736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 3464736Swnj bp->b_flags |= B_ERROR; 3474736Swnj break; 3484736Swnj 3494736Swnj default: 3504736Swnj printf("mu%d: hard error bn%d mbsr=%b er=%x ds=%b\n", 3514736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 3524736Swnj mbsr, mbsr_bits, sc->sc_erreg, 3534736Swnj sc->sc_dsreg, mtds_bits); 3544736Swnj bp->b_flags |= B_ERROR; 3554736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 3564736Swnj DELAY(250); 3574736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 3584736Swnj ; 3594736Swnj return (MBD_DONE); 3604736Swnj } 3614736Swnj /* CHECK FOR MBA ERROR WHEN NO OTHER ERROR INDICATED? */ 3624736Swnj return (MBD_DONE); 3634736Swnj } 3644736Swnj 3654736Swnj mtndtint(mi) 3664736Swnj register struct mba_device *mi; 3674736Swnj { 3684736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 3694736Swnj register struct buf *bp = mi->mi_tab.b_actf; 3704736Swnj register struct mu_softc *sc; 3714736Swnj int er, fc, unit; 3724736Swnj 3734736Swnj unit = (mtaddr->mtner >> 8) & 3; 3744736Swnj er = MASKREG(mtaddr->mtner); 3754736Swnj /* WILL THIS OCCUR IF ANOTHER DRIVE COMES ONLINE? */ 3764736Swnj if (bp == 0 || unit != MUUNIT(bp->b_dev)) { /* consistency check */ 3774736Swnj if ((er & MTER_INTCODE) != MTER_ONLINE) 3784736Swnj printf("mt: unit %d random interrupt\n", unit); 3794736Swnj return (MBN_SKIP); 3804736Swnj } 3814736Swnj if (bp == 0) 3824736Swnj return (MBN_SKIP); 3834736Swnj fc = (mtaddr->mtncs[unit] >> 8) & 0xff; 3844736Swnj sc = &mu_softc[unit]; 3854736Swnj sc->sc_erreg = er; 3864736Swnj sc->sc_resid = fc; 3874736Swnj switch (er & MTER_INTCODE) { 3884736Swnj case MTER_DONE: 3894736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) { 3904736Swnj done: 3914736Swnj if (bp->b_command == MT_SENSE) 3924736Swnj sc->sc_dsreg = MASKREG(mtaddr->mtds); 3934736Swnj bp->b_resid = fc; 3944736Swnj return (MBN_DONE); 3954736Swnj } 3964736Swnj /* this is UGLY! (but is it correct?) */ 3977380Ssam if ((fc = bdbtofsb(bp->b_blkno) - sc->sc_blkno) < 0) 3986186Ssam sc->sc_blkno -= MIN(0377, -fc); 3994736Swnj else 4006186Ssam sc->sc_blkno += MIN(0377, fc); 4014736Swnj return (MBN_RETRY); 4024736Swnj 4034736Swnj case MTER_RWDING: 4044736Swnj return (MBN_SKIP); /* ignore "rewind started" interrupt */ 4054736Swnj 4064736Swnj case MTER_NOTCAP: 4074736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 4084736Swnj 4094736Swnj case MTER_TM: 4104736Swnj case MTER_EOT: 4114736Swnj case MTER_LEOT: 4127380Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4137380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + fc; 4144736Swnj sc->sc_blkno = sc->sc_nxrec; 4154736Swnj } else { 4167380Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno) - fc; 4174736Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4184736Swnj } 4194736Swnj return (MBN_RETRY); 4204736Swnj 4214736Swnj case MTER_FPT: 4224736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 4234736Swnj bp->b_flags |= B_ERROR; 4244736Swnj return (MBN_DONE); 4254736Swnj 4264736Swnj case MTER_OFFLINE: 4274736Swnj if (sc->sc_openf > 0) { 4284736Swnj sc->sc_openf = -1; 4294736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 4304736Swnj } 4314736Swnj bp->b_flags |= B_ERROR; 4324736Swnj return (MBN_DONE); 4334736Swnj 4344736Swnj case MTER_BOT: 4354736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) 4364736Swnj goto done; 4374736Swnj /* FALL THROUGH */ 4384736Swnj 4394736Swnj default: 4404736Swnj printf("mu%d: hard error bn%d er=%o ds=%b\n", 4414736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 4424736Swnj sc->sc_erreg, sc->sc_dsreg, mtds_bits); 4434736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 4444736Swnj DELAY(250); 4454736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 4464736Swnj ; 4474736Swnj bp->b_flags |= B_ERROR; 4484736Swnj return (MBN_DONE); 4494736Swnj } 4504736Swnj /* NOTREACHED */ 4514736Swnj } 4524736Swnj 4537740Sroot mtread(dev, uio) 4544736Swnj dev_t dev; 4557740Sroot struct uio *uio; 4564736Swnj { 4578158Sroot int errno; 4584736Swnj 4598158Sroot errno = mtphys(dev, uio); 4608158Sroot if (errno) 4618158Sroot return (errno); 4628158Sroot return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_READ, minphys, uio)); 4634736Swnj } 4644736Swnj 4657833Sroot mtwrite(dev, uio) 4667833Sroot dev_t dev; 4677833Sroot struct uio *uio; 4684736Swnj { 4698158Sroot int errno; 4704736Swnj 4718158Sroot errno = mtphys(dev, uio); 4728158Sroot if (errno) 4738158Sroot return (errno); 4748158Sroot return (physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_WRITE, minphys, uio)); 4754736Swnj } 4764736Swnj 4777740Sroot mtphys(dev, uio) 4784736Swnj dev_t dev; 4797740Sroot struct uio *uio; 4804736Swnj { 4814736Swnj register int mtunit; 4824736Swnj register struct mu_softc *sc; 4834736Swnj register struct mba_device *mi; 4844736Swnj daddr_t a; 4854736Swnj 4864736Swnj mtunit = MTUNIT(dev); 4877833Sroot if (mtunit >= NMT || (mi = mtinfo[mtunit]) == 0 || mi->mi_alive == 0) 4887740Sroot return (ENXIO); 4897833Sroot a = uio->uio_offset >> 9; 4904736Swnj sc = &mu_softc[MUUNIT(dev)]; 4917380Ssam sc->sc_blkno = bdbtofsb(a); 4927380Ssam sc->sc_nxrec = bdbtofsb(a)+1; 4937740Sroot return (0); 4944736Swnj } 4954736Swnj 4964736Swnj /*ARGSUSED*/ 4977637Ssam mtioctl(dev, cmd, data, flag) 4984736Swnj dev_t dev; 4994736Swnj int cmd; 5007637Ssam caddr_t data; 5014736Swnj int flag; 5024736Swnj { 5034736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 5044736Swnj register struct buf *bp = &cmtbuf[MTUNIT(dev)]; 5054736Swnj register callcount; 5066186Ssam register int op; 5074736Swnj int fcount; 5087637Ssam struct mtop *mtop; 5097637Ssam struct mtget *mtget; 5104736Swnj /* we depend of the values and order of the MT codes here */ 5114736Swnj static mtops[] = 5124736Swnj {MT_WTM,MT_SFORWF,MT_SREVF,MT_SFORW,MT_SREV,MT_REW,MT_UNLOAD,MT_SENSE}; 5134736Swnj 5144736Swnj switch (cmd) { 5157637Ssam 5167637Ssam case MTIOCTOP: /* tape operation */ 5177637Ssam mtop = (struct mtop *)mtop; 5187637Ssam switch(mtop->mt_op) { 5197637Ssam 5204736Swnj case MTWEOF: 5217637Ssam callcount = mtop->mt_count; 5224736Swnj fcount = 1; 5234736Swnj break; 5247637Ssam 5254736Swnj case MTFSF: case MTBSF: 5267637Ssam callcount = mtop->mt_count; 5274736Swnj fcount = 1; 5284736Swnj break; 5297637Ssam 5304736Swnj case MTFSR: case MTBSR: 5314736Swnj callcount = 1; 5327637Ssam fcount = mtop->mt_count; 5334736Swnj break; 5347637Ssam 5354736Swnj case MTREW: case MTOFFL: 5364736Swnj callcount = 1; 5374736Swnj fcount = 1; 5384736Swnj break; 5397637Ssam 5404736Swnj default: 541*8581Sroot return (ENXIO); 5424736Swnj } 543*8581Sroot if (callcount <= 0 || fcount <= 0) 544*8581Sroot return (EINVAL); 5457637Ssam op = mtops[mtop->mt_op]; 5464736Swnj if (op == MT_WTM) 5474736Swnj op |= sc->sc_dens; 5484736Swnj while (--callcount >= 0) { 5494736Swnj register int n; 5504736Swnj 5514736Swnj do { 5526186Ssam n = MIN(fcount, 0xff); 5534736Swnj mtcommand(dev, op, n); 5544736Swnj fcount -= n; 5554736Swnj } while (fcount); 5567637Ssam if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) && 557*8581Sroot bp->b_resid) 558*8581Sroot return (EIO); 5594736Swnj if (bp->b_flags&B_ERROR) 5604736Swnj break; 5614736Swnj } 562*8581Sroot geterror(bp); /* XXX */ 563*8581Sroot return (u.u_error); /* XXX */ 5647637Ssam 5654736Swnj case MTIOCGET: 5667637Ssam mtget = (struct mtget *)data; 5677637Ssam mtget->mt_erreg = sc->sc_erreg; 5687637Ssam mtget->mt_resid = sc->sc_resid; 5694736Swnj mtcommand(dev, MT_SENSE, 1); /* update drive status */ 5707637Ssam mtget->mt_dsreg = sc->sc_dsreg; 5717637Ssam mtget->mt_type = MT_ISMT; 572*8581Sroot break; 5737637Ssam 5744736Swnj default: 575*8581Sroot return (ENXIO); 5764736Swnj } 577*8581Sroot return (0); 5784736Swnj } 5794736Swnj 5804736Swnj #define DBSIZE 20 5814736Swnj 5824736Swnj mtdump() 5834736Swnj { 5844736Swnj register struct mba_device *mi; 5854736Swnj register struct mba_regs *mp; 5864736Swnj register struct mtdevice *mtaddr; 5874736Swnj int blk, num; 5884736Swnj int start; 5894736Swnj 5904736Swnj start = 0; 5914736Swnj num = maxfree; 5924736Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5934736Swnj if (mtinfo[0] == 0) 5944736Swnj return (ENXIO); 5954736Swnj mi = phys(mtinfo[0], struct mba_device *); 5964736Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5974736Swnj mp->mba_cr = MBCR_IE; 5986186Ssam #if lint 5996186Ssam blk = blk; num = num; start = start; 6006186Ssam return (0); 6016186Ssam #endif 6026186Ssam #ifdef notyet 6034736Swnj mtaddr = (struct mtdevice *)&mp->mba_drv[mi->mi_drive]; 6044736Swnj mtaddr->mttc = MTTC_PDP11|MTTC_1600BPI; 6054736Swnj mtaddr->mtcs1 = MT_DCLR|MT_GO; 6064736Swnj while (num > 0) { 6074736Swnj blk = num > DBSIZE ? DBSIZE : num; 6084736Swnj mtdwrite(start, blk, mtaddr, mp); 6094736Swnj start += blk; 6104736Swnj num -= blk; 6114736Swnj } 6124736Swnj mteof(mtaddr); 6134736Swnj mteof(mtaddr); 6144736Swnj mtwait(mtaddr); 6154736Swnj if (mtaddr->mtds&MTDS_ERR) 6164736Swnj return (EIO); 6174736Swnj mtaddr->mtcs1 = MT_REW|MT_GO; 6184736Swnj return (0); 6194736Swnj } 6204736Swnj 6214736Swnj mtdwrite(dbuf, num, mtaddr, mp) 6224736Swnj register dbuf, num; 6234736Swnj register struct mtdevice *mtaddr; 6244736Swnj struct mba_regs *mp; 6254736Swnj { 6264736Swnj register struct pte *io; 6274736Swnj register int i; 6284736Swnj 6294736Swnj mtwait(mtaddr); 6304736Swnj io = mp->mba_map; 6314736Swnj for (i = 0; i < num; i++) 6324736Swnj *(int *)io++ = dbuf++ | PG_V; 6334736Swnj mtaddr->mtfc = -(num*NBPG); 6344736Swnj mp->mba_sr = -1; 6354736Swnj mp->mba_bcr = -(num*NBPG); 6364736Swnj mp->mba_var = 0; 6374736Swnj mtaddr->mtcs1 = MT_WCOM|MT_GO; 6384736Swnj } 6394736Swnj 6404736Swnj mtwait(mtaddr) 6414736Swnj struct mtdevice *mtaddr; 6424736Swnj { 6434736Swnj register s; 6444736Swnj 6454736Swnj do 6464736Swnj s = mtaddr->mtds; 6474736Swnj while ((s & MTDS_DRY) == 0); 6484736Swnj } 6494736Swnj 6504736Swnj mteof(mtaddr) 6514736Swnj struct mtdevice *mtaddr; 6524736Swnj { 6534736Swnj 6544736Swnj mtwait(mtaddr); 6554736Swnj mtaddr->mtcs1 = MT_WEOF|MT_GO; 6564736Swnj #endif notyet 6574736Swnj } 6584736Swnj #endif 659