1*7637Ssam /* mt.c 4.6 82/08/01 */ 24736Swnj 34736Swnj #include "mu.h" 44736Swnj #if NMT > 0 54736Swnj /* 64736Swnj * TM78/TU78 tape driver 74736Swnj * 84736Swnj * Behavior in complex error situations is uncertain... 94736Swnj * 104736Swnj * TODO: 114736Swnj * test error recovery 124736Swnj * add odd byte count kludge from VMS driver 134736Swnj * write dump routine 144736Swnj */ 154736Swnj #include "../h/param.h" 164736Swnj #include "../h/systm.h" 174736Swnj #include "../h/buf.h" 184736Swnj #include "../h/conf.h" 194736Swnj #include "../h/dir.h" 204736Swnj #include "../h/file.h" 214736Swnj #include "../h/user.h" 224736Swnj #include "../h/map.h" 234736Swnj #include "../h/pte.h" 244736Swnj #include "../h/mbareg.h" 254736Swnj #include "../h/mbavar.h" 26*7637Ssam #include "../h/ioctl.h" 274736Swnj #include "../h/mtio.h" 284736Swnj #include "../h/cmap.h" 294736Swnj #include "../h/cpu.h" 304736Swnj 314736Swnj #include "../h/mtreg.h" 324736Swnj 334736Swnj struct buf rmtbuf[NMT]; 344736Swnj struct buf cmtbuf[NMT]; 354736Swnj 364736Swnj short mttypes[] = 374736Swnj { MBDT_TU78, 0 }; 384736Swnj struct mba_device *mtinfo[NMT]; 394736Swnj int mtattach(), mtslave(), mtustart(), mtstart(), mtndtint(), mtdtint(); 404736Swnj struct mba_driver mtdriver = 414736Swnj { mtattach, mtslave, mtustart, mtstart, mtdtint, mtndtint, 424736Swnj mttypes, "mt", "mu", mtinfo }; 434736Swnj 444736Swnj #define MASKREG(r) ((r) & 0xffff) 454736Swnj 464736Swnj /* bits in minor device */ 474736Swnj #define MUUNIT(dev) (minor(dev)&03) 484736Swnj #define H_NOREWIND 04 494736Swnj #define H_6250BPI 08 504736Swnj 514736Swnj #define MTUNIT(dev) (mutomt[MUUNIT(dev)]) 524736Swnj 534736Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544736Swnj 554736Swnj struct mu_softc { 564736Swnj char sc_openf; 574736Swnj char sc_flags; 584736Swnj daddr_t sc_blkno; 594736Swnj daddr_t sc_nxrec; 604736Swnj u_short sc_erreg; 614736Swnj u_short sc_dsreg; 624736Swnj short sc_resid; 634736Swnj short sc_dens; 644736Swnj struct mba_device *sc_mi; 654736Swnj int sc_slave; 664736Swnj } mu_softc[NMU]; 674736Swnj short mutomt[NMU]; 684736Swnj 694736Swnj /* 704736Swnj * Bits for sc_flags. 714736Swnj */ 724736Swnj #define H_WRITTEN 1 /* last operation was a write */ 734736Swnj 744736Swnj char mtds_bits[] = MTDS_BITS; 754736Swnj 764736Swnj /*ARGSUSED*/ 774736Swnj mtattach(mi) 784736Swnj struct mba_device *mi; 794736Swnj { 806186Ssam #ifdef lint 816186Ssam mtread(0); mtwrite(0); mtioctl(0, 0, 0, 0); 826186Ssam #endif 834736Swnj } 844736Swnj 857431Skre mtslave(mi, ms, sn) 864736Swnj struct mba_device *mi; 874736Swnj struct mba_slave *ms; 887431Skre int sn; 894736Swnj { 904736Swnj register struct mu_softc *sc = &mu_softc[ms->ms_unit]; 914736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 924736Swnj int s = spl7(), rtn = 0; 934736Swnj 944736Swnj mtaddr->mtas = -1; 957431Skre mtaddr->mtncs[sn] = MT_SENSE|MT_GO; 964736Swnj while (mtaddr->mtas == 0) 974736Swnj ; 984736Swnj if ((mtaddr->mtner & MTER_INTCODE) == MTER_DONE && 994736Swnj (mtaddr->mtds & MTDS_PRES)) { 1004736Swnj sc->sc_mi = mi; 1017431Skre sc->sc_slave = sn; 1024736Swnj mutomt[ms->ms_unit] = mi->mi_unit; 1034736Swnj rtn = 1; 1044736Swnj } 1054736Swnj mtaddr->mtas = mtaddr->mtas; 1064736Swnj splx(s); 1074736Swnj return (rtn); 1084736Swnj } 1094736Swnj 1104736Swnj mtopen(dev, flag) 1114736Swnj dev_t dev; 1124736Swnj int flag; 1134736Swnj { 1144736Swnj register int muunit; 1154736Swnj register struct mba_device *mi; 1164736Swnj register struct mu_softc *sc; 1174736Swnj int olddens, dens; 1184736Swnj 1194736Swnj muunit = MUUNIT(dev); 1204736Swnj if (muunit >= NMU || (sc = &mu_softc[muunit])->sc_openf || 1214736Swnj (mi = mtinfo[MTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 1224736Swnj u.u_error = ENXIO; 1234736Swnj return; 1244736Swnj } 1254736Swnj olddens = sc->sc_dens; 1264736Swnj dens = sc->sc_dens = (minor(dev)&H_6250BPI) ? MT_GCR : 0; 1274736Swnj mtcommand(dev, MT_SENSE, 1); 1284736Swnj sc->sc_dens = olddens; 1294736Swnj if ((sc->sc_dsreg & MTDS_ONL) == 0) { 1304736Swnj uprintf("mu%d: not online\n", muunit); 1314736Swnj u.u_error = EIO; 1324736Swnj return; 1334736Swnj } 1344736Swnj if ((flag&FWRITE) && (sc->sc_dsreg&MTDS_FPT)) { 1354736Swnj uprintf("mu%d: no write ring\n", muunit); 1364736Swnj u.u_error = EIO; 1374736Swnj return; 1384736Swnj } 1394736Swnj if ((sc->sc_dsreg & MTDS_BOT) == 0 && (flag&FWRITE) && 1404736Swnj dens != sc->sc_dens) { 1414736Swnj uprintf("mu%d: can't change density in mid-tape\n", muunit); 1424736Swnj u.u_error = EIO; 1434736Swnj return; 1444736Swnj } 1454736Swnj sc->sc_openf = 1; 1464736Swnj sc->sc_blkno = (daddr_t)0; 1474736Swnj sc->sc_nxrec = INF; 1484736Swnj sc->sc_flags = 0; 1494736Swnj sc->sc_dens = dens; 1504736Swnj } 1514736Swnj 1524736Swnj mtclose(dev, flag) 1534736Swnj register dev_t dev; 1544736Swnj register flag; 1554736Swnj { 1564736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 1574736Swnj 1584736Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) 1594736Swnj mtcommand(dev, MT_CLS|sc->sc_dens, 1); 1604736Swnj if ((minor(dev)&H_NOREWIND) == 0) 1614736Swnj mtcommand(dev, MT_REW, 0); 1624736Swnj sc->sc_openf = 0; 1634736Swnj } 1644736Swnj 1654736Swnj mtcommand(dev, com, count) 1664736Swnj dev_t dev; 1674736Swnj int com, count; 1684736Swnj { 1694736Swnj register struct buf *bp; 1705437Sroot register int s; 1714736Swnj 1724736Swnj bp = &cmtbuf[MTUNIT(dev)]; 1735437Sroot s = spl5(); 1744736Swnj while (bp->b_flags&B_BUSY) { 1754736Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1764736Swnj break; 1774736Swnj bp->b_flags |= B_WANTED; 1784736Swnj sleep((caddr_t)bp, PRIBIO); 1794736Swnj } 1804736Swnj bp->b_flags = B_BUSY|B_READ; 1815437Sroot splx(s); 1824736Swnj bp->b_dev = dev; 1834736Swnj bp->b_command = com; 1844736Swnj bp->b_repcnt = count; 1854736Swnj bp->b_blkno = 0; 1864736Swnj mtstrategy(bp); 1874736Swnj if (count == 0) 1884736Swnj return; 1894736Swnj iowait(bp); 1904736Swnj if (bp->b_flags&B_WANTED) 1914736Swnj wakeup((caddr_t)bp); 1924736Swnj bp->b_flags &= B_ERROR; 1934736Swnj } 1944736Swnj 1954736Swnj mtstrategy(bp) 1964736Swnj register struct buf *bp; 1974736Swnj { 1984736Swnj register struct mba_device *mi = mtinfo[MTUNIT(bp->b_dev)]; 1994736Swnj register struct buf *dp; 2005437Sroot register int s; 2014736Swnj 2024736Swnj bp->av_forw = NULL; 2034736Swnj dp = &mi->mi_tab; 2045437Sroot s = spl5(); 2054736Swnj if (dp->b_actf == NULL) 2064736Swnj dp->b_actf = bp; 2074736Swnj else 2084736Swnj dp->b_actl->av_forw = bp; 2094736Swnj dp->b_actl = bp; 2104736Swnj if (dp->b_active == 0) 2114736Swnj mbustart(mi); 2125437Sroot splx(s); 2134736Swnj } 2144736Swnj 2154736Swnj mtustart(mi) 2164736Swnj register struct mba_device *mi; 2174736Swnj { 2184736Swnj register struct mtdevice *mtaddr = 2194736Swnj (struct mtdevice *)mi->mi_drv; 2204736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2214736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2224736Swnj daddr_t blkno; 2234736Swnj 2244736Swnj sc->sc_flags &= ~H_WRITTEN; 2254736Swnj if (sc->sc_openf < 0) { 2264736Swnj bp->b_flags |= B_ERROR; 2274736Swnj return (MBU_NEXT); 2284736Swnj } 2294736Swnj if (bp != &cmtbuf[MTUNIT(bp->b_dev)]) { 2307380Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2314736Swnj bp->b_flags |= B_ERROR; 2324736Swnj bp->b_error = ENXIO; 2334736Swnj return (MBU_NEXT); 2344736Swnj } 2357380Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 2364736Swnj bp->b_flags&B_READ) { 2374736Swnj bp->b_resid = bp->b_bcount; 2384736Swnj clrbuf(bp); 2394736Swnj return (MBU_NEXT); 2404736Swnj } 2414736Swnj if ((bp->b_flags&B_READ)==0) 2427380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 2434736Swnj } else { 2444736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2454736Swnj (bp->b_repcnt<<8)|bp->b_command|MT_GO; 2464736Swnj return (MBU_STARTED); 2474736Swnj } 2487380Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 2494736Swnj if (mi->mi_tab.b_errcnt == 2) { 2504736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2514736Swnj } else { 2524736Swnj mtaddr->mtbc = bp->b_bcount; 2534736Swnj mtaddr->mtca = (1<<2)|MUUNIT(bp->b_dev); 2544736Swnj } 2554736Swnj return (MBU_DODATA); 2564736Swnj } 2577380Ssam if (blkno < bdbtofsb(bp->b_blkno)) 2584736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2597380Ssam (min((unsigned)(bdbtofsb(bp->b_blkno) - blkno), 0377) << 8) | 2606186Ssam MT_SFORW|MT_GO; 2614736Swnj else 2624736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2637380Ssam (min((unsigned)(blkno - bdbtofsb(bp->b_blkno)), 0377) << 8) | 2646186Ssam MT_SREV|MT_GO; 2654736Swnj return (MBU_STARTED); 2664736Swnj } 2674736Swnj 2684736Swnj mtstart(mi) 2694736Swnj register struct mba_device *mi; 2704736Swnj { 2714736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2724736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2734736Swnj 2744736Swnj if (bp->b_flags & B_READ) 2754736Swnj if (mi->mi_tab.b_errcnt == 2) 2764736Swnj return(MT_READREV|MT_GO); 2774736Swnj else 2784736Swnj return(MT_READ|MT_GO); 2794736Swnj else 2804736Swnj return(MT_WRITE|sc->sc_dens|MT_GO); 2814736Swnj } 2824736Swnj 2834736Swnj mtdtint(mi, mbsr) 2844736Swnj register struct mba_device *mi; 2854736Swnj int mbsr; 2864736Swnj { 2874736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 2884736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2894736Swnj register struct mu_softc *sc; 2904736Swnj 2914736Swnj /* I'M NOT SURE IF THIS SHOULD ALWAYS BE THE CASE SO FOR NOW... */ 2924736Swnj if ((mtaddr->mtca&3) != MUUNIT(bp->b_dev)) { 2934736Swnj printf("mt: wrong unit!\n"); 2944736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2954736Swnj } 2964736Swnj sc = &mu_softc[MUUNIT(bp->b_dev)]; 2974736Swnj sc->sc_erreg = mtaddr->mter; 2984736Swnj if((bp->b_flags & B_READ) == 0) 2994736Swnj sc->sc_flags |= H_WRITTEN; 3004736Swnj switch (sc->sc_erreg & MTER_INTCODE) { 3014736Swnj case MTER_DONE: 3024736Swnj case MTER_LONGREC: 3034736Swnj if (mi->mi_tab.b_errcnt != 2) 3044736Swnj sc->sc_blkno++; 3054736Swnj bp->b_resid = 0; 3064736Swnj break; 3074736Swnj 3084736Swnj case MTER_NOTCAP: 3094736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 3104736Swnj goto err; 3114736Swnj 3124736Swnj case MTER_TM: 3134736Swnj case MTER_EOT: 3144736Swnj sc->sc_blkno++; 3154736Swnj err: 3164736Swnj bp->b_resid = bp->b_bcount; 3177380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 3184736Swnj break; 3194736Swnj 3204736Swnj case MTER_SHRTREC: 3214736Swnj sc->sc_blkno++; 3224736Swnj if (bp != &rmtbuf[MTUNIT(bp->b_dev)]) 3234736Swnj bp->b_flags |= B_ERROR; 3244736Swnj if (mi->mi_tab.b_errcnt == 2) 3254736Swnj bp->b_bcount = bp->b_resid; /* restore saved value */ 3264736Swnj bp->b_resid = bp->b_bcount - mtaddr->mtbc; 3274736Swnj break; 3284736Swnj 3294736Swnj case MTER_RDOPP: 3304736Swnj mi->mi_tab.b_errcnt = 2; /* indicate "read opposite" */ 3314736Swnj bp->b_resid = bp->b_bcount; /* save it */ 3324736Swnj bp->b_bcount = mtaddr->mtbc; /* use this instead */ 3334736Swnj return(MBD_RETRY); 3344736Swnj 3354736Swnj case MTER_RETRY: 3364736Swnj mi->mi_tab.b_errcnt = 1; /* indicate simple retry */ 3374736Swnj return(MBD_RETRY); 3384736Swnj 3394736Swnj case MTER_OFFLINE: 3404736Swnj if (sc->sc_openf > 0) { 3414736Swnj sc->sc_openf = -1; 3424736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 3434736Swnj } 3444736Swnj bp->b_flags |= B_ERROR; 3454736Swnj break; 3464736Swnj 3474736Swnj case MTER_FPT: 3484736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 3494736Swnj bp->b_flags |= B_ERROR; 3504736Swnj break; 3514736Swnj 3524736Swnj default: 3534736Swnj printf("mu%d: hard error bn%d mbsr=%b er=%x ds=%b\n", 3544736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 3554736Swnj mbsr, mbsr_bits, sc->sc_erreg, 3564736Swnj sc->sc_dsreg, mtds_bits); 3574736Swnj bp->b_flags |= B_ERROR; 3584736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 3594736Swnj DELAY(250); 3604736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 3614736Swnj ; 3624736Swnj return (MBD_DONE); 3634736Swnj } 3644736Swnj /* CHECK FOR MBA ERROR WHEN NO OTHER ERROR INDICATED? */ 3654736Swnj return (MBD_DONE); 3664736Swnj } 3674736Swnj 3684736Swnj mtndtint(mi) 3694736Swnj register struct mba_device *mi; 3704736Swnj { 3714736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 3724736Swnj register struct buf *bp = mi->mi_tab.b_actf; 3734736Swnj register struct mu_softc *sc; 3744736Swnj int er, fc, unit; 3754736Swnj 3764736Swnj unit = (mtaddr->mtner >> 8) & 3; 3774736Swnj er = MASKREG(mtaddr->mtner); 3784736Swnj /* WILL THIS OCCUR IF ANOTHER DRIVE COMES ONLINE? */ 3794736Swnj if (bp == 0 || unit != MUUNIT(bp->b_dev)) { /* consistency check */ 3804736Swnj if ((er & MTER_INTCODE) != MTER_ONLINE) 3814736Swnj printf("mt: unit %d random interrupt\n", unit); 3824736Swnj return (MBN_SKIP); 3834736Swnj } 3844736Swnj if (bp == 0) 3854736Swnj return (MBN_SKIP); 3864736Swnj fc = (mtaddr->mtncs[unit] >> 8) & 0xff; 3874736Swnj sc = &mu_softc[unit]; 3884736Swnj sc->sc_erreg = er; 3894736Swnj sc->sc_resid = fc; 3904736Swnj switch (er & MTER_INTCODE) { 3914736Swnj case MTER_DONE: 3924736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) { 3934736Swnj done: 3944736Swnj if (bp->b_command == MT_SENSE) 3954736Swnj sc->sc_dsreg = MASKREG(mtaddr->mtds); 3964736Swnj bp->b_resid = fc; 3974736Swnj return (MBN_DONE); 3984736Swnj } 3994736Swnj /* this is UGLY! (but is it correct?) */ 4007380Ssam if ((fc = bdbtofsb(bp->b_blkno) - sc->sc_blkno) < 0) 4016186Ssam sc->sc_blkno -= MIN(0377, -fc); 4024736Swnj else 4036186Ssam sc->sc_blkno += MIN(0377, fc); 4044736Swnj return (MBN_RETRY); 4054736Swnj 4064736Swnj case MTER_RWDING: 4074736Swnj return (MBN_SKIP); /* ignore "rewind started" interrupt */ 4084736Swnj 4094736Swnj case MTER_NOTCAP: 4104736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 4114736Swnj 4124736Swnj case MTER_TM: 4134736Swnj case MTER_EOT: 4144736Swnj case MTER_LEOT: 4157380Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4167380Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + fc; 4174736Swnj sc->sc_blkno = sc->sc_nxrec; 4184736Swnj } else { 4197380Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno) - fc; 4204736Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4214736Swnj } 4224736Swnj return (MBN_RETRY); 4234736Swnj 4244736Swnj case MTER_FPT: 4254736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 4264736Swnj bp->b_flags |= B_ERROR; 4274736Swnj return (MBN_DONE); 4284736Swnj 4294736Swnj case MTER_OFFLINE: 4304736Swnj if (sc->sc_openf > 0) { 4314736Swnj sc->sc_openf = -1; 4324736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 4334736Swnj } 4344736Swnj bp->b_flags |= B_ERROR; 4354736Swnj return (MBN_DONE); 4364736Swnj 4374736Swnj case MTER_BOT: 4384736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) 4394736Swnj goto done; 4404736Swnj /* FALL THROUGH */ 4414736Swnj 4424736Swnj default: 4434736Swnj printf("mu%d: hard error bn%d er=%o ds=%b\n", 4444736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 4454736Swnj sc->sc_erreg, sc->sc_dsreg, mtds_bits); 4464736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 4474736Swnj DELAY(250); 4484736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 4494736Swnj ; 4504736Swnj bp->b_flags |= B_ERROR; 4514736Swnj return (MBN_DONE); 4524736Swnj } 4534736Swnj /* NOTREACHED */ 4544736Swnj } 4554736Swnj 4564736Swnj mtread(dev) 4574736Swnj dev_t dev; 4584736Swnj { 4594736Swnj 4604736Swnj mtphys(dev); 4614736Swnj if (u.u_error) 4624736Swnj return; 4634736Swnj physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_READ, minphys); 4644736Swnj } 4654736Swnj 4664736Swnj mtwrite(dev) 4674736Swnj { 4684736Swnj 4694736Swnj mtphys(dev); 4704736Swnj if (u.u_error) 4714736Swnj return; 4724736Swnj physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_WRITE, minphys); 4734736Swnj } 4744736Swnj 4754736Swnj mtphys(dev) 4764736Swnj dev_t dev; 4774736Swnj { 4784736Swnj register int mtunit; 4794736Swnj register struct mu_softc *sc; 4804736Swnj register struct mba_device *mi; 4814736Swnj daddr_t a; 4824736Swnj 4834736Swnj mtunit = MTUNIT(dev); 4844736Swnj if (mtunit >= NMT || (mi = mtinfo[mtunit]) == 0 || mi->mi_alive == 0) { 4854736Swnj u.u_error = ENXIO; 4864736Swnj return; 4874736Swnj } 4884736Swnj a = u.u_offset >> 9; 4894736Swnj sc = &mu_softc[MUUNIT(dev)]; 4907380Ssam sc->sc_blkno = bdbtofsb(a); 4917380Ssam sc->sc_nxrec = bdbtofsb(a)+1; 4924736Swnj } 4934736Swnj 4944736Swnj /*ARGSUSED*/ 495*7637Ssam mtioctl(dev, cmd, data, flag) 4964736Swnj dev_t dev; 4974736Swnj int cmd; 498*7637Ssam caddr_t data; 4994736Swnj int flag; 5004736Swnj { 5014736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 5024736Swnj register struct buf *bp = &cmtbuf[MTUNIT(dev)]; 5034736Swnj register callcount; 5046186Ssam register int op; 5054736Swnj int fcount; 506*7637Ssam struct mtop *mtop; 507*7637Ssam struct mtget *mtget; 5084736Swnj /* we depend of the values and order of the MT codes here */ 5094736Swnj static mtops[] = 5104736Swnj {MT_WTM,MT_SFORWF,MT_SREVF,MT_SFORW,MT_SREV,MT_REW,MT_UNLOAD,MT_SENSE}; 5114736Swnj 5124736Swnj switch (cmd) { 513*7637Ssam 514*7637Ssam case MTIOCTOP: /* tape operation */ 515*7637Ssam mtop = (struct mtop *)mtop; 516*7637Ssam switch(mtop->mt_op) { 517*7637Ssam 5184736Swnj case MTWEOF: 519*7637Ssam callcount = mtop->mt_count; 5204736Swnj fcount = 1; 5214736Swnj break; 522*7637Ssam 5234736Swnj case MTFSF: case MTBSF: 524*7637Ssam callcount = mtop->mt_count; 5254736Swnj fcount = 1; 5264736Swnj break; 527*7637Ssam 5284736Swnj case MTFSR: case MTBSR: 5294736Swnj callcount = 1; 530*7637Ssam fcount = mtop->mt_count; 5314736Swnj break; 532*7637Ssam 5334736Swnj case MTREW: case MTOFFL: 5344736Swnj callcount = 1; 5354736Swnj fcount = 1; 5364736Swnj break; 537*7637Ssam 5384736Swnj default: 5394736Swnj u.u_error = ENXIO; 5404736Swnj return; 5414736Swnj } 5424736Swnj if (callcount <= 0 || fcount <= 0) { 5434736Swnj u.u_error = ENXIO; 5444736Swnj return; 5454736Swnj } 546*7637Ssam op = mtops[mtop->mt_op]; 5474736Swnj if (op == MT_WTM) 5484736Swnj op |= sc->sc_dens; 5494736Swnj while (--callcount >= 0) { 5504736Swnj register int n; 5514736Swnj 5524736Swnj do { 5536186Ssam n = MIN(fcount, 0xff); 5544736Swnj mtcommand(dev, op, n); 5554736Swnj fcount -= n; 5564736Swnj } while (fcount); 557*7637Ssam if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) && 5584736Swnj bp->b_resid) { 5594736Swnj u.u_error = EIO; 5604736Swnj break; 5614736Swnj } 5624736Swnj if (bp->b_flags&B_ERROR) 5634736Swnj break; 5644736Swnj } 5654736Swnj geterror(bp); 5664736Swnj return; 567*7637Ssam 5684736Swnj case MTIOCGET: 569*7637Ssam mtget = (struct mtget *)data; 570*7637Ssam mtget->mt_erreg = sc->sc_erreg; 571*7637Ssam mtget->mt_resid = sc->sc_resid; 5724736Swnj mtcommand(dev, MT_SENSE, 1); /* update drive status */ 573*7637Ssam mtget->mt_dsreg = sc->sc_dsreg; 574*7637Ssam mtget->mt_type = MT_ISMT; 5754736Swnj return; 576*7637Ssam 5774736Swnj default: 5784736Swnj u.u_error = ENXIO; 5794736Swnj } 5804736Swnj } 5814736Swnj 5824736Swnj #define DBSIZE 20 5834736Swnj 5844736Swnj mtdump() 5854736Swnj { 5864736Swnj register struct mba_device *mi; 5874736Swnj register struct mba_regs *mp; 5884736Swnj register struct mtdevice *mtaddr; 5894736Swnj int blk, num; 5904736Swnj int start; 5914736Swnj 5924736Swnj start = 0; 5934736Swnj num = maxfree; 5944736Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5954736Swnj if (mtinfo[0] == 0) 5964736Swnj return (ENXIO); 5974736Swnj mi = phys(mtinfo[0], struct mba_device *); 5984736Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5994736Swnj mp->mba_cr = MBCR_IE; 6006186Ssam #if lint 6016186Ssam blk = blk; num = num; start = start; 6026186Ssam return (0); 6036186Ssam #endif 6046186Ssam #ifdef notyet 6054736Swnj mtaddr = (struct mtdevice *)&mp->mba_drv[mi->mi_drive]; 6064736Swnj mtaddr->mttc = MTTC_PDP11|MTTC_1600BPI; 6074736Swnj mtaddr->mtcs1 = MT_DCLR|MT_GO; 6084736Swnj while (num > 0) { 6094736Swnj blk = num > DBSIZE ? DBSIZE : num; 6104736Swnj mtdwrite(start, blk, mtaddr, mp); 6114736Swnj start += blk; 6124736Swnj num -= blk; 6134736Swnj } 6144736Swnj mteof(mtaddr); 6154736Swnj mteof(mtaddr); 6164736Swnj mtwait(mtaddr); 6174736Swnj if (mtaddr->mtds&MTDS_ERR) 6184736Swnj return (EIO); 6194736Swnj mtaddr->mtcs1 = MT_REW|MT_GO; 6204736Swnj return (0); 6214736Swnj } 6224736Swnj 6234736Swnj mtdwrite(dbuf, num, mtaddr, mp) 6244736Swnj register dbuf, num; 6254736Swnj register struct mtdevice *mtaddr; 6264736Swnj struct mba_regs *mp; 6274736Swnj { 6284736Swnj register struct pte *io; 6294736Swnj register int i; 6304736Swnj 6314736Swnj mtwait(mtaddr); 6324736Swnj io = mp->mba_map; 6334736Swnj for (i = 0; i < num; i++) 6344736Swnj *(int *)io++ = dbuf++ | PG_V; 6354736Swnj mtaddr->mtfc = -(num*NBPG); 6364736Swnj mp->mba_sr = -1; 6374736Swnj mp->mba_bcr = -(num*NBPG); 6384736Swnj mp->mba_var = 0; 6394736Swnj mtaddr->mtcs1 = MT_WCOM|MT_GO; 6404736Swnj } 6414736Swnj 6424736Swnj mtwait(mtaddr) 6434736Swnj struct mtdevice *mtaddr; 6444736Swnj { 6454736Swnj register s; 6464736Swnj 6474736Swnj do 6484736Swnj s = mtaddr->mtds; 6494736Swnj while ((s & MTDS_DRY) == 0); 6504736Swnj } 6514736Swnj 6524736Swnj mteof(mtaddr) 6534736Swnj struct mtdevice *mtaddr; 6544736Swnj { 6554736Swnj 6564736Swnj mtwait(mtaddr); 6574736Swnj mtaddr->mtcs1 = MT_WEOF|MT_GO; 6584736Swnj #endif notyet 6594736Swnj } 6604736Swnj #endif 661