1*5437Sroot /* mt.c 4.2 82/01/17 */ 24736Swnj 34736Swnj #include "mu.h" 44736Swnj #if NMT > 0 54736Swnj /* 64736Swnj * TM78/TU78 tape driver 74736Swnj * 84736Swnj * Behavior in complex error situations is uncertain... 94736Swnj * 104736Swnj * TODO: 114736Swnj * test error recovery 124736Swnj * add odd byte count kludge from VMS driver 134736Swnj * write dump routine 144736Swnj */ 154736Swnj #include "../h/param.h" 164736Swnj #include "../h/systm.h" 174736Swnj #include "../h/buf.h" 184736Swnj #include "../h/conf.h" 194736Swnj #include "../h/dir.h" 204736Swnj #include "../h/file.h" 214736Swnj #include "../h/user.h" 224736Swnj #include "../h/map.h" 234736Swnj #include "../h/pte.h" 244736Swnj #include "../h/mbareg.h" 254736Swnj #include "../h/mbavar.h" 264736Swnj #include "../h/mtio.h" 274736Swnj #include "../h/ioctl.h" 284736Swnj #include "../h/cmap.h" 294736Swnj #include "../h/cpu.h" 304736Swnj 314736Swnj #include "../h/mtreg.h" 324736Swnj 334736Swnj struct buf rmtbuf[NMT]; 344736Swnj struct buf cmtbuf[NMT]; 354736Swnj 364736Swnj short mttypes[] = 374736Swnj { MBDT_TU78, 0 }; 384736Swnj struct mba_device *mtinfo[NMT]; 394736Swnj int mtattach(), mtslave(), mtustart(), mtstart(), mtndtint(), mtdtint(); 404736Swnj struct mba_driver mtdriver = 414736Swnj { mtattach, mtslave, mtustart, mtstart, mtdtint, mtndtint, 424736Swnj mttypes, "mt", "mu", mtinfo }; 434736Swnj 444736Swnj #define MASKREG(r) ((r) & 0xffff) 454736Swnj 464736Swnj /* bits in minor device */ 474736Swnj #define MUUNIT(dev) (minor(dev)&03) 484736Swnj #define H_NOREWIND 04 494736Swnj #define H_6250BPI 08 504736Swnj 514736Swnj #define MTUNIT(dev) (mutomt[MUUNIT(dev)]) 524736Swnj 534736Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544736Swnj 554736Swnj struct mu_softc { 564736Swnj char sc_openf; 574736Swnj char sc_flags; 584736Swnj daddr_t sc_blkno; 594736Swnj daddr_t sc_nxrec; 604736Swnj u_short sc_erreg; 614736Swnj u_short sc_dsreg; 624736Swnj short sc_resid; 634736Swnj short sc_dens; 644736Swnj struct mba_device *sc_mi; 654736Swnj int sc_slave; 664736Swnj } mu_softc[NMU]; 674736Swnj short mutomt[NMU]; 684736Swnj 694736Swnj /* 704736Swnj * Bits for sc_flags. 714736Swnj */ 724736Swnj #define H_WRITTEN 1 /* last operation was a write */ 734736Swnj 744736Swnj char mtds_bits[] = MTDS_BITS; 754736Swnj 764736Swnj /*ARGSUSED*/ 774736Swnj mtattach(mi) 784736Swnj struct mba_device *mi; 794736Swnj { 804736Swnj 814736Swnj } 824736Swnj 834736Swnj mtslave(mi, ms) 844736Swnj struct mba_device *mi; 854736Swnj struct mba_slave *ms; 864736Swnj { 874736Swnj register struct mu_softc *sc = &mu_softc[ms->ms_unit]; 884736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 894736Swnj int s = spl7(), rtn = 0; 904736Swnj 914736Swnj mtaddr->mtas = -1; 924736Swnj mtaddr->mtncs[ms->ms_slave] = MT_SENSE|MT_GO; 934736Swnj while (mtaddr->mtas == 0) 944736Swnj ; 954736Swnj if ((mtaddr->mtner & MTER_INTCODE) == MTER_DONE && 964736Swnj (mtaddr->mtds & MTDS_PRES)) { 974736Swnj sc->sc_mi = mi; 984736Swnj sc->sc_slave = ms->ms_slave; 994736Swnj mutomt[ms->ms_unit] = mi->mi_unit; 1004736Swnj rtn = 1; 1014736Swnj } 1024736Swnj mtaddr->mtas = mtaddr->mtas; 1034736Swnj splx(s); 1044736Swnj return (rtn); 1054736Swnj } 1064736Swnj 1074736Swnj mtopen(dev, flag) 1084736Swnj dev_t dev; 1094736Swnj int flag; 1104736Swnj { 1114736Swnj register int muunit; 1124736Swnj register struct mba_device *mi; 1134736Swnj register struct mu_softc *sc; 1144736Swnj int olddens, dens; 1154736Swnj 1164736Swnj muunit = MUUNIT(dev); 1174736Swnj if (muunit >= NMU || (sc = &mu_softc[muunit])->sc_openf || 1184736Swnj (mi = mtinfo[MTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 1194736Swnj u.u_error = ENXIO; 1204736Swnj return; 1214736Swnj } 1224736Swnj olddens = sc->sc_dens; 1234736Swnj dens = sc->sc_dens = (minor(dev)&H_6250BPI) ? MT_GCR : 0; 1244736Swnj mtcommand(dev, MT_SENSE, 1); 1254736Swnj sc->sc_dens = olddens; 1264736Swnj if ((sc->sc_dsreg & MTDS_ONL) == 0) { 1274736Swnj uprintf("mu%d: not online\n", muunit); 1284736Swnj u.u_error = EIO; 1294736Swnj return; 1304736Swnj } 1314736Swnj if ((flag&FWRITE) && (sc->sc_dsreg&MTDS_FPT)) { 1324736Swnj uprintf("mu%d: no write ring\n", muunit); 1334736Swnj u.u_error = EIO; 1344736Swnj return; 1354736Swnj } 1364736Swnj if ((sc->sc_dsreg & MTDS_BOT) == 0 && (flag&FWRITE) && 1374736Swnj dens != sc->sc_dens) { 1384736Swnj uprintf("mu%d: can't change density in mid-tape\n", muunit); 1394736Swnj u.u_error = EIO; 1404736Swnj return; 1414736Swnj } 1424736Swnj sc->sc_openf = 1; 1434736Swnj sc->sc_blkno = (daddr_t)0; 1444736Swnj sc->sc_nxrec = INF; 1454736Swnj sc->sc_flags = 0; 1464736Swnj sc->sc_dens = dens; 1474736Swnj } 1484736Swnj 1494736Swnj mtclose(dev, flag) 1504736Swnj register dev_t dev; 1514736Swnj register flag; 1524736Swnj { 1534736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 1544736Swnj 1554736Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) 1564736Swnj mtcommand(dev, MT_CLS|sc->sc_dens, 1); 1574736Swnj if ((minor(dev)&H_NOREWIND) == 0) 1584736Swnj mtcommand(dev, MT_REW, 0); 1594736Swnj sc->sc_openf = 0; 1604736Swnj } 1614736Swnj 1624736Swnj mtcommand(dev, com, count) 1634736Swnj dev_t dev; 1644736Swnj int com, count; 1654736Swnj { 1664736Swnj register struct buf *bp; 167*5437Sroot register int s; 1684736Swnj 1694736Swnj bp = &cmtbuf[MTUNIT(dev)]; 170*5437Sroot s = spl5(); 1714736Swnj while (bp->b_flags&B_BUSY) { 1724736Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1734736Swnj break; 1744736Swnj bp->b_flags |= B_WANTED; 1754736Swnj sleep((caddr_t)bp, PRIBIO); 1764736Swnj } 1774736Swnj bp->b_flags = B_BUSY|B_READ; 178*5437Sroot splx(s); 1794736Swnj bp->b_dev = dev; 1804736Swnj bp->b_command = com; 1814736Swnj bp->b_repcnt = count; 1824736Swnj bp->b_blkno = 0; 1834736Swnj mtstrategy(bp); 1844736Swnj if (count == 0) 1854736Swnj return; 1864736Swnj iowait(bp); 1874736Swnj if (bp->b_flags&B_WANTED) 1884736Swnj wakeup((caddr_t)bp); 1894736Swnj bp->b_flags &= B_ERROR; 1904736Swnj } 1914736Swnj 1924736Swnj mtstrategy(bp) 1934736Swnj register struct buf *bp; 1944736Swnj { 1954736Swnj register struct mba_device *mi = mtinfo[MTUNIT(bp->b_dev)]; 1964736Swnj register struct buf *dp; 197*5437Sroot register int s; 1984736Swnj 1994736Swnj bp->av_forw = NULL; 2004736Swnj dp = &mi->mi_tab; 201*5437Sroot s = spl5(); 2024736Swnj if (dp->b_actf == NULL) 2034736Swnj dp->b_actf = bp; 2044736Swnj else 2054736Swnj dp->b_actl->av_forw = bp; 2064736Swnj dp->b_actl = bp; 2074736Swnj if (dp->b_active == 0) 2084736Swnj mbustart(mi); 209*5437Sroot splx(s); 2104736Swnj } 2114736Swnj 2124736Swnj mtustart(mi) 2134736Swnj register struct mba_device *mi; 2144736Swnj { 2154736Swnj register struct mtdevice *mtaddr = 2164736Swnj (struct mtdevice *)mi->mi_drv; 2174736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2184736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2194736Swnj daddr_t blkno; 2204736Swnj 2214736Swnj sc->sc_flags &= ~H_WRITTEN; 2224736Swnj if (sc->sc_openf < 0) { 2234736Swnj bp->b_flags |= B_ERROR; 2244736Swnj return (MBU_NEXT); 2254736Swnj } 2264736Swnj if (bp != &cmtbuf[MTUNIT(bp->b_dev)]) { 2274736Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2284736Swnj bp->b_flags |= B_ERROR; 2294736Swnj bp->b_error = ENXIO; 2304736Swnj return (MBU_NEXT); 2314736Swnj } 2324736Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 2334736Swnj bp->b_flags&B_READ) { 2344736Swnj bp->b_resid = bp->b_bcount; 2354736Swnj clrbuf(bp); 2364736Swnj return (MBU_NEXT); 2374736Swnj } 2384736Swnj if ((bp->b_flags&B_READ)==0) 2394736Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 2404736Swnj } else { 2414736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2424736Swnj (bp->b_repcnt<<8)|bp->b_command|MT_GO; 2434736Swnj return (MBU_STARTED); 2444736Swnj } 2454736Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 2464736Swnj if (mi->mi_tab.b_errcnt == 2) { 2474736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2484736Swnj } else { 2494736Swnj mtaddr->mtbc = bp->b_bcount; 2504736Swnj mtaddr->mtca = (1<<2)|MUUNIT(bp->b_dev); 2514736Swnj } 2524736Swnj return (MBU_DODATA); 2534736Swnj } 2544736Swnj if (blkno < dbtofsb(bp->b_blkno)) 2554736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2564736Swnj (min(dbtofsb(bp->b_blkno) - blkno, 0377)<<8)| MT_SFORW|MT_GO; 2574736Swnj else 2584736Swnj mtaddr->mtncs[MUUNIT(bp->b_dev)] = 2594736Swnj (min(blkno - dbtofsb(bp->b_blkno), 0377)<<8)| MT_SREV|MT_GO; 2604736Swnj return (MBU_STARTED); 2614736Swnj } 2624736Swnj 2634736Swnj mtstart(mi) 2644736Swnj register struct mba_device *mi; 2654736Swnj { 2664736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2674736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(bp->b_dev)]; 2684736Swnj 2694736Swnj if (bp->b_flags & B_READ) 2704736Swnj if (mi->mi_tab.b_errcnt == 2) 2714736Swnj return(MT_READREV|MT_GO); 2724736Swnj else 2734736Swnj return(MT_READ|MT_GO); 2744736Swnj else 2754736Swnj return(MT_WRITE|sc->sc_dens|MT_GO); 2764736Swnj } 2774736Swnj 2784736Swnj mtdtint(mi, mbsr) 2794736Swnj register struct mba_device *mi; 2804736Swnj int mbsr; 2814736Swnj { 2824736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 2834736Swnj register struct buf *bp = mi->mi_tab.b_actf; 2844736Swnj register struct mu_softc *sc; 2854736Swnj 2864736Swnj /* I'M NOT SURE IF THIS SHOULD ALWAYS BE THE CASE SO FOR NOW... */ 2874736Swnj if ((mtaddr->mtca&3) != MUUNIT(bp->b_dev)) { 2884736Swnj printf("mt: wrong unit!\n"); 2894736Swnj mtaddr->mtca = MUUNIT(bp->b_dev); 2904736Swnj } 2914736Swnj sc = &mu_softc[MUUNIT(bp->b_dev)]; 2924736Swnj sc->sc_erreg = mtaddr->mter; 2934736Swnj if((bp->b_flags & B_READ) == 0) 2944736Swnj sc->sc_flags |= H_WRITTEN; 2954736Swnj switch (sc->sc_erreg & MTER_INTCODE) { 2964736Swnj case MTER_DONE: 2974736Swnj case MTER_LONGREC: 2984736Swnj if (mi->mi_tab.b_errcnt != 2) 2994736Swnj sc->sc_blkno++; 3004736Swnj bp->b_resid = 0; 3014736Swnj break; 3024736Swnj 3034736Swnj case MTER_NOTCAP: 3044736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 3054736Swnj goto err; 3064736Swnj 3074736Swnj case MTER_TM: 3084736Swnj case MTER_EOT: 3094736Swnj sc->sc_blkno++; 3104736Swnj err: 3114736Swnj bp->b_resid = bp->b_bcount; 3124736Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 3134736Swnj break; 3144736Swnj 3154736Swnj case MTER_SHRTREC: 3164736Swnj sc->sc_blkno++; 3174736Swnj if (bp != &rmtbuf[MTUNIT(bp->b_dev)]) 3184736Swnj bp->b_flags |= B_ERROR; 3194736Swnj if (mi->mi_tab.b_errcnt == 2) 3204736Swnj bp->b_bcount = bp->b_resid; /* restore saved value */ 3214736Swnj bp->b_resid = bp->b_bcount - mtaddr->mtbc; 3224736Swnj break; 3234736Swnj 3244736Swnj case MTER_RDOPP: 3254736Swnj mi->mi_tab.b_errcnt = 2; /* indicate "read opposite" */ 3264736Swnj bp->b_resid = bp->b_bcount; /* save it */ 3274736Swnj bp->b_bcount = mtaddr->mtbc; /* use this instead */ 3284736Swnj return(MBD_RETRY); 3294736Swnj 3304736Swnj case MTER_RETRY: 3314736Swnj mi->mi_tab.b_errcnt = 1; /* indicate simple retry */ 3324736Swnj return(MBD_RETRY); 3334736Swnj 3344736Swnj case MTER_OFFLINE: 3354736Swnj if (sc->sc_openf > 0) { 3364736Swnj sc->sc_openf = -1; 3374736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 3384736Swnj } 3394736Swnj bp->b_flags |= B_ERROR; 3404736Swnj break; 3414736Swnj 3424736Swnj case MTER_FPT: 3434736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 3444736Swnj bp->b_flags |= B_ERROR; 3454736Swnj break; 3464736Swnj 3474736Swnj default: 3484736Swnj printf("mu%d: hard error bn%d mbsr=%b er=%x ds=%b\n", 3494736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 3504736Swnj mbsr, mbsr_bits, sc->sc_erreg, 3514736Swnj sc->sc_dsreg, mtds_bits); 3524736Swnj bp->b_flags |= B_ERROR; 3534736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 3544736Swnj DELAY(250); 3554736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 3564736Swnj ; 3574736Swnj return (MBD_DONE); 3584736Swnj } 3594736Swnj /* CHECK FOR MBA ERROR WHEN NO OTHER ERROR INDICATED? */ 3604736Swnj return (MBD_DONE); 3614736Swnj } 3624736Swnj 3634736Swnj mtndtint(mi) 3644736Swnj register struct mba_device *mi; 3654736Swnj { 3664736Swnj register struct mtdevice *mtaddr = (struct mtdevice *)mi->mi_drv; 3674736Swnj register struct buf *bp = mi->mi_tab.b_actf; 3684736Swnj register struct mu_softc *sc; 3694736Swnj int er, fc, unit; 3704736Swnj 3714736Swnj unit = (mtaddr->mtner >> 8) & 3; 3724736Swnj er = MASKREG(mtaddr->mtner); 3734736Swnj /* WILL THIS OCCUR IF ANOTHER DRIVE COMES ONLINE? */ 3744736Swnj if (bp == 0 || unit != MUUNIT(bp->b_dev)) { /* consistency check */ 3754736Swnj if ((er & MTER_INTCODE) != MTER_ONLINE) 3764736Swnj printf("mt: unit %d random interrupt\n", unit); 3774736Swnj return (MBN_SKIP); 3784736Swnj } 3794736Swnj if (bp == 0) 3804736Swnj return (MBN_SKIP); 3814736Swnj fc = (mtaddr->mtncs[unit] >> 8) & 0xff; 3824736Swnj sc = &mu_softc[unit]; 3834736Swnj sc->sc_erreg = er; 3844736Swnj sc->sc_resid = fc; 3854736Swnj switch (er & MTER_INTCODE) { 3864736Swnj case MTER_DONE: 3874736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) { 3884736Swnj done: 3894736Swnj if (bp->b_command == MT_SENSE) 3904736Swnj sc->sc_dsreg = MASKREG(mtaddr->mtds); 3914736Swnj bp->b_resid = fc; 3924736Swnj return (MBN_DONE); 3934736Swnj } 3944736Swnj /* this is UGLY! (but is it correct?) */ 3954736Swnj if ((fc = dbtofsb(bp->b_blkno) - sc->sc_blkno) < 0) 3964736Swnj sc->sc_blkno -= min(0377, -fc); 3974736Swnj else 3984736Swnj sc->sc_blkno += min(0377, fc); 3994736Swnj return (MBN_RETRY); 4004736Swnj 4014736Swnj case MTER_RWDING: 4024736Swnj return (MBN_SKIP); /* ignore "rewind started" interrupt */ 4034736Swnj 4044736Swnj case MTER_NOTCAP: 4054736Swnj printf("mu%d: blank tape\n", MUUNIT(bp->b_dev)); 4064736Swnj 4074736Swnj case MTER_TM: 4084736Swnj case MTER_EOT: 4094736Swnj case MTER_LEOT: 4104736Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 4114736Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + fc; 4124736Swnj sc->sc_blkno = sc->sc_nxrec; 4134736Swnj } else { 4144736Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) - fc; 4154736Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4164736Swnj } 4174736Swnj return (MBN_RETRY); 4184736Swnj 4194736Swnj case MTER_FPT: 4204736Swnj printf("mu%d: no write ring\n", MUUNIT(bp->b_dev)); 4214736Swnj bp->b_flags |= B_ERROR; 4224736Swnj return (MBN_DONE); 4234736Swnj 4244736Swnj case MTER_OFFLINE: 4254736Swnj if (sc->sc_openf > 0) { 4264736Swnj sc->sc_openf = -1; 4274736Swnj printf("mu%d: offline\n", MUUNIT(bp->b_dev)); 4284736Swnj } 4294736Swnj bp->b_flags |= B_ERROR; 4304736Swnj return (MBN_DONE); 4314736Swnj 4324736Swnj case MTER_BOT: 4334736Swnj if (bp == &cmtbuf[MTUNIT(bp->b_dev)]) 4344736Swnj goto done; 4354736Swnj /* FALL THROUGH */ 4364736Swnj 4374736Swnj default: 4384736Swnj printf("mu%d: hard error bn%d er=%o ds=%b\n", 4394736Swnj MUUNIT(bp->b_dev), bp->b_blkno, 4404736Swnj sc->sc_erreg, sc->sc_dsreg, mtds_bits); 4414736Swnj mtaddr->mtid = MTID_CLR; /* reset the TM78 */ 4424736Swnj DELAY(250); 4434736Swnj while ((mtaddr->mtid & MTID_RDY) == 0) /* wait for it */ 4444736Swnj ; 4454736Swnj bp->b_flags |= B_ERROR; 4464736Swnj return (MBN_DONE); 4474736Swnj } 4484736Swnj /* NOTREACHED */ 4494736Swnj } 4504736Swnj 4514736Swnj mtread(dev) 4524736Swnj dev_t dev; 4534736Swnj { 4544736Swnj 4554736Swnj mtphys(dev); 4564736Swnj if (u.u_error) 4574736Swnj return; 4584736Swnj physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_READ, minphys); 4594736Swnj } 4604736Swnj 4614736Swnj mtwrite(dev) 4624736Swnj { 4634736Swnj 4644736Swnj mtphys(dev); 4654736Swnj if (u.u_error) 4664736Swnj return; 4674736Swnj physio(mtstrategy, &rmtbuf[MTUNIT(dev)], dev, B_WRITE, minphys); 4684736Swnj } 4694736Swnj 4704736Swnj mtphys(dev) 4714736Swnj dev_t dev; 4724736Swnj { 4734736Swnj register int mtunit; 4744736Swnj register struct mu_softc *sc; 4754736Swnj register struct mba_device *mi; 4764736Swnj daddr_t a; 4774736Swnj 4784736Swnj mtunit = MTUNIT(dev); 4794736Swnj if (mtunit >= NMT || (mi = mtinfo[mtunit]) == 0 || mi->mi_alive == 0) { 4804736Swnj u.u_error = ENXIO; 4814736Swnj return; 4824736Swnj } 4834736Swnj a = u.u_offset >> 9; 4844736Swnj sc = &mu_softc[MUUNIT(dev)]; 4854736Swnj sc->sc_blkno = dbtofsb(a); 4864736Swnj sc->sc_nxrec = dbtofsb(a)+1; 4874736Swnj } 4884736Swnj 4894736Swnj /*ARGSUSED*/ 4904736Swnj mtioctl(dev, cmd, addr, flag) 4914736Swnj dev_t dev; 4924736Swnj int cmd; 4934736Swnj caddr_t addr; 4944736Swnj int flag; 4954736Swnj { 4964736Swnj register struct mu_softc *sc = &mu_softc[MUUNIT(dev)]; 4974736Swnj register struct buf *bp = &cmtbuf[MTUNIT(dev)]; 4984736Swnj register callcount; 4994736Swnj register int n, op; 5004736Swnj int fcount; 5014736Swnj struct mtop mtop; 5024736Swnj struct mtget mtget; 5034736Swnj /* we depend of the values and order of the MT codes here */ 5044736Swnj static mtops[] = 5054736Swnj {MT_WTM,MT_SFORWF,MT_SREVF,MT_SFORW,MT_SREV,MT_REW,MT_UNLOAD,MT_SENSE}; 5064736Swnj 5074736Swnj switch (cmd) { 5084736Swnj case MTIOCTOP: /* tape operation */ 5094736Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 5104736Swnj u.u_error = EFAULT; 5114736Swnj return; 5124736Swnj } 5134736Swnj switch(mtop.mt_op) { 5144736Swnj case MTWEOF: 5154736Swnj callcount = mtop.mt_count; 5164736Swnj fcount = 1; 5174736Swnj break; 5184736Swnj case MTFSF: case MTBSF: 5194736Swnj callcount = mtop.mt_count; 5204736Swnj fcount = 1; 5214736Swnj break; 5224736Swnj case MTFSR: case MTBSR: 5234736Swnj callcount = 1; 5244736Swnj fcount = mtop.mt_count; 5254736Swnj break; 5264736Swnj case MTREW: case MTOFFL: 5274736Swnj callcount = 1; 5284736Swnj fcount = 1; 5294736Swnj break; 5304736Swnj default: 5314736Swnj u.u_error = ENXIO; 5324736Swnj return; 5334736Swnj } 5344736Swnj if (callcount <= 0 || fcount <= 0) { 5354736Swnj u.u_error = ENXIO; 5364736Swnj return; 5374736Swnj } 5384736Swnj op = mtops[mtop.mt_op]; 5394736Swnj if (op == MT_WTM) 5404736Swnj op |= sc->sc_dens; 5414736Swnj while (--callcount >= 0) { 5424736Swnj register int n; 5434736Swnj 5444736Swnj do { 5454736Swnj n = min(fcount, 0xff); 5464736Swnj mtcommand(dev, op, n); 5474736Swnj fcount -= n; 5484736Swnj } while (fcount); 5494736Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 5504736Swnj bp->b_resid) { 5514736Swnj u.u_error = EIO; 5524736Swnj break; 5534736Swnj } 5544736Swnj if (bp->b_flags&B_ERROR) 5554736Swnj break; 5564736Swnj } 5574736Swnj geterror(bp); 5584736Swnj return; 5594736Swnj case MTIOCGET: 5604736Swnj mtget.mt_erreg = sc->sc_erreg; 5614736Swnj mtget.mt_resid = sc->sc_resid; 5624736Swnj mtcommand(dev, MT_SENSE, 1); /* update drive status */ 5634736Swnj mtget.mt_dsreg = sc->sc_dsreg; 5644736Swnj mtget.mt_type = MT_ISMT; 5654736Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 5664736Swnj u.u_error = EFAULT; 5674736Swnj return; 5684736Swnj default: 5694736Swnj u.u_error = ENXIO; 5704736Swnj } 5714736Swnj } 5724736Swnj 5734736Swnj #define DBSIZE 20 5744736Swnj 5754736Swnj mtdump() 5764736Swnj { 5774736Swnj register struct mba_device *mi; 5784736Swnj register struct mba_regs *mp; 5794736Swnj register struct mtdevice *mtaddr; 5804736Swnj int blk, num; 5814736Swnj int start; 5824736Swnj 5834736Swnj start = 0; 5844736Swnj num = maxfree; 5854736Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5864736Swnj if (mtinfo[0] == 0) 5874736Swnj return (ENXIO); 5884736Swnj mi = phys(mtinfo[0], struct mba_device *); 5894736Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5904736Swnj mp->mba_cr = MBCR_IE; 5914736Swnj mtaddr = (struct mtdevice *)&mp->mba_drv[mi->mi_drive]; 5924736Swnj #ifdef notyet 5934736Swnj mtaddr->mttc = MTTC_PDP11|MTTC_1600BPI; 5944736Swnj mtaddr->mtcs1 = MT_DCLR|MT_GO; 5954736Swnj while (num > 0) { 5964736Swnj blk = num > DBSIZE ? DBSIZE : num; 5974736Swnj mtdwrite(start, blk, mtaddr, mp); 5984736Swnj start += blk; 5994736Swnj num -= blk; 6004736Swnj } 6014736Swnj mteof(mtaddr); 6024736Swnj mteof(mtaddr); 6034736Swnj mtwait(mtaddr); 6044736Swnj if (mtaddr->mtds&MTDS_ERR) 6054736Swnj return (EIO); 6064736Swnj mtaddr->mtcs1 = MT_REW|MT_GO; 6074736Swnj return (0); 6084736Swnj } 6094736Swnj 6104736Swnj mtdwrite(dbuf, num, mtaddr, mp) 6114736Swnj register dbuf, num; 6124736Swnj register struct mtdevice *mtaddr; 6134736Swnj struct mba_regs *mp; 6144736Swnj { 6154736Swnj register struct pte *io; 6164736Swnj register int i; 6174736Swnj 6184736Swnj mtwait(mtaddr); 6194736Swnj io = mp->mba_map; 6204736Swnj for (i = 0; i < num; i++) 6214736Swnj *(int *)io++ = dbuf++ | PG_V; 6224736Swnj mtaddr->mtfc = -(num*NBPG); 6234736Swnj mp->mba_sr = -1; 6244736Swnj mp->mba_bcr = -(num*NBPG); 6254736Swnj mp->mba_var = 0; 6264736Swnj mtaddr->mtcs1 = MT_WCOM|MT_GO; 6274736Swnj } 6284736Swnj 6294736Swnj mtwait(mtaddr) 6304736Swnj struct mtdevice *mtaddr; 6314736Swnj { 6324736Swnj register s; 6334736Swnj 6344736Swnj do 6354736Swnj s = mtaddr->mtds; 6364736Swnj while ((s & MTDS_DRY) == 0); 6374736Swnj } 6384736Swnj 6394736Swnj mteof(mtaddr) 6404736Swnj struct mtdevice *mtaddr; 6414736Swnj { 6424736Swnj 6434736Swnj mtwait(mtaddr); 6444736Swnj mtaddr->mtcs1 = MT_WEOF|MT_GO; 6454736Swnj #endif notyet 6464736Swnj } 6474736Swnj #endif 648