1*2687Swnj /* mbavar.h 4.9 81/02/25 */ 260Sbill 360Sbill /* 460Sbill * VAX Massbus adapter registers 560Sbill */ 660Sbill 72388Swnj struct mba_regs 82332Swnj { 92388Swnj int mba_csr; /* configuration register */ 102388Swnj int mba_cr; /* control register */ 112388Swnj int mba_sr; /* status register */ 122388Swnj int mba_var; /* virtual address register */ 132388Swnj int mba_bcr; /* byte count register */ 142388Swnj int mba_dr; 152388Swnj int mba_pad1[250]; 162388Swnj struct mba_drv { /* per drive registers */ 172388Swnj int mbd_cs1; /* control status */ 182388Swnj int mbd_ds; /* drive status */ 192388Swnj int mbd_er1; /* error register */ 202388Swnj int mbd_mr1; /* maintenance register */ 212388Swnj int mbd_as; /* attention status */ 222388Swnj int mbd_da; /* desired address (disks) */ 232388Swnj #define mbd_fc mbd_da /* frame count (tapes) */ 242388Swnj int mbd_dt; /* drive type */ 252388Swnj int mbd_la; /* look ahead (disks) */ 262388Swnj #define mbd_ck mbd_la /* ??? (tapes) */ 272388Swnj int mbd_sn; /* serial number */ 282388Swnj int mbd_of; /* ??? */ 292388Swnj #define mbd_tc mbd_of /* ??? */ 302388Swnj int mbd_fill[22]; 312388Swnj } mba_drv[8]; 322388Swnj struct pte mba_map[256]; /* io space virtual map */ 332388Swnj int mba_pad2[256*5]; /* to size of a nexus */ 342332Swnj }; 352388Swnj 362332Swnj /* 372388Swnj * Bits in mba_cr 382332Swnj */ 392388Swnj #define MBAINIT 0x1 /* init mba */ 402388Swnj #define MBAIE 0x4 /* enable mba interrupts */ 412388Swnj 422388Swnj /* 432388Swnj * Bits in mba_sr 442388Swnj */ 452388Swnj #define MBS_DTBUSY 0x80000000 /* data transfer busy */ 462388Swnj #define MBS_NRCONF 0x40000000 /* no response confirmation */ 472388Swnj #define MBS_CRD 0x20000000 /* corrected read data */ 482388Swnj #define MBS_CBHUNG 0x00800000 /* control bus hung */ 492388Swnj #define MBS_PGE 0x00080000 /* programming error */ 502388Swnj #define MBS_NED 0x00040000 /* non-existant drive */ 512388Swnj #define MBS_MCPE 0x00020000 /* massbus control parity error */ 522388Swnj #define MBS_ATTN 0x00010000 /* attention from massbus */ 532388Swnj #define MBS_SPE 0x00004000 /* silo parity error */ 542388Swnj #define MBS_DTCMP 0x00002000 /* data transfer completed */ 552388Swnj #define MBS_DTABT 0x00001000 /* data transfer aborted */ 562388Swnj #define MBS_DLT 0x00000800 /* data late */ 572388Swnj #define MBS_WCKUP 0x00000400 /* write check upper */ 582388Swnj #define MBS_WCKLWR 0x00000200 /* write check lower */ 592388Swnj #define MBS_MXF 0x00000100 /* miss transfer error */ 602388Swnj #define MBS_MBEXC 0x00000080 /* massbus exception */ 612388Swnj #define MBS_MDPE 0x00000040 /* massbus data parity error */ 622388Swnj #define MBS_MAPPE 0x00000020 /* page frame map parity error */ 632388Swnj #define MBS_INVMAP 0x00000010 /* invalid map */ 642388Swnj #define MBS_ERRCONF 0x00000008 /* error confirmation */ 652388Swnj #define MBS_RDS 0x00000004 /* read data substitute */ 662388Swnj #define MBS_ISTIMO 0x00000002 /* interface sequence timeout */ 672388Swnj #define MBS_RDTIMO 0x00000001 /* read data timeout */ 682388Swnj 69*2687Swnj #define MBASR_BITS \ 70*2687Swnj "\20\40DTBUSY\37NRCONF\36CRD\30CBHUNG\24PGE\23NED\22MCPE\21ATTN\ 71*2687Swnj \17SPE\16DTCMP\15DTABT\14DLT\13WCKUP\12WCKLWR\11MXF\10MBEXC\7MDPE\ 72*2687Swnj \6MAPPE\5INVMAP\4ERRCONF\3RDS\2ISTIMO\1RDTIMO" 732388Swnj #define MBAEBITS (~(MBS_DTBUSY|MBS_CRD|MBS_ATTN|MBS_DTCMP)) 74*2687Swnj extern char mbasr_bits[]; 752388Swnj 762388Swnj /* 772388Swnj * Commands for mbd_cs1 782388Swnj */ 792388Swnj #define MBD_WCOM 0x30 802388Swnj #define MBD_RCOM 0x38 812388Swnj #define MBD_GO 0x1 822388Swnj 832388Swnj /* 842388Swnj * Bits in mbd_ds. 852388Swnj */ 862388Swnj #define MBD_DRY 0x80 /* drive ready */ 872388Swnj #define MBD_MOL 0x1000 /* medium on line */ 882388Swnj #define MBD_DPR 0x100 /* drive present */ 892388Swnj #define MBD_ERR 0x4000 /* error in drive */ 902388Swnj 912388Swnj /* 922388Swnj * Bits in mbd_dt 932388Swnj */ 942332Swnj #define MBDT_NSA 0x8000 /* not sector addressible */ 952332Swnj #define MBDT_TAP 0x4000 /* is a tape */ 962332Swnj #define MBDT_MOH 0x2000 /* moving head */ 972332Swnj #define MBDT_7CH 0x1000 /* 7 channel */ 982332Swnj #define MBDT_DRQ 0x800 /* drive request required */ 992332Swnj #define MBDT_SPR 0x400 /* slave present */ 1002332Swnj 1012332Swnj #define MBDT_TYPE 0x1ff 1022332Swnj #define MBDT_MASK (MBDT_NSA|MBDT_TAP|MBDT_TYPE) 1032332Swnj 1042388Swnj /* type codes for disk drives */ 1052332Swnj #define MBDT_RP04 020 1062332Swnj #define MBDT_RP05 021 1072332Swnj #define MBDT_RP06 022 1082332Swnj #define MBDT_RP07 042 1092332Swnj #define MBDT_RM03 024 1102332Swnj #define MBDT_RM05 027 1112332Swnj #define MBDT_RM80 026 1122332Swnj 1132388Swnj /* type codes for tape drives */ 1142332Swnj #define MBDT_TM03 050 1152332Swnj #define MBDT_TE16 051 1162332Swnj #define MBDT_TU45 052 1172332Swnj #define MBDT_TU77 054 1182388Swnj #define MBDT_TU78 0140 /* can't handle these (yet) */ 1192332Swnj 1202332Swnj /* 1212388Swnj * Each driver has an array of pointers to these structures, one for 1222388Swnj * each device it is willing to handle. At bootstrap time, the 1232388Swnj * driver tables are filled in; 1242332Swnj */ 1252388Swnj struct mba_info { 1262388Swnj struct mba_driver *mi_driver; 1272388Swnj short mi_name; /* two character generic name */ 1282388Swnj short mi_unit; /* unit number to the system */ 1292388Swnj short mi_mbanum; /* the mba it is on */ 1302388Swnj short mi_drive; /* controller on mba */ 1312388Swnj short mi_slave; /* slave to controller (TM03/TU16) */ 1322547Swnj short mi_dk; /* driver number for iostat */ 1332388Swnj short mi_alive; /* device exists */ 1342388Swnj short mi_type; /* driver specific unit type */ 1352388Swnj struct buf mi_tab; /* head of queue for this device */ 1362388Swnj struct mba_info *mi_forw; 1372388Swnj /* we could compute these every time, but hereby save time */ 1382388Swnj struct mba_regs *mi_mba; 1392388Swnj struct mba_drv *mi_drv; 1402388Swnj struct mba_hd *mi_hd; 1412388Swnj }; 1422332Swnj 1432388Swnj /* 1442388Swnj * The initialization routine uses the information in the mbinit table 1452388Swnj * to initialize the drive type routines in the drivers and the 1462388Swnj * mbahd array summarizing which devices are hooked to which massbus slots. 1472388Swnj */ 1482388Swnj struct mba_hd { 1492388Swnj short mh_active; 1502612Swnj short mh_ndrive; 1512388Swnj struct mba_regs *mh_mba; /* virt addr of mba */ 1522388Swnj struct mba_regs *mh_physmba; /* phys addr of mba */ 1532388Swnj struct mba_info *mh_mbip[8]; /* what is attached */ 1542388Swnj struct mba_info *mh_actf; /* head of queue to transfer */ 1552388Swnj struct mba_info *mh_actl; /* tail of queue to transfer */ 1562388Swnj } mba_hd[4]; 1572388Swnj /* 1582388Swnj * Values for flags; normally MH_NOSEEK will be set when there is 1592388Swnj * only a single drive on an massbus. 1602388Swnj */ 1612388Swnj #define MH_NOSEEK 1 1622388Swnj #define MH_NOSEARCH 2 1632332Swnj 1642388Swnj /* 1652388Swnj * Each massbus driver defines entries for a set of routines 1662388Swnj * as well as an array of types which are acceptable to it. 1672388Swnj */ 1682388Swnj struct mba_driver { 1692388Swnj int (*md_dkinit)(); /* setup dk info (mspw) */ 1702388Swnj int (*md_ustart)(); /* unit start routine */ 1712388Swnj int (*md_start)(); /* setup a data transfer */ 1722388Swnj int (*md_dtint)(); /* data transfer complete */ 1732388Swnj int (*md_ndint)(); /* non-data transfer interrupt */ 1742388Swnj short *md_type; /* array of drive type codes */ 1752388Swnj struct mba_info **md_info; /* backpointers to mbinit structs */ 17660Sbill }; 17760Sbill 1782388Swnj /* 1792388Swnj * Possible return values from unit start routines. 1802388Swnj */ 1812388Swnj #define MBU_NEXT 0 /* skip to next operation */ 1822388Swnj #define MBU_BUSY 1 /* dual port busy; wait for intr */ 1832388Swnj #define MBU_STARTED 2 /* non-data transfer started */ 1842388Swnj #define MBU_DODATA 3 /* data transfer ready; start mba */ 18560Sbill 1862388Swnj /* 1872388Swnj * Possible return values from data transfer interrupt handling routines 1882388Swnj */ 1892388Swnj #define MBD_DONE 0 /* data transfer complete */ 1902388Swnj #define MBD_RETRY 1 /* error occurred, please retry */ 1912388Swnj #define MBD_RESTARTED 2 /* driver restarted i/o itself */ 19260Sbill 1932388Swnj /* 1942388Swnj * Possible return values from non-data-transfer interrupt handling routines 1952388Swnj */ 1962388Swnj #define MBN_DONE 0 /* non-data transfer complete */ 1972388Swnj #define MBN_RETRY 1 /* failed; retry the operation */ 19860Sbill 1992388Swnj /* 2002388Swnj * Clear attention status for specified drive. 2012388Swnj */ 2022388Swnj #define mbclrattn(mi) ((mi)->mi_mba->mba_drv[0].mbd_as = 1 << (mi)->mi_drive) 2032547Swnj 2042547Swnj /* 2052547Swnj * Kernel definitions related to mba. 2062547Swnj */ 2072547Swnj #ifdef KERNEL 2082547Swnj extern Xmba0int(), Xmba1int(), Xmba2int(), Xmba3int(); 2092547Swnj extern struct mba_info mbinit[]; /* blanks for filling mba_info */ 2102547Swnj int nummba; 2112547Swnj #endif 212