xref: /csrg-svn/sys/vax/mba/mbavar.h (revision 2547)
1*2547Swnj /*	mbavar.h	4.6	02/19/81	*/
260Sbill 
360Sbill /*
460Sbill  * VAX Massbus adapter registers
560Sbill  */
660Sbill 
72388Swnj struct mba_regs
82332Swnj {
92388Swnj 	int	mba_csr;		/* configuration register */
102388Swnj 	int	mba_cr;			/* control register */
112388Swnj 	int	mba_sr;			/* status register */
122388Swnj 	int	mba_var;		/* virtual address register */
132388Swnj 	int	mba_bcr;		/* byte count register */
142388Swnj 	int	mba_dr;
152388Swnj 	int	mba_pad1[250];
162388Swnj 	struct mba_drv {		/* per drive registers */
172388Swnj 		int	mbd_cs1;		/* control status */
182388Swnj 		int	mbd_ds;			/* drive status */
192388Swnj 		int	mbd_er1;		/* error register */
202388Swnj 		int	mbd_mr1;		/* maintenance register */
212388Swnj 		int	mbd_as;			/* attention status */
222388Swnj 		int	mbd_da;			/* desired address (disks) */
232388Swnj #define	mbd_fc	mbd_da				/* frame count (tapes) */
242388Swnj 		int	mbd_dt;			/* drive type */
252388Swnj 		int	mbd_la;			/* look ahead (disks) */
262388Swnj #define	mbd_ck	mbd_la				/* ??? (tapes) */
272388Swnj 		int	mbd_sn;			/* serial number */
282388Swnj 		int	mbd_of;			/* ??? */
292388Swnj #define	mbd_tc	mbd_of				/* ??? */
302388Swnj 		int	mbd_fill[22];
312388Swnj 	} mba_drv[8];
322388Swnj 	struct	pte mba_map[256];	/* io space virtual map */
332388Swnj 	int	mba_pad2[256*5];	/* to size of a nexus */
342332Swnj };
352388Swnj 
362332Swnj /*
372388Swnj  * Bits in mba_cr
382332Swnj  */
392388Swnj #define	MBAINIT		0x1		/* init mba */
402388Swnj #define	MBAIE		0x4		/* enable mba interrupts */
412388Swnj 
422388Swnj /*
432388Swnj  * Bits in mba_sr
442388Swnj  */
452388Swnj #define	MBS_DTBUSY	0x80000000	/* data transfer busy */
462388Swnj #define	MBS_NRCONF	0x40000000	/* no response confirmation */
472388Swnj #define	MBS_CRD		0x20000000	/* corrected read data */
482388Swnj #define	MBS_CBHUNG	0x00800000	/* control bus hung */
492388Swnj #define	MBS_PGE		0x00080000	/* programming error */
502388Swnj #define	MBS_NED		0x00040000	/* non-existant drive */
512388Swnj #define	MBS_MCPE	0x00020000	/* massbus control parity error */
522388Swnj #define	MBS_ATTN	0x00010000	/* attention from massbus */
532388Swnj #define	MBS_SPE		0x00004000	/* silo parity error */
542388Swnj #define	MBS_DTCMP	0x00002000	/* data transfer completed */
552388Swnj #define	MBS_DTABT	0x00001000	/* data transfer aborted */
562388Swnj #define	MBS_DLT		0x00000800	/* data late */
572388Swnj #define	MBS_WCKUP	0x00000400	/* write check upper */
582388Swnj #define	MBS_WCKLWR	0x00000200	/* write check lower */
592388Swnj #define	MBS_MXF		0x00000100	/* miss transfer error */
602388Swnj #define	MBS_MBEXC	0x00000080	/* massbus exception */
612388Swnj #define	MBS_MDPE	0x00000040	/* massbus data parity error */
622388Swnj #define	MBS_MAPPE	0x00000020	/* page frame map parity error */
632388Swnj #define	MBS_INVMAP	0x00000010	/* invalid map */
642388Swnj #define	MBS_ERRCONF	0x00000008	/* error confirmation */
652388Swnj #define	MBS_RDS		0x00000004	/* read data substitute */
662388Swnj #define	MBS_ISTIMO	0x00000002	/* interface sequence timeout */
672388Swnj #define	MBS_RDTIMO	0x00000001	/* read data timeout */
682388Swnj 
692388Swnj #define MBAEBITS	(~(MBS_DTBUSY|MBS_CRD|MBS_ATTN|MBS_DTCMP))
702388Swnj 
712388Swnj /*
722388Swnj  * Commands for mbd_cs1
732388Swnj  */
742388Swnj #define	MBD_WCOM	0x30
752388Swnj #define	MBD_RCOM	0x38
762388Swnj #define	MBD_GO		0x1
772388Swnj 
782388Swnj /*
792388Swnj  * Bits in mbd_ds.
802388Swnj  */
812388Swnj #define	MBD_DRY		0x80		/* drive ready */
822388Swnj #define	MBD_MOL		0x1000		/* medium on line */
832388Swnj #define	MBD_DPR		0x100		/* drive present */
842388Swnj #define	MBD_ERR		0x4000		/* error in drive */
852388Swnj 
862388Swnj /*
872388Swnj  * Bits in mbd_dt
882388Swnj  */
892332Swnj #define	MBDT_NSA	0x8000		/* not sector addressible */
902332Swnj #define	MBDT_TAP	0x4000		/* is a tape */
912332Swnj #define	MBDT_MOH	0x2000		/* moving head */
922332Swnj #define	MBDT_7CH	0x1000		/* 7 channel */
932332Swnj #define	MBDT_DRQ	0x800		/* drive request required */
942332Swnj #define	MBDT_SPR	0x400		/* slave present */
952332Swnj 
962332Swnj #define	MBDT_TYPE	0x1ff
972332Swnj #define	MBDT_MASK	(MBDT_NSA|MBDT_TAP|MBDT_TYPE)
982332Swnj 
992388Swnj /* type codes for disk drives */
1002332Swnj #define	MBDT_RP04	020
1012332Swnj #define	MBDT_RP05	021
1022332Swnj #define	MBDT_RP06	022
1032332Swnj #define	MBDT_RP07	042
1042332Swnj #define	MBDT_RM03	024
1052332Swnj #define	MBDT_RM05	027
1062332Swnj #define	MBDT_RM80	026
1072332Swnj 
1082388Swnj /* type codes for tape drives */
1092332Swnj #define	MBDT_TM03	050
1102332Swnj #define	MBDT_TE16	051
1112332Swnj #define	MBDT_TU45	052
1122332Swnj #define	MBDT_TU77	054
1132388Swnj #define	MBDT_TU78	0140		/* can't handle these (yet) */
1142332Swnj 
1152332Swnj /*
1162388Swnj  * Each driver has an array of pointers to these structures, one for
1172388Swnj  * each device it is willing to handle.  At bootstrap time, the
1182388Swnj  * driver tables are filled in;
1192332Swnj  */
1202388Swnj struct	mba_info {
1212388Swnj 	struct	mba_driver *mi_driver;
1222388Swnj 	short	mi_name;	/* two character generic name */
1232388Swnj 	short	mi_unit;	/* unit number to the system */
1242388Swnj 	short	mi_mbanum;	/* the mba it is on */
1252388Swnj 	short	mi_drive;	/* controller on mba */
1262388Swnj 	short	mi_slave;	/* slave to controller (TM03/TU16) */
127*2547Swnj 	short	mi_dk;		/* driver number for iostat */
1282388Swnj 	short	mi_alive;	/* device exists */
1292388Swnj 	short	mi_type;	/* driver specific unit type */
1302388Swnj 	struct	buf mi_tab;	/* head of queue for this device */
1312388Swnj 	struct	mba_info *mi_forw;
1322388Swnj /* we could compute these every time, but hereby save time */
1332388Swnj 	struct	mba_regs *mi_mba;
1342388Swnj 	struct	mba_drv *mi_drv;
1352388Swnj 	struct	mba_hd *mi_hd;
1362388Swnj };
1372332Swnj 
1382388Swnj /*
1392388Swnj  * The initialization routine uses the information in the mbinit table
1402388Swnj  * to initialize the drive type routines in the drivers and the
1412388Swnj  * mbahd array summarizing which devices are hooked to which massbus slots.
1422388Swnj  */
1432388Swnj struct	mba_hd {
1442388Swnj 	short	mh_active;
1452388Swnj 	short	mh_flags;
1462388Swnj 	struct	mba_regs *mh_mba;	/* virt addr of mba */
1472388Swnj 	struct	mba_regs *mh_physmba;	/* phys addr of mba */
1482388Swnj 	struct	mba_info *mh_mbip[8];	/* what is attached */
1492388Swnj 	struct	mba_info *mh_actf;	/* head of queue to transfer */
1502388Swnj 	struct	mba_info *mh_actl;	/* tail of queue to transfer */
1512388Swnj } mba_hd[4];
1522388Swnj /*
1532388Swnj  * Values for flags; normally MH_NOSEEK will be set when there is
1542388Swnj  * only a single drive on an massbus.
1552388Swnj  */
1562388Swnj #define	MH_NOSEEK	1
1572388Swnj #define	MH_NOSEARCH	2
1582332Swnj 
1592388Swnj /*
1602388Swnj  * Each massbus driver defines entries for a set of routines
1612388Swnj  * as well as an array of types which are acceptable to it.
1622388Swnj  */
1632388Swnj struct mba_driver {
1642388Swnj 	int	(*md_dkinit)();		/* setup dk info (mspw) */
1652388Swnj 	int	(*md_ustart)();		/* unit start routine */
1662388Swnj 	int	(*md_start)();		/* setup a data transfer */
1672388Swnj 	int	(*md_dtint)();		/* data transfer complete */
1682388Swnj 	int	(*md_ndint)();		/* non-data transfer interrupt */
1692388Swnj 	short	*md_type;		/* array of drive type codes */
1702388Swnj 	struct	mba_info **md_info;	/* backpointers to mbinit structs */
17160Sbill };
17260Sbill 
1732388Swnj /*
1742388Swnj  * Possible return values from unit start routines.
1752388Swnj  */
1762388Swnj #define	MBU_NEXT	0		/* skip to next operation */
1772388Swnj #define	MBU_BUSY	1		/* dual port busy; wait for intr */
1782388Swnj #define	MBU_STARTED	2		/* non-data transfer started */
1792388Swnj #define	MBU_DODATA	3		/* data transfer ready; start mba */
18060Sbill 
1812388Swnj /*
1822388Swnj  * Possible return values from data transfer interrupt handling routines
1832388Swnj  */
1842388Swnj #define	MBD_DONE	0		/* data transfer complete */
1852388Swnj #define	MBD_RETRY	1		/* error occurred, please retry */
1862388Swnj #define	MBD_RESTARTED	2		/* driver restarted i/o itself */
18760Sbill 
1882388Swnj /*
1892388Swnj  * Possible return values from non-data-transfer interrupt handling routines
1902388Swnj  */
1912388Swnj #define	MBN_DONE	0		/* non-data transfer complete */
1922388Swnj #define	MBN_RETRY	1		/* failed; retry the operation */
19360Sbill 
1942388Swnj /*
1952388Swnj  * Clear attention status for specified drive.
1962388Swnj  */
1972388Swnj #define	mbclrattn(mi)	((mi)->mi_mba->mba_drv[0].mbd_as = 1 << (mi)->mi_drive)
198*2547Swnj 
199*2547Swnj /*
200*2547Swnj  * Kernel definitions related to mba.
201*2547Swnj  */
202*2547Swnj #ifdef KERNEL
203*2547Swnj extern	Xmba0int(), Xmba1int(), Xmba2int(), Xmba3int();
204*2547Swnj extern	struct	mba_info mbinit[];	/* blanks for filling mba_info */
205*2547Swnj int	nummba;
206*2547Swnj #endif
207