xref: /csrg-svn/sys/vax/mba/mbavar.h (revision 2388)
1*2388Swnj /*	mbavar.h	4.4	02/08/81	*/
260Sbill 
360Sbill /*
460Sbill  * VAX Massbus adapter registers
560Sbill  */
660Sbill 
7*2388Swnj struct mba_regs
82332Swnj {
9*2388Swnj 	int	mba_csr;		/* configuration register */
10*2388Swnj 	int	mba_cr;			/* control register */
11*2388Swnj 	int	mba_sr;			/* status register */
12*2388Swnj 	int	mba_var;		/* virtual address register */
13*2388Swnj 	int	mba_bcr;		/* byte count register */
14*2388Swnj 	int	mba_dr;
15*2388Swnj 	int	mba_pad1[250];
16*2388Swnj 	struct mba_drv {		/* per drive registers */
17*2388Swnj 		int	mbd_cs1;		/* control status */
18*2388Swnj 		int	mbd_ds;			/* drive status */
19*2388Swnj 		int	mbd_er1;		/* error register */
20*2388Swnj 		int	mbd_mr1;		/* maintenance register */
21*2388Swnj 		int	mbd_as;			/* attention status */
22*2388Swnj 		int	mbd_da;			/* desired address (disks) */
23*2388Swnj #define	mbd_fc	mbd_da				/* frame count (tapes) */
24*2388Swnj 		int	mbd_dt;			/* drive type */
25*2388Swnj 		int	mbd_la;			/* look ahead (disks) */
26*2388Swnj #define	mbd_ck	mbd_la				/* ??? (tapes) */
27*2388Swnj 		int	mbd_sn;			/* serial number */
28*2388Swnj 		int	mbd_of;			/* ??? */
29*2388Swnj #define	mbd_tc	mbd_of				/* ??? */
30*2388Swnj 		int	mbd_fill[22];
31*2388Swnj 	} mba_drv[8];
32*2388Swnj 	struct	pte mba_map[256];	/* io space virtual map */
33*2388Swnj 	int	mba_pad2[256*5];	/* to size of a nexus */
342332Swnj };
35*2388Swnj 
362332Swnj /*
37*2388Swnj  * Bits in mba_cr
382332Swnj  */
39*2388Swnj #define	MBAINIT		0x1		/* init mba */
40*2388Swnj #define	MBAIE		0x4		/* enable mba interrupts */
41*2388Swnj 
42*2388Swnj /*
43*2388Swnj  * Bits in mba_sr
44*2388Swnj  */
45*2388Swnj #define	MBS_DTBUSY	0x80000000	/* data transfer busy */
46*2388Swnj #define	MBS_NRCONF	0x40000000	/* no response confirmation */
47*2388Swnj #define	MBS_CRD		0x20000000	/* corrected read data */
48*2388Swnj #define	MBS_CBHUNG	0x00800000	/* control bus hung */
49*2388Swnj #define	MBS_PGE		0x00080000	/* programming error */
50*2388Swnj #define	MBS_NED		0x00040000	/* non-existant drive */
51*2388Swnj #define	MBS_MCPE	0x00020000	/* massbus control parity error */
52*2388Swnj #define	MBS_ATTN	0x00010000	/* attention from massbus */
53*2388Swnj #define	MBS_SPE		0x00004000	/* silo parity error */
54*2388Swnj #define	MBS_DTCMP	0x00002000	/* data transfer completed */
55*2388Swnj #define	MBS_DTABT	0x00001000	/* data transfer aborted */
56*2388Swnj #define	MBS_DLT		0x00000800	/* data late */
57*2388Swnj #define	MBS_WCKUP	0x00000400	/* write check upper */
58*2388Swnj #define	MBS_WCKLWR	0x00000200	/* write check lower */
59*2388Swnj #define	MBS_MXF		0x00000100	/* miss transfer error */
60*2388Swnj #define	MBS_MBEXC	0x00000080	/* massbus exception */
61*2388Swnj #define	MBS_MDPE	0x00000040	/* massbus data parity error */
62*2388Swnj #define	MBS_MAPPE	0x00000020	/* page frame map parity error */
63*2388Swnj #define	MBS_INVMAP	0x00000010	/* invalid map */
64*2388Swnj #define	MBS_ERRCONF	0x00000008	/* error confirmation */
65*2388Swnj #define	MBS_RDS		0x00000004	/* read data substitute */
66*2388Swnj #define	MBS_ISTIMO	0x00000002	/* interface sequence timeout */
67*2388Swnj #define	MBS_RDTIMO	0x00000001	/* read data timeout */
68*2388Swnj 
69*2388Swnj #define MBAEBITS	(~(MBS_DTBUSY|MBS_CRD|MBS_ATTN|MBS_DTCMP))
70*2388Swnj 
71*2388Swnj /*
72*2388Swnj  * Commands for mbd_cs1
73*2388Swnj  */
74*2388Swnj #define	MBD_WCOM	0x30
75*2388Swnj #define	MBD_RCOM	0x38
76*2388Swnj #define	MBD_GO		0x1
77*2388Swnj 
78*2388Swnj /*
79*2388Swnj  * Bits in mbd_ds.
80*2388Swnj  */
81*2388Swnj #define	MBD_DRY		0x80		/* drive ready */
82*2388Swnj #define	MBD_MOL		0x1000		/* medium on line */
83*2388Swnj #define	MBD_DPR		0x100		/* drive present */
84*2388Swnj #define	MBD_ERR		0x4000		/* error in drive */
85*2388Swnj 
86*2388Swnj /*
87*2388Swnj  * Bits in mbd_dt
88*2388Swnj  */
892332Swnj #define	MBDT_NSA	0x8000		/* not sector addressible */
902332Swnj #define	MBDT_TAP	0x4000		/* is a tape */
912332Swnj #define	MBDT_MOH	0x2000		/* moving head */
922332Swnj #define	MBDT_7CH	0x1000		/* 7 channel */
932332Swnj #define	MBDT_DRQ	0x800		/* drive request required */
942332Swnj #define	MBDT_SPR	0x400		/* slave present */
952332Swnj 
962332Swnj #define	MBDT_TYPE	0x1ff
972332Swnj #define	MBDT_MASK	(MBDT_NSA|MBDT_TAP|MBDT_TYPE)
982332Swnj 
99*2388Swnj /* type codes for disk drives */
1002332Swnj #define	MBDT_RP04	020
1012332Swnj #define	MBDT_RP05	021
1022332Swnj #define	MBDT_RP06	022
1032332Swnj #define	MBDT_RP07	042
1042332Swnj #define	MBDT_RM03	024
1052332Swnj #define	MBDT_RM05	027
1062332Swnj #define	MBDT_RM80	026
1072332Swnj 
108*2388Swnj /* type codes for tape drives */
1092332Swnj #define	MBDT_TM03	050
1102332Swnj #define	MBDT_TE16	051
1112332Swnj #define	MBDT_TU45	052
1122332Swnj #define	MBDT_TU77	054
113*2388Swnj #define	MBDT_TU78	0140		/* can't handle these (yet) */
1142332Swnj 
1152332Swnj /*
116*2388Swnj  * Each driver has an array of pointers to these structures, one for
117*2388Swnj  * each device it is willing to handle.  At bootstrap time, the
118*2388Swnj  * driver tables are filled in;
1192332Swnj  */
120*2388Swnj struct	mba_info {
121*2388Swnj 	struct	mba_driver *mi_driver;
122*2388Swnj 	short	mi_name;	/* two character generic name */
123*2388Swnj 	short	mi_unit;	/* unit number to the system */
124*2388Swnj 	short	mi_mbanum;	/* the mba it is on */
125*2388Swnj 	short	mi_drive;	/* controller on mba */
126*2388Swnj 	short	mi_slave;	/* slave to controller (TM03/TU16) */
127*2388Swnj 	short	mi_alive;	/* device exists */
128*2388Swnj 	short	mi_type;	/* driver specific unit type */
129*2388Swnj 	short	mi_dk;		/* driver number for iostat */
130*2388Swnj 	struct	buf mi_tab;	/* head of queue for this device */
131*2388Swnj 	struct	mba_info *mi_forw;
132*2388Swnj /* we could compute these every time, but hereby save time */
133*2388Swnj 	struct	mba_regs *mi_mba;
134*2388Swnj 	struct	mba_drv *mi_drv;
135*2388Swnj 	struct	mba_hd *mi_hd;
136*2388Swnj };
1372332Swnj 
138*2388Swnj /*
139*2388Swnj  * The initialization routine uses the information in the mbinit table
140*2388Swnj  * to initialize the drive type routines in the drivers and the
141*2388Swnj  * mbahd array summarizing which devices are hooked to which massbus slots.
142*2388Swnj  */
143*2388Swnj struct	mba_hd {
144*2388Swnj 	short	mh_active;
145*2388Swnj 	short	mh_flags;
146*2388Swnj 	struct	mba_regs *mh_mba;	/* virt addr of mba */
147*2388Swnj 	struct	mba_regs *mh_physmba;	/* phys addr of mba */
148*2388Swnj 	struct	mba_info *mh_mbip[8];	/* what is attached */
149*2388Swnj 	struct	mba_info *mh_actf;	/* head of queue to transfer */
150*2388Swnj 	struct	mba_info *mh_actl;	/* tail of queue to transfer */
151*2388Swnj } mba_hd[4];
152*2388Swnj #ifdef KERNEL
153*2388Swnj extern	struct	mba_info mbinit[];	/* blanks for filling mba_info */
154*2388Swnj #endif
155*2388Swnj /*
156*2388Swnj  * Values for flags; normally MH_NOSEEK will be set when there is
157*2388Swnj  * only a single drive on an massbus.
158*2388Swnj  */
159*2388Swnj #define	MH_NOSEEK	1
160*2388Swnj #define	MH_NOSEARCH	2
1612332Swnj 
162*2388Swnj /*
163*2388Swnj  * Each massbus driver defines entries for a set of routines
164*2388Swnj  * as well as an array of types which are acceptable to it.
165*2388Swnj  */
166*2388Swnj struct mba_driver {
167*2388Swnj 	int	(*md_dkinit)();		/* setup dk info (mspw) */
168*2388Swnj 	int	(*md_ustart)();		/* unit start routine */
169*2388Swnj 	int	(*md_start)();		/* setup a data transfer */
170*2388Swnj 	int	(*md_dtint)();		/* data transfer complete */
171*2388Swnj 	int	(*md_ndint)();		/* non-data transfer interrupt */
172*2388Swnj 	short	*md_type;		/* array of drive type codes */
173*2388Swnj 	struct	mba_info **md_info;	/* backpointers to mbinit structs */
17460Sbill };
17560Sbill 
176*2388Swnj /*
177*2388Swnj  * Possible return values from unit start routines.
178*2388Swnj  */
179*2388Swnj #define	MBU_NEXT	0		/* skip to next operation */
180*2388Swnj #define	MBU_BUSY	1		/* dual port busy; wait for intr */
181*2388Swnj #define	MBU_STARTED	2		/* non-data transfer started */
182*2388Swnj #define	MBU_DODATA	3		/* data transfer ready; start mba */
18360Sbill 
184*2388Swnj /*
185*2388Swnj  * Possible return values from data transfer interrupt handling routines
186*2388Swnj  */
187*2388Swnj #define	MBD_DONE	0		/* data transfer complete */
188*2388Swnj #define	MBD_RETRY	1		/* error occurred, please retry */
189*2388Swnj #define	MBD_RESTARTED	2		/* driver restarted i/o itself */
19060Sbill 
191*2388Swnj /*
192*2388Swnj  * Possible return values from non-data-transfer interrupt handling routines
193*2388Swnj  */
194*2388Swnj #define	MBN_DONE	0		/* non-data transfer complete */
195*2388Swnj #define	MBN_RETRY	1		/* failed; retry the operation */
19660Sbill 
197*2388Swnj /*
198*2388Swnj  * Clear attention status for specified drive.
199*2388Swnj  */
200*2388Swnj #define	mbclrattn(mi)	((mi)->mi_mba->mba_drv[0].mbd_as = 1 << (mi)->mi_drive)
201