xref: /csrg-svn/sys/vax/mba/mba.c (revision 3182)
1*3182Swnj /*	mba.c	4.19	81/03/10	*/
228Sbill 
32704Swnj #include "mba.h"
42704Swnj #if NMBA > 0
52383Swnj /*
63095Swnj  * Massbus driver, arbitrates a massbus among attached devices.
72383Swnj  */
828Sbill #include "../h/param.h"
92383Swnj #include "../h/systm.h"
102383Swnj #include "../h/dk.h"
1128Sbill #include "../h/buf.h"
1228Sbill #include "../h/conf.h"
1328Sbill #include "../h/dir.h"
1428Sbill #include "../h/user.h"
1528Sbill #include "../h/proc.h"
162383Swnj #include "../h/map.h"
1728Sbill #include "../h/pte.h"
182981Swnj #include "../h/mbareg.h"
192981Swnj #include "../h/mbavar.h"
2028Sbill #include "../h/mtpr.h"
2128Sbill #include "../h/vm.h"
2228Sbill 
233095Swnj char	mbsr_bits[] = MBSR_BITS;
2428Sbill /*
252383Swnj  * Start activity on a massbus device.
262981Swnj  * We are given the device's mba_device structure and activate
272383Swnj  * the device via the unit start routine.  The unit start
282383Swnj  * routine may indicate that it is finished (e.g. if the operation
292383Swnj  * was a ``sense'' on a tape drive), that the (multi-ported) unit
302383Swnj  * is busy (we will get an interrupt later), that it started the
312383Swnj  * unit (e.g. for a non-data transfer operation), or that it has
322383Swnj  * set up a data transfer operation and we should start the massbus adaptor.
3328Sbill  */
342383Swnj mbustart(mi)
352981Swnj 	register struct mba_device *mi;
362383Swnj {
372383Swnj 	register struct buf *bp;	/* i/o operation at head of queue */
382383Swnj 	register struct mba_hd *mhp;	/* header for mba device is on */
3928Sbill 
402383Swnj loop:
412383Swnj 	/*
422383Swnj 	 * Get the first thing to do off device queue.
432383Swnj 	 */
442383Swnj 	bp = mi->mi_tab.b_actf;
452383Swnj 	if (bp == NULL)
462383Swnj 		return;
472383Swnj 	/*
482383Swnj 	 * Let the drivers unit start routine have at it
492383Swnj 	 * and then process the request further, per its instructions.
502383Swnj 	 */
512383Swnj 	switch ((*mi->mi_driver->md_ustart)(mi)) {
522383Swnj 
532383Swnj 	case MBU_NEXT:		/* request is complete (e.g. ``sense'') */
542383Swnj 		mi->mi_tab.b_active = 0;
552955Swnj 		mi->mi_tab.b_errcnt = 0;
562383Swnj 		mi->mi_tab.b_actf = bp->av_forw;
572383Swnj 		iodone(bp);
582383Swnj 		goto loop;
592383Swnj 
602383Swnj 	case MBU_DODATA:	/* all ready to do data transfer */
612383Swnj 		/*
622981Swnj 		 * Queue the device mba_device structure on the massbus
632383Swnj 		 * mba_hd structure for processing as soon as the
642383Swnj 		 * data path is available.
652383Swnj 		 */
662383Swnj 		mhp = mi->mi_hd;
672383Swnj 		mi->mi_forw = NULL;
682383Swnj 		if (mhp->mh_actf == NULL)
692383Swnj 			mhp->mh_actf = mi;
702383Swnj 		else
712383Swnj 			mhp->mh_actl->mi_forw = mi;
722383Swnj 		mhp->mh_actl = mi;
732383Swnj 		/*
742383Swnj 		 * If data path is idle, start transfer now.
752383Swnj 		 * In any case the device is ``active'' waiting for the
762383Swnj 		 * data to transfer.
772383Swnj 		 */
782893Swnj 		mi->mi_tab.b_active = 1;
792383Swnj 		if (mhp->mh_active == 0)
802383Swnj 			mbstart(mhp);
812383Swnj 		return;
822383Swnj 
832383Swnj 	case MBU_STARTED:	/* driver started a non-data transfer */
842383Swnj 		/*
852383Swnj 		 * Mark device busy during non-data transfer
862383Swnj 		 * and count this as a ``seek'' on the device.
872383Swnj 		 */
88*3182Swnj 		if (mi->mi_dk >= 0) {
892383Swnj 			dk_seek[mi->mi_dk]++;
90*3182Swnj 			dk_busy |= (1 << mi->mi_dk);
91*3182Swnj 		}
922383Swnj 		mi->mi_tab.b_active = 1;
932383Swnj 		return;
942383Swnj 
952383Swnj 	case MBU_BUSY:		/* dual port drive busy */
962383Swnj 		/*
972383Swnj 		 * We mark the device structure so that when an
982383Swnj 		 * interrupt occurs we will know to restart the unit.
992383Swnj 		 */
1002383Swnj 		mi->mi_tab.b_flags |= B_BUSY;
1012383Swnj 		return;
1022383Swnj 
1032383Swnj 	default:
1042383Swnj 		panic("mbustart");
1052383Swnj 	}
1062403Skre }
1072383Swnj 
1082383Swnj /*
1092383Swnj  * Start an i/o operation on the massbus specified by the argument.
1102383Swnj  * We peel the first operation off its queue and insure that the drive
1112383Swnj  * is present and on-line.  We then use the drivers start routine
1122383Swnj  * (if any) to prepare the drive, setup the massbus map for the transfer
1132383Swnj  * and start the transfer.
1142383Swnj  */
1152383Swnj mbstart(mhp)
1162383Swnj 	register struct mba_hd *mhp;
1172383Swnj {
1182981Swnj 	register struct mba_device *mi;
1192383Swnj 	struct buf *bp;
1202383Swnj 	register struct mba_regs *mbp;
1212383Swnj 
1222383Swnj loop:
1232383Swnj 	/*
1242383Swnj 	 * Look for an operation at the front of the queue.
1252383Swnj 	 */
1262955Swnj 	if ((mi = mhp->mh_actf) == NULL) {
1272383Swnj 		return;
1282955Swnj 	}
1292383Swnj 	if ((bp = mi->mi_tab.b_actf) == NULL) {
1302383Swnj 		mhp->mh_actf = mi->mi_forw;
1312383Swnj 		goto loop;
1322383Swnj 	}
1332383Swnj 	/*
1342383Swnj 	 * If this device isn't present and on-line, then
1352383Swnj 	 * we screwed up, and can't really do the operation.
1362383Swnj 	 */
1373095Swnj 	if ((mi->mi_drv->mbd_ds & MBDS_DREADY) != MBDS_DREADY) {
1382981Swnj 		printf("%s%d: not ready\n", mi->mi_driver->md_dname,
1392981Swnj 		    dkunit(bp));
1402383Swnj 		mi->mi_tab.b_actf = bp->av_forw;
1412893Swnj 		mi->mi_tab.b_errcnt = 0;
1422893Swnj 		mi->mi_tab.b_active = 0;
1432383Swnj 		bp->b_flags |= B_ERROR;
1442383Swnj 		iodone(bp);
1452383Swnj 		goto loop;
1462383Swnj 	}
1472383Swnj 	/*
1482383Swnj 	 * We can do the operation; mark the massbus active
1492383Swnj 	 * and let the device start routine setup any necessary
1502383Swnj 	 * device state for the transfer (e.g. desired cylinder, etc
1512383Swnj 	 * on disks).
1522383Swnj 	 */
1532383Swnj 	mhp->mh_active = 1;
1542884Swnj 	if (mi->mi_driver->md_start)
1552383Swnj 		(*mi->mi_driver->md_start)(mi);
1562383Swnj 
1572383Swnj 	/*
1582383Swnj 	 * Setup the massbus control and map registers and start
1592383Swnj 	 * the transfer.
1602383Swnj 	 */
1612383Swnj 	mbp = mi->mi_mba;
1622383Swnj 	mbp->mba_sr = -1;	/* conservative */
1632383Swnj 	mbp->mba_var = mbasetup(mi);
1642383Swnj 	mbp->mba_bcr = -bp->b_bcount;
1652383Swnj 	mi->mi_drv->mbd_cs1 =
1663095Swnj 	    (bp->b_flags & B_READ) ? MB_RCOM|MB_GO : MB_WCOM|MB_GO;
1672383Swnj 	if (mi->mi_dk >= 0) {
1682383Swnj 		dk_busy |= 1 << mi->mi_dk;
1692383Swnj 		dk_xfer[mi->mi_dk]++;
1702383Swnj 		dk_wds[mi->mi_dk] += bp->b_bcount >> 6;
1712383Swnj 	}
1722383Swnj }
1732383Swnj 
1742383Swnj /*
1752383Swnj  * Take an interrupt off of massbus mbanum,
1762383Swnj  * and dispatch to drivers as appropriate.
1772383Swnj  */
1782383Swnj mbintr(mbanum)
1792383Swnj 	int mbanum;
1802383Swnj {
1812383Swnj 	register struct mba_hd *mhp = &mba_hd[mbanum];
1822383Swnj 	register struct mba_regs *mbp = mhp->mh_mba;
1832981Swnj 	register struct mba_device *mi;
184420Sbill 	register struct buf *bp;
1852383Swnj 	register int drive;
1862955Swnj 	int mbasr, as;
1872383Swnj 
1882383Swnj 	/*
1892383Swnj 	 * Read out the massbus status register
1902383Swnj 	 * and attention status register and clear
1912383Swnj 	 * the bits in same by writing them back.
1922383Swnj 	 */
1932955Swnj 	mbasr = mbp->mba_sr;
1942955Swnj 	mbp->mba_sr = mbasr;
1952884Swnj #if VAX750
1963095Swnj 	if (mbasr&MBSR_CBHUNG) {
1972930Swnj 		printf("mba%d: control bus hung\n", mbanum);
1982930Swnj 		panic("cbhung");
1992930Swnj 	}
2002884Swnj #endif
2012383Swnj 	/* note: the mbd_as register is shared between drives */
2022955Swnj 	as = mbp->mba_drv[0].mbd_as & 0xff;
2032383Swnj 	mbp->mba_drv[0].mbd_as = as;
2042383Swnj 
2052383Swnj 	/*
2062383Swnj 	 * If the mba was active, process the data transfer
2072383Swnj 	 * complete interrupt; otherwise just process units which
2082383Swnj 	 * are now finished.
2092383Swnj 	 */
2102383Swnj 	if (mhp->mh_active) {
2112383Swnj 		/*
2122383Swnj 		 * Clear attention status for drive whose data
2133095Swnj 		 * transfer related operation completed,
2143095Swnj 		 * and give the dtint driver
2152383Swnj 		 * routine a chance to say what is next.
2162383Swnj 		 */
2172383Swnj 		mi = mhp->mh_actf;
2182383Swnj 		as &= ~(1 << mi->mi_drive);
2192383Swnj 		dk_busy &= ~(1 << mi->mi_dk);
2202383Swnj 		bp = mi->mi_tab.b_actf;
2213095Swnj 		switch ((*mi->mi_driver->md_dtint)(mi, mbasr)) {
2222383Swnj 
2232383Swnj 		case MBD_DONE:		/* all done, for better or worse */
2242383Swnj 			/*
2252383Swnj 			 * Flush request from drive queue.
2262383Swnj 			 */
2272383Swnj 			mi->mi_tab.b_errcnt = 0;
2282383Swnj 			mi->mi_tab.b_actf = bp->av_forw;
2292383Swnj 			iodone(bp);
2302383Swnj 			/* fall into... */
2312383Swnj 		case MBD_RETRY:		/* attempt the operation again */
2322383Swnj 			/*
2332383Swnj 			 * Dequeue data transfer from massbus queue;
2342383Swnj 			 * if there is still a i/o request on the device
2352383Swnj 			 * queue then start the next operation on the device.
2362383Swnj 			 * (Common code for DONE and RETRY).
2372383Swnj 			 */
2382383Swnj 			mhp->mh_active = 0;
2392383Swnj 			mi->mi_tab.b_active = 0;
2402383Swnj 			mhp->mh_actf = mi->mi_forw;
2412383Swnj 			if (mi->mi_tab.b_actf)
2422383Swnj 				mbustart(mi);
2432383Swnj 			break;
2442383Swnj 
2452383Swnj 		case MBD_RESTARTED:	/* driver restarted op (ecc, e.g.)
2462383Swnj 			/*
2472893Swnj 			 * Note that mhp->mh_active is still on.
2482383Swnj 			 */
2492383Swnj 			break;
2502383Swnj 
2512383Swnj 		default:
2522884Swnj 			panic("mbintr");
2532383Swnj 		}
2542383Swnj 	}
2552383Swnj 	/*
2562383Swnj 	 * Service drives which require attention
2572383Swnj 	 * after non-data-transfer operations.
2582383Swnj 	 */
2592955Swnj 	while (drive = ffs(as)) {
2602955Swnj 		drive--;		/* was 1 origin */
2612955Swnj 		as &= ~(1 << drive);
2622981Swnj 		mi = mhp->mh_mbip[drive];
2632981Swnj 		if (mi == NULL)
2642981Swnj 			continue;
2652955Swnj 		/*
2662981Swnj 		 * If driver has a handler for non-data transfer
2673095Swnj 		 * interrupts, give it a chance to tell us what to do.
2682955Swnj 		 */
2692955Swnj 		if (mi->mi_driver->md_ndint) {
2702955Swnj 			mi->mi_tab.b_active = 0;
2712955Swnj 			switch ((*mi->mi_driver->md_ndint)(mi)) {
2722383Swnj 
2733095Swnj 			case MBN_DONE:		/* operation completed */
2742955Swnj 				mi->mi_tab.b_errcnt = 0;
2752981Swnj 				bp = mi->mi_tab.b_actf;
2762955Swnj 				mi->mi_tab.b_actf = bp->av_forw;
2772955Swnj 				iodone(bp);
2783095Swnj 				/* fall into common code */
2793095Swnj 			case MBN_RETRY:		/* operation continues */
2802955Swnj 				if (mi->mi_tab.b_actf)
2812955Swnj 					mbustart(mi);
2822955Swnj 				break;
2833095Swnj 			case MBN_SKIP:		/* ignore unsol. interrupt */
2842981Swnj 				break;
2852955Swnj 			default:
2862955Swnj 				panic("mbintr");
2872955Swnj 			}
2882955Swnj 		} else
2893095Swnj 			/*
2903095Swnj 			 * If there is no non-data transfer interrupt
2913095Swnj 			 * routine, then we should just
2923095Swnj 			 * restart the unit, leading to a mbstart() soon.
2933095Swnj 			 */
2942955Swnj 			mbustart(mi);
2952955Swnj 	}
2962383Swnj 	/*
2972383Swnj 	 * If there is an operation available and
2982383Swnj 	 * the massbus isn't active, get it going.
2992383Swnj 	 */
3002383Swnj 	if (mhp->mh_actf && !mhp->mh_active)
3012383Swnj 		mbstart(mhp);
3023095Swnj 	/* THHHHATS all folks... */
3032383Swnj }
3042383Swnj 
3052383Swnj /*
3062383Swnj  * Setup the mapping registers for a transfer.
3072383Swnj  */
3082383Swnj mbasetup(mi)
3092981Swnj 	register struct mba_device *mi;
31028Sbill {
3112383Swnj 	register struct mba_regs *mbap = mi->mi_mba;
3122383Swnj 	struct buf *bp = mi->mi_tab.b_actf;
31328Sbill 	register int i;
31428Sbill 	int npf;
31528Sbill 	unsigned v;
31628Sbill 	register struct pte *pte, *io;
31728Sbill 	int o;
31828Sbill 	int vaddr;
31928Sbill 	struct proc *rp;
32028Sbill 
3211412Sbill 	io = mbap->mba_map;
3221412Sbill 	v = btop(bp->b_un.b_addr);
3231412Sbill 	o = (int)bp->b_un.b_addr & PGOFSET;
3241412Sbill 	npf = btoc(bp->b_bcount + o);
3251412Sbill 	rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc;
3261412Sbill 	vaddr = o;
3271412Sbill 	if (bp->b_flags & B_UAREA) {
3281412Sbill 		for (i = 0; i < UPAGES; i++) {
3291412Sbill 			if (rp->p_addr[i].pg_pfnum == 0)
3301412Sbill 				panic("mba: zero upage");
3311412Sbill 			*(int *)io++ = rp->p_addr[i].pg_pfnum | PG_V;
33228Sbill 		}
3331412Sbill 	} else if ((bp->b_flags & B_PHYS) == 0) {
3341412Sbill 		pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)];
3351412Sbill 		while (--npf >= 0)
3361412Sbill 			*(int *)io++ = pte++->pg_pfnum | PG_V;
3371412Sbill 	} else {
3381412Sbill 		if (bp->b_flags & B_PAGET)
3391412Sbill 			pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)];
3401412Sbill 		else
3411412Sbill 			pte = vtopte(rp, v);
3421412Sbill 		while (--npf >= 0) {
3431412Sbill 			if (pte->pg_pfnum == 0)
3441412Sbill 				panic("mba, zero entry");
3451412Sbill 			*(int *)io++ = pte++->pg_pfnum | PG_V;
3461412Sbill 		}
34728Sbill 	}
3481412Sbill 	*(int *)io++ = 0;
3492383Swnj 	return (vaddr);
35028Sbill }
3512930Swnj 
3523095Swnj /*
3533095Swnj  * Init and interrupt enable a massbus adapter.
3543095Swnj  */
3552930Swnj mbainit(mp)
3562930Swnj 	struct mba_regs *mp;
3572930Swnj {
3582930Swnj 
3593095Swnj 	mp->mba_cr = MBCR_INIT;
3603095Swnj 	mp->mba_cr = MBCR_IE;
3612930Swnj }
3622704Swnj #endif
363