1*3095Swnj /* mba.c 4.17 81/03/08 */ 228Sbill 32704Swnj #include "mba.h" 42704Swnj #if NMBA > 0 52383Swnj /* 6*3095Swnj * Massbus driver, arbitrates a massbus among attached devices. 72383Swnj */ 828Sbill #include "../h/param.h" 92383Swnj #include "../h/systm.h" 102383Swnj #include "../h/dk.h" 1128Sbill #include "../h/buf.h" 1228Sbill #include "../h/conf.h" 1328Sbill #include "../h/dir.h" 1428Sbill #include "../h/user.h" 1528Sbill #include "../h/proc.h" 162383Swnj #include "../h/map.h" 1728Sbill #include "../h/pte.h" 182981Swnj #include "../h/mbareg.h" 192981Swnj #include "../h/mbavar.h" 2028Sbill #include "../h/mtpr.h" 2128Sbill #include "../h/vm.h" 2228Sbill 23*3095Swnj char mbsr_bits[] = MBSR_BITS; 2428Sbill /* 252383Swnj * Start activity on a massbus device. 262981Swnj * We are given the device's mba_device structure and activate 272383Swnj * the device via the unit start routine. The unit start 282383Swnj * routine may indicate that it is finished (e.g. if the operation 292383Swnj * was a ``sense'' on a tape drive), that the (multi-ported) unit 302383Swnj * is busy (we will get an interrupt later), that it started the 312383Swnj * unit (e.g. for a non-data transfer operation), or that it has 322383Swnj * set up a data transfer operation and we should start the massbus adaptor. 3328Sbill */ 342383Swnj mbustart(mi) 352981Swnj register struct mba_device *mi; 362383Swnj { 372383Swnj register struct buf *bp; /* i/o operation at head of queue */ 382383Swnj register struct mba_hd *mhp; /* header for mba device is on */ 3928Sbill 402383Swnj loop: 412383Swnj /* 422383Swnj * Get the first thing to do off device queue. 432383Swnj */ 442383Swnj bp = mi->mi_tab.b_actf; 452383Swnj if (bp == NULL) 462383Swnj return; 472383Swnj /* 482383Swnj * Let the drivers unit start routine have at it 492383Swnj * and then process the request further, per its instructions. 502383Swnj */ 512383Swnj switch ((*mi->mi_driver->md_ustart)(mi)) { 522383Swnj 532383Swnj case MBU_NEXT: /* request is complete (e.g. ``sense'') */ 542383Swnj mi->mi_tab.b_active = 0; 552955Swnj mi->mi_tab.b_errcnt = 0; 562383Swnj mi->mi_tab.b_actf = bp->av_forw; 572383Swnj iodone(bp); 582383Swnj goto loop; 592383Swnj 602383Swnj case MBU_DODATA: /* all ready to do data transfer */ 612383Swnj /* 622981Swnj * Queue the device mba_device structure on the massbus 632383Swnj * mba_hd structure for processing as soon as the 642383Swnj * data path is available. 652383Swnj */ 662383Swnj mhp = mi->mi_hd; 672383Swnj mi->mi_forw = NULL; 682383Swnj if (mhp->mh_actf == NULL) 692383Swnj mhp->mh_actf = mi; 702383Swnj else 712383Swnj mhp->mh_actl->mi_forw = mi; 722383Swnj mhp->mh_actl = mi; 732383Swnj /* 742383Swnj * If data path is idle, start transfer now. 752383Swnj * In any case the device is ``active'' waiting for the 762383Swnj * data to transfer. 772383Swnj */ 782893Swnj mi->mi_tab.b_active = 1; 792383Swnj if (mhp->mh_active == 0) 802383Swnj mbstart(mhp); 812383Swnj return; 822383Swnj 832383Swnj case MBU_STARTED: /* driver started a non-data transfer */ 842383Swnj /* 852383Swnj * Mark device busy during non-data transfer 862383Swnj * and count this as a ``seek'' on the device. 872383Swnj */ 882383Swnj if (mi->mi_dk >= 0) 892383Swnj dk_seek[mi->mi_dk]++; 902383Swnj mi->mi_tab.b_active = 1; 912383Swnj return; 922383Swnj 932383Swnj case MBU_BUSY: /* dual port drive busy */ 942383Swnj /* 952383Swnj * We mark the device structure so that when an 962383Swnj * interrupt occurs we will know to restart the unit. 972383Swnj */ 982383Swnj mi->mi_tab.b_flags |= B_BUSY; 992383Swnj return; 1002383Swnj 1012383Swnj default: 1022383Swnj panic("mbustart"); 1032383Swnj } 1042403Skre } 1052383Swnj 1062383Swnj /* 1072383Swnj * Start an i/o operation on the massbus specified by the argument. 1082383Swnj * We peel the first operation off its queue and insure that the drive 1092383Swnj * is present and on-line. We then use the drivers start routine 1102383Swnj * (if any) to prepare the drive, setup the massbus map for the transfer 1112383Swnj * and start the transfer. 1122383Swnj */ 1132383Swnj mbstart(mhp) 1142383Swnj register struct mba_hd *mhp; 1152383Swnj { 1162981Swnj register struct mba_device *mi; 1172383Swnj struct buf *bp; 1182383Swnj register struct mba_regs *mbp; 1192383Swnj 1202383Swnj loop: 1212383Swnj /* 1222383Swnj * Look for an operation at the front of the queue. 1232383Swnj */ 1242955Swnj if ((mi = mhp->mh_actf) == NULL) { 1252383Swnj return; 1262955Swnj } 1272383Swnj if ((bp = mi->mi_tab.b_actf) == NULL) { 1282383Swnj mhp->mh_actf = mi->mi_forw; 1292383Swnj goto loop; 1302383Swnj } 1312383Swnj /* 1322383Swnj * If this device isn't present and on-line, then 1332383Swnj * we screwed up, and can't really do the operation. 1342383Swnj */ 135*3095Swnj if ((mi->mi_drv->mbd_ds & MBDS_DREADY) != MBDS_DREADY) { 1362981Swnj printf("%s%d: not ready\n", mi->mi_driver->md_dname, 1372981Swnj dkunit(bp)); 1382383Swnj mi->mi_tab.b_actf = bp->av_forw; 1392893Swnj mi->mi_tab.b_errcnt = 0; 1402893Swnj mi->mi_tab.b_active = 0; 1412383Swnj bp->b_flags |= B_ERROR; 1422383Swnj iodone(bp); 1432383Swnj goto loop; 1442383Swnj } 1452383Swnj /* 1462383Swnj * We can do the operation; mark the massbus active 1472383Swnj * and let the device start routine setup any necessary 1482383Swnj * device state for the transfer (e.g. desired cylinder, etc 1492383Swnj * on disks). 1502383Swnj */ 1512383Swnj mhp->mh_active = 1; 1522884Swnj if (mi->mi_driver->md_start) 1532383Swnj (*mi->mi_driver->md_start)(mi); 1542383Swnj 1552383Swnj /* 1562383Swnj * Setup the massbus control and map registers and start 1572383Swnj * the transfer. 1582383Swnj */ 1592383Swnj mbp = mi->mi_mba; 1602383Swnj mbp->mba_sr = -1; /* conservative */ 1612383Swnj mbp->mba_var = mbasetup(mi); 1622383Swnj mbp->mba_bcr = -bp->b_bcount; 1632383Swnj mi->mi_drv->mbd_cs1 = 164*3095Swnj (bp->b_flags & B_READ) ? MB_RCOM|MB_GO : MB_WCOM|MB_GO; 1652383Swnj if (mi->mi_dk >= 0) { 1662383Swnj dk_busy |= 1 << mi->mi_dk; 1672383Swnj dk_xfer[mi->mi_dk]++; 1682383Swnj dk_wds[mi->mi_dk] += bp->b_bcount >> 6; 1692383Swnj } 1702383Swnj } 1712383Swnj 1722383Swnj /* 1732383Swnj * Take an interrupt off of massbus mbanum, 1742383Swnj * and dispatch to drivers as appropriate. 1752383Swnj */ 1762383Swnj mbintr(mbanum) 1772383Swnj int mbanum; 1782383Swnj { 1792383Swnj register struct mba_hd *mhp = &mba_hd[mbanum]; 1802383Swnj register struct mba_regs *mbp = mhp->mh_mba; 1812981Swnj register struct mba_device *mi; 182420Sbill register struct buf *bp; 1832383Swnj register int drive; 1842955Swnj int mbasr, as; 1852383Swnj 1862383Swnj /* 1872383Swnj * Read out the massbus status register 1882383Swnj * and attention status register and clear 1892383Swnj * the bits in same by writing them back. 1902383Swnj */ 1912955Swnj mbasr = mbp->mba_sr; 1922955Swnj mbp->mba_sr = mbasr; 1932884Swnj #if VAX750 194*3095Swnj if (mbasr&MBSR_CBHUNG) { 1952930Swnj printf("mba%d: control bus hung\n", mbanum); 1962930Swnj panic("cbhung"); 1972930Swnj } 1982884Swnj #endif 1992383Swnj /* note: the mbd_as register is shared between drives */ 2002955Swnj as = mbp->mba_drv[0].mbd_as & 0xff; 2012383Swnj mbp->mba_drv[0].mbd_as = as; 2022383Swnj 2032383Swnj /* 2042383Swnj * If the mba was active, process the data transfer 2052383Swnj * complete interrupt; otherwise just process units which 2062383Swnj * are now finished. 2072383Swnj */ 2082383Swnj if (mhp->mh_active) { 2092383Swnj /* 2102383Swnj * Clear attention status for drive whose data 211*3095Swnj * transfer related operation completed, 212*3095Swnj * and give the dtint driver 2132383Swnj * routine a chance to say what is next. 2142383Swnj */ 2152383Swnj mi = mhp->mh_actf; 2162383Swnj as &= ~(1 << mi->mi_drive); 2172383Swnj dk_busy &= ~(1 << mi->mi_dk); 2182383Swnj bp = mi->mi_tab.b_actf; 219*3095Swnj switch ((*mi->mi_driver->md_dtint)(mi, mbasr)) { 2202383Swnj 2212383Swnj case MBD_DONE: /* all done, for better or worse */ 2222383Swnj /* 2232383Swnj * Flush request from drive queue. 2242383Swnj */ 2252383Swnj mi->mi_tab.b_errcnt = 0; 2262383Swnj mi->mi_tab.b_actf = bp->av_forw; 2272383Swnj iodone(bp); 2282383Swnj /* fall into... */ 2292383Swnj case MBD_RETRY: /* attempt the operation again */ 2302383Swnj /* 2312383Swnj * Dequeue data transfer from massbus queue; 2322383Swnj * if there is still a i/o request on the device 2332383Swnj * queue then start the next operation on the device. 2342383Swnj * (Common code for DONE and RETRY). 2352383Swnj */ 2362383Swnj mhp->mh_active = 0; 2372383Swnj mi->mi_tab.b_active = 0; 2382383Swnj mhp->mh_actf = mi->mi_forw; 2392383Swnj if (mi->mi_tab.b_actf) 2402383Swnj mbustart(mi); 2412383Swnj break; 2422383Swnj 2432383Swnj case MBD_RESTARTED: /* driver restarted op (ecc, e.g.) 2442383Swnj /* 2452893Swnj * Note that mhp->mh_active is still on. 2462383Swnj */ 2472383Swnj break; 2482383Swnj 2492383Swnj default: 2502884Swnj panic("mbintr"); 2512383Swnj } 2522383Swnj } 2532383Swnj /* 2542383Swnj * Service drives which require attention 2552383Swnj * after non-data-transfer operations. 2562383Swnj */ 2572955Swnj while (drive = ffs(as)) { 2582955Swnj drive--; /* was 1 origin */ 2592955Swnj as &= ~(1 << drive); 2602981Swnj mi = mhp->mh_mbip[drive]; 2612981Swnj if (mi == NULL) 2622981Swnj continue; 2632955Swnj /* 2642981Swnj * If driver has a handler for non-data transfer 265*3095Swnj * interrupts, give it a chance to tell us what to do. 2662955Swnj */ 2672955Swnj if (mi->mi_driver->md_ndint) { 2682955Swnj mi->mi_tab.b_active = 0; 2692955Swnj switch ((*mi->mi_driver->md_ndint)(mi)) { 2702383Swnj 271*3095Swnj case MBN_DONE: /* operation completed */ 2722955Swnj mi->mi_tab.b_errcnt = 0; 2732981Swnj bp = mi->mi_tab.b_actf; 2742955Swnj mi->mi_tab.b_actf = bp->av_forw; 2752955Swnj iodone(bp); 276*3095Swnj /* fall into common code */ 277*3095Swnj case MBN_RETRY: /* operation continues */ 2782955Swnj if (mi->mi_tab.b_actf) 2792955Swnj mbustart(mi); 2802955Swnj break; 281*3095Swnj case MBN_SKIP: /* ignore unsol. interrupt */ 2822981Swnj break; 2832955Swnj default: 2842955Swnj panic("mbintr"); 2852955Swnj } 2862955Swnj } else 287*3095Swnj /* 288*3095Swnj * If there is no non-data transfer interrupt 289*3095Swnj * routine, then we should just 290*3095Swnj * restart the unit, leading to a mbstart() soon. 291*3095Swnj */ 2922955Swnj mbustart(mi); 2932955Swnj } 2942383Swnj /* 2952383Swnj * If there is an operation available and 2962383Swnj * the massbus isn't active, get it going. 2972383Swnj */ 2982383Swnj if (mhp->mh_actf && !mhp->mh_active) 2992383Swnj mbstart(mhp); 300*3095Swnj /* THHHHATS all folks... */ 3012383Swnj } 3022383Swnj 3032383Swnj /* 3042383Swnj * Setup the mapping registers for a transfer. 3052383Swnj */ 3062383Swnj mbasetup(mi) 3072981Swnj register struct mba_device *mi; 30828Sbill { 3092383Swnj register struct mba_regs *mbap = mi->mi_mba; 3102383Swnj struct buf *bp = mi->mi_tab.b_actf; 31128Sbill register int i; 31228Sbill int npf; 31328Sbill unsigned v; 31428Sbill register struct pte *pte, *io; 31528Sbill int o; 31628Sbill int vaddr; 31728Sbill struct proc *rp; 31828Sbill 3191412Sbill io = mbap->mba_map; 3201412Sbill v = btop(bp->b_un.b_addr); 3211412Sbill o = (int)bp->b_un.b_addr & PGOFSET; 3221412Sbill npf = btoc(bp->b_bcount + o); 3231412Sbill rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 3241412Sbill vaddr = o; 3251412Sbill if (bp->b_flags & B_UAREA) { 3261412Sbill for (i = 0; i < UPAGES; i++) { 3271412Sbill if (rp->p_addr[i].pg_pfnum == 0) 3281412Sbill panic("mba: zero upage"); 3291412Sbill *(int *)io++ = rp->p_addr[i].pg_pfnum | PG_V; 33028Sbill } 3311412Sbill } else if ((bp->b_flags & B_PHYS) == 0) { 3321412Sbill pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 3331412Sbill while (--npf >= 0) 3341412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3351412Sbill } else { 3361412Sbill if (bp->b_flags & B_PAGET) 3371412Sbill pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 3381412Sbill else 3391412Sbill pte = vtopte(rp, v); 3401412Sbill while (--npf >= 0) { 3411412Sbill if (pte->pg_pfnum == 0) 3421412Sbill panic("mba, zero entry"); 3431412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3441412Sbill } 34528Sbill } 3461412Sbill *(int *)io++ = 0; 3472383Swnj return (vaddr); 34828Sbill } 3492930Swnj 350*3095Swnj /* 351*3095Swnj * Init and interrupt enable a massbus adapter. 352*3095Swnj */ 3532930Swnj mbainit(mp) 3542930Swnj struct mba_regs *mp; 3552930Swnj { 3562930Swnj 357*3095Swnj mp->mba_cr = MBCR_INIT; 358*3095Swnj mp->mba_cr = MBCR_IE; 3592930Swnj } 3602704Swnj #endif 361