1*2981Swnj /* mba.c 4.16 81/03/07 */ 228Sbill 32704Swnj #include "mba.h" 42704Swnj #if NMBA > 0 52383Swnj /* 62884Swnj * Massbus driver; arbitrates massbus using device 72884Swnj * driver routines. This module provides common functions. 82383Swnj */ 928Sbill #include "../h/param.h" 102383Swnj #include "../h/systm.h" 112383Swnj #include "../h/dk.h" 1228Sbill #include "../h/buf.h" 1328Sbill #include "../h/conf.h" 1428Sbill #include "../h/dir.h" 1528Sbill #include "../h/user.h" 1628Sbill #include "../h/proc.h" 172383Swnj #include "../h/map.h" 1828Sbill #include "../h/pte.h" 19*2981Swnj #include "../h/mbareg.h" 20*2981Swnj #include "../h/mbavar.h" 2128Sbill #include "../h/mtpr.h" 2228Sbill #include "../h/vm.h" 2328Sbill 242673Swnj char mbasr_bits[] = MBASR_BITS; 2528Sbill /* 262383Swnj * Start activity on a massbus device. 27*2981Swnj * We are given the device's mba_device structure and activate 282383Swnj * the device via the unit start routine. The unit start 292383Swnj * routine may indicate that it is finished (e.g. if the operation 302383Swnj * was a ``sense'' on a tape drive), that the (multi-ported) unit 312383Swnj * is busy (we will get an interrupt later), that it started the 322383Swnj * unit (e.g. for a non-data transfer operation), or that it has 332383Swnj * set up a data transfer operation and we should start the massbus adaptor. 3428Sbill */ 352383Swnj mbustart(mi) 36*2981Swnj register struct mba_device *mi; 372383Swnj { 382383Swnj register struct buf *bp; /* i/o operation at head of queue */ 392383Swnj register struct mba_hd *mhp; /* header for mba device is on */ 4028Sbill 412383Swnj loop: 422383Swnj /* 432383Swnj * Get the first thing to do off device queue. 442383Swnj */ 452383Swnj bp = mi->mi_tab.b_actf; 462383Swnj if (bp == NULL) 472383Swnj return; 482383Swnj /* 492383Swnj * Let the drivers unit start routine have at it 502383Swnj * and then process the request further, per its instructions. 512383Swnj */ 522383Swnj switch ((*mi->mi_driver->md_ustart)(mi)) { 532383Swnj 542383Swnj case MBU_NEXT: /* request is complete (e.g. ``sense'') */ 552383Swnj mi->mi_tab.b_active = 0; 562955Swnj mi->mi_tab.b_errcnt = 0; 572383Swnj mi->mi_tab.b_actf = bp->av_forw; 582383Swnj iodone(bp); 592383Swnj goto loop; 602383Swnj 612383Swnj case MBU_DODATA: /* all ready to do data transfer */ 622383Swnj /* 63*2981Swnj * Queue the device mba_device structure on the massbus 642383Swnj * mba_hd structure for processing as soon as the 652383Swnj * data path is available. 662383Swnj */ 672383Swnj mhp = mi->mi_hd; 682383Swnj mi->mi_forw = NULL; 692383Swnj if (mhp->mh_actf == NULL) 702383Swnj mhp->mh_actf = mi; 712383Swnj else 722383Swnj mhp->mh_actl->mi_forw = mi; 732383Swnj mhp->mh_actl = mi; 742383Swnj /* 752383Swnj * If data path is idle, start transfer now. 762383Swnj * In any case the device is ``active'' waiting for the 772383Swnj * data to transfer. 782383Swnj */ 792893Swnj mi->mi_tab.b_active = 1; 802383Swnj if (mhp->mh_active == 0) 812383Swnj mbstart(mhp); 822383Swnj return; 832383Swnj 842383Swnj case MBU_STARTED: /* driver started a non-data transfer */ 852383Swnj /* 862383Swnj * Mark device busy during non-data transfer 872383Swnj * and count this as a ``seek'' on the device. 882383Swnj */ 892383Swnj if (mi->mi_dk >= 0) 902383Swnj dk_seek[mi->mi_dk]++; 912383Swnj mi->mi_tab.b_active = 1; 922383Swnj return; 932383Swnj 942383Swnj case MBU_BUSY: /* dual port drive busy */ 952383Swnj /* 962383Swnj * We mark the device structure so that when an 972383Swnj * interrupt occurs we will know to restart the unit. 982383Swnj */ 992383Swnj mi->mi_tab.b_flags |= B_BUSY; 1002383Swnj return; 1012383Swnj 1022383Swnj default: 1032383Swnj panic("mbustart"); 1042383Swnj } 1052403Skre } 1062383Swnj 1072383Swnj /* 1082383Swnj * Start an i/o operation on the massbus specified by the argument. 1092383Swnj * We peel the first operation off its queue and insure that the drive 1102383Swnj * is present and on-line. We then use the drivers start routine 1112383Swnj * (if any) to prepare the drive, setup the massbus map for the transfer 1122383Swnj * and start the transfer. 1132383Swnj */ 1142383Swnj mbstart(mhp) 1152383Swnj register struct mba_hd *mhp; 1162383Swnj { 117*2981Swnj register struct mba_device *mi; 1182383Swnj struct buf *bp; 1192383Swnj register struct mba_regs *mbp; 1202383Swnj 1212383Swnj loop: 1222383Swnj /* 1232383Swnj * Look for an operation at the front of the queue. 1242383Swnj */ 1252955Swnj if ((mi = mhp->mh_actf) == NULL) { 1262383Swnj return; 1272955Swnj } 1282383Swnj if ((bp = mi->mi_tab.b_actf) == NULL) { 1292383Swnj mhp->mh_actf = mi->mi_forw; 1302383Swnj goto loop; 1312383Swnj } 1322383Swnj /* 1332383Swnj * If this device isn't present and on-line, then 1342383Swnj * we screwed up, and can't really do the operation. 1352383Swnj */ 1362383Swnj if ((mi->mi_drv->mbd_ds & (MBD_DPR|MBD_MOL)) != (MBD_DPR|MBD_MOL)) { 137*2981Swnj printf("%s%d: not ready\n", mi->mi_driver->md_dname, 138*2981Swnj dkunit(bp)); 1392383Swnj mi->mi_tab.b_actf = bp->av_forw; 1402893Swnj mi->mi_tab.b_errcnt = 0; 1412893Swnj mi->mi_tab.b_active = 0; 1422383Swnj bp->b_flags |= B_ERROR; 1432383Swnj iodone(bp); 1442383Swnj goto loop; 1452383Swnj } 1462383Swnj /* 1472383Swnj * We can do the operation; mark the massbus active 1482383Swnj * and let the device start routine setup any necessary 1492383Swnj * device state for the transfer (e.g. desired cylinder, etc 1502383Swnj * on disks). 1512383Swnj */ 1522383Swnj mhp->mh_active = 1; 1532884Swnj if (mi->mi_driver->md_start) 1542383Swnj (*mi->mi_driver->md_start)(mi); 1552383Swnj 1562383Swnj /* 1572383Swnj * Setup the massbus control and map registers and start 1582383Swnj * the transfer. 1592383Swnj */ 1602383Swnj mbp = mi->mi_mba; 1612383Swnj mbp->mba_sr = -1; /* conservative */ 1622383Swnj mbp->mba_var = mbasetup(mi); 1632383Swnj mbp->mba_bcr = -bp->b_bcount; 1642383Swnj mi->mi_drv->mbd_cs1 = 1652383Swnj (bp->b_flags & B_READ) ? MBD_RCOM|MBD_GO : MBD_WCOM|MBD_GO; 1662383Swnj if (mi->mi_dk >= 0) { 1672383Swnj dk_busy |= 1 << mi->mi_dk; 1682383Swnj dk_xfer[mi->mi_dk]++; 1692383Swnj dk_wds[mi->mi_dk] += bp->b_bcount >> 6; 1702383Swnj } 1712383Swnj } 1722383Swnj 1732383Swnj /* 1742383Swnj * Take an interrupt off of massbus mbanum, 1752383Swnj * and dispatch to drivers as appropriate. 1762383Swnj */ 1772383Swnj mbintr(mbanum) 1782383Swnj int mbanum; 1792383Swnj { 1802383Swnj register struct mba_hd *mhp = &mba_hd[mbanum]; 1812383Swnj register struct mba_regs *mbp = mhp->mh_mba; 182*2981Swnj register struct mba_device *mi; 183420Sbill register struct buf *bp; 1842383Swnj register int drive; 1852955Swnj int mbasr, as; 1862383Swnj 1872383Swnj /* 1882383Swnj * Read out the massbus status register 1892383Swnj * and attention status register and clear 1902383Swnj * the bits in same by writing them back. 1912383Swnj */ 1922955Swnj mbasr = mbp->mba_sr; 1932955Swnj mbp->mba_sr = mbasr; 1942884Swnj #if VAX750 1952955Swnj if (mbasr&MBS_CBHUNG) { 1962930Swnj printf("mba%d: control bus hung\n", mbanum); 1972930Swnj panic("cbhung"); 1982930Swnj } 1992884Swnj #endif 2002383Swnj /* note: the mbd_as register is shared between drives */ 2012955Swnj as = mbp->mba_drv[0].mbd_as & 0xff; 2022383Swnj mbp->mba_drv[0].mbd_as = as; 2032383Swnj 2042383Swnj /* 2052383Swnj * Disable interrupts from the massbus adapter 2062383Swnj * for the duration of the operation of the massbus 2072383Swnj * driver, so that spurious interrupts won't be generated. 2082383Swnj */ 2092383Swnj mbp->mba_cr &= ~MBAIE; 2102383Swnj 2112383Swnj /* 2122383Swnj * If the mba was active, process the data transfer 2132383Swnj * complete interrupt; otherwise just process units which 2142383Swnj * are now finished. 2152383Swnj */ 2162383Swnj if (mhp->mh_active) { 2172383Swnj /* 2182383Swnj * Clear attention status for drive whose data 2192383Swnj * transfer completed, and give the dtint driver 2202383Swnj * routine a chance to say what is next. 2212383Swnj */ 2222383Swnj mi = mhp->mh_actf; 2232383Swnj as &= ~(1 << mi->mi_drive); 2242383Swnj dk_busy &= ~(1 << mi->mi_dk); 2252383Swnj bp = mi->mi_tab.b_actf; 2262955Swnj switch((*mi->mi_driver->md_dtint)(mi, mbasr)) { 2272383Swnj 2282383Swnj case MBD_DONE: /* all done, for better or worse */ 2292383Swnj /* 2302383Swnj * Flush request from drive queue. 2312383Swnj */ 2322383Swnj mi->mi_tab.b_errcnt = 0; 2332383Swnj mi->mi_tab.b_actf = bp->av_forw; 2342383Swnj iodone(bp); 2352383Swnj /* fall into... */ 2362383Swnj case MBD_RETRY: /* attempt the operation again */ 2372383Swnj /* 2382383Swnj * Dequeue data transfer from massbus queue; 2392383Swnj * if there is still a i/o request on the device 2402383Swnj * queue then start the next operation on the device. 2412383Swnj * (Common code for DONE and RETRY). 2422383Swnj */ 2432383Swnj mhp->mh_active = 0; 2442383Swnj mi->mi_tab.b_active = 0; 2452383Swnj mhp->mh_actf = mi->mi_forw; 2462383Swnj if (mi->mi_tab.b_actf) 2472383Swnj mbustart(mi); 2482383Swnj break; 2492383Swnj 2502383Swnj case MBD_RESTARTED: /* driver restarted op (ecc, e.g.) 2512383Swnj /* 2522893Swnj * Note that mhp->mh_active is still on. 2532383Swnj */ 2542383Swnj break; 2552383Swnj 2562383Swnj default: 2572884Swnj panic("mbintr"); 2582383Swnj } 2592383Swnj } 2602383Swnj /* 2612383Swnj * Service drives which require attention 2622383Swnj * after non-data-transfer operations. 2632383Swnj */ 2642955Swnj while (drive = ffs(as)) { 2652955Swnj drive--; /* was 1 origin */ 2662955Swnj as &= ~(1 << drive); 267*2981Swnj mi = mhp->mh_mbip[drive]; 268*2981Swnj if (mi == NULL) 269*2981Swnj continue; 2702955Swnj /* 271*2981Swnj * If driver has a handler for non-data transfer 2722955Swnj * interrupts, give it a chance to tell us that 2732955Swnj * the operation needs to be redone 2742955Swnj */ 2752955Swnj if (mi->mi_driver->md_ndint) { 2762955Swnj mi->mi_tab.b_active = 0; 2772955Swnj switch ((*mi->mi_driver->md_ndint)(mi)) { 2782383Swnj 2792955Swnj case MBN_DONE: 2802955Swnj /* 2812955Swnj * Non-data transfer interrupt 2822955Swnj * completed i/o request's processing. 2832955Swnj */ 2842955Swnj mi->mi_tab.b_errcnt = 0; 285*2981Swnj bp = mi->mi_tab.b_actf; 2862955Swnj mi->mi_tab.b_actf = bp->av_forw; 2872955Swnj iodone(bp); 2882955Swnj /* fall into... */ 2892955Swnj case MBN_RETRY: 2902955Swnj if (mi->mi_tab.b_actf) 2912955Swnj mbustart(mi); 2922955Swnj break; 2932383Swnj 294*2981Swnj case MBN_SKIP: 295*2981Swnj /* 296*2981Swnj * Ignore (unsolicited interrupt, e.g.) 297*2981Swnj */ 298*2981Swnj break; 299*2981Swnj 300*2981Swnj case MBN_CONT: 301*2981Swnj /* 302*2981Swnj * Continue with unit active, e.g. 303*2981Swnj * between first and second rewind 304*2981Swnj * interrupts. 305*2981Swnj */ 306*2981Swnj mi->mi_tab.b_active = 1; 307*2981Swnj break; 308*2981Swnj 3092955Swnj default: 3102955Swnj panic("mbintr"); 3112955Swnj } 3122955Swnj } else 3132955Swnj mbustart(mi); 3142955Swnj } 3152383Swnj /* 3162383Swnj * If there is an operation available and 3172383Swnj * the massbus isn't active, get it going. 3182383Swnj */ 3192383Swnj if (mhp->mh_actf && !mhp->mh_active) 3202383Swnj mbstart(mhp); 3212383Swnj mbp->mba_cr |= MBAIE; 3222383Swnj } 3232383Swnj 3242383Swnj /* 3252383Swnj * Setup the mapping registers for a transfer. 3262383Swnj */ 3272383Swnj mbasetup(mi) 328*2981Swnj register struct mba_device *mi; 32928Sbill { 3302383Swnj register struct mba_regs *mbap = mi->mi_mba; 3312383Swnj struct buf *bp = mi->mi_tab.b_actf; 33228Sbill register int i; 33328Sbill int npf; 33428Sbill unsigned v; 33528Sbill register struct pte *pte, *io; 33628Sbill int o; 33728Sbill int vaddr; 33828Sbill struct proc *rp; 33928Sbill 3401412Sbill io = mbap->mba_map; 3411412Sbill v = btop(bp->b_un.b_addr); 3421412Sbill o = (int)bp->b_un.b_addr & PGOFSET; 3431412Sbill npf = btoc(bp->b_bcount + o); 3441412Sbill rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 3451412Sbill vaddr = o; 3461412Sbill if (bp->b_flags & B_UAREA) { 3471412Sbill for (i = 0; i < UPAGES; i++) { 3481412Sbill if (rp->p_addr[i].pg_pfnum == 0) 3491412Sbill panic("mba: zero upage"); 3501412Sbill *(int *)io++ = rp->p_addr[i].pg_pfnum | PG_V; 35128Sbill } 3521412Sbill } else if ((bp->b_flags & B_PHYS) == 0) { 3531412Sbill pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 3541412Sbill while (--npf >= 0) 3551412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3561412Sbill } else { 3571412Sbill if (bp->b_flags & B_PAGET) 3581412Sbill pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 3591412Sbill else 3601412Sbill pte = vtopte(rp, v); 3611412Sbill while (--npf >= 0) { 3621412Sbill if (pte->pg_pfnum == 0) 3631412Sbill panic("mba, zero entry"); 3641412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3651412Sbill } 36628Sbill } 3671412Sbill *(int *)io++ = 0; 3682383Swnj return (vaddr); 36928Sbill } 3702930Swnj 3712930Swnj mbainit(mp) 3722930Swnj struct mba_regs *mp; 3732930Swnj { 3742930Swnj 3752930Swnj mp->mba_cr = MBAINIT; 3762930Swnj mp->mba_cr = MBAIE; 3772930Swnj } 3782704Swnj #endif 379