1*2955Swnj /* mba.c 4.15 81/03/06 */ 228Sbill 32704Swnj #include "mba.h" 42704Swnj #if NMBA > 0 52383Swnj /* 62884Swnj * Massbus driver; arbitrates massbus using device 72884Swnj * driver routines. This module provides common functions. 82383Swnj */ 928Sbill #include "../h/param.h" 102383Swnj #include "../h/systm.h" 112383Swnj #include "../h/dk.h" 1228Sbill #include "../h/buf.h" 1328Sbill #include "../h/conf.h" 1428Sbill #include "../h/dir.h" 1528Sbill #include "../h/user.h" 1628Sbill #include "../h/proc.h" 172383Swnj #include "../h/map.h" 1828Sbill #include "../h/pte.h" 1928Sbill #include "../h/mba.h" 2028Sbill #include "../h/mtpr.h" 2128Sbill #include "../h/vm.h" 2228Sbill 232673Swnj char mbasr_bits[] = MBASR_BITS; 2428Sbill /* 252383Swnj * Start activity on a massbus device. 262383Swnj * We are given the device's mba_info structure and activate 272383Swnj * the device via the unit start routine. The unit start 282383Swnj * routine may indicate that it is finished (e.g. if the operation 292383Swnj * was a ``sense'' on a tape drive), that the (multi-ported) unit 302383Swnj * is busy (we will get an interrupt later), that it started the 312383Swnj * unit (e.g. for a non-data transfer operation), or that it has 322383Swnj * set up a data transfer operation and we should start the massbus adaptor. 3328Sbill */ 342383Swnj mbustart(mi) 352383Swnj register struct mba_info *mi; 362383Swnj { 372383Swnj register struct buf *bp; /* i/o operation at head of queue */ 382383Swnj register struct mba_hd *mhp; /* header for mba device is on */ 3928Sbill 402383Swnj loop: 412383Swnj /* 422383Swnj * Get the first thing to do off device queue. 432383Swnj */ 442383Swnj bp = mi->mi_tab.b_actf; 452383Swnj if (bp == NULL) 462383Swnj return; 472383Swnj /* 482383Swnj * Let the drivers unit start routine have at it 492383Swnj * and then process the request further, per its instructions. 502383Swnj */ 512383Swnj switch ((*mi->mi_driver->md_ustart)(mi)) { 522383Swnj 532383Swnj case MBU_NEXT: /* request is complete (e.g. ``sense'') */ 542383Swnj mi->mi_tab.b_active = 0; 55*2955Swnj mi->mi_tab.b_errcnt = 0; 562383Swnj mi->mi_tab.b_actf = bp->av_forw; 572383Swnj iodone(bp); 582383Swnj goto loop; 592383Swnj 602383Swnj case MBU_DODATA: /* all ready to do data transfer */ 612383Swnj /* 622383Swnj * Queue the device mba_info structure on the massbus 632383Swnj * mba_hd structure for processing as soon as the 642383Swnj * data path is available. 652383Swnj */ 662383Swnj mhp = mi->mi_hd; 672383Swnj mi->mi_forw = NULL; 682383Swnj if (mhp->mh_actf == NULL) 692383Swnj mhp->mh_actf = mi; 702383Swnj else 712383Swnj mhp->mh_actl->mi_forw = mi; 722383Swnj mhp->mh_actl = mi; 732383Swnj /* 742383Swnj * If data path is idle, start transfer now. 752383Swnj * In any case the device is ``active'' waiting for the 762383Swnj * data to transfer. 772383Swnj */ 782893Swnj mi->mi_tab.b_active = 1; 792383Swnj if (mhp->mh_active == 0) 802383Swnj mbstart(mhp); 812383Swnj return; 822383Swnj 832383Swnj case MBU_STARTED: /* driver started a non-data transfer */ 842383Swnj /* 852383Swnj * Mark device busy during non-data transfer 862383Swnj * and count this as a ``seek'' on the device. 872383Swnj */ 882383Swnj if (mi->mi_dk >= 0) 892383Swnj dk_seek[mi->mi_dk]++; 902383Swnj mi->mi_tab.b_active = 1; 912383Swnj return; 922383Swnj 932383Swnj case MBU_BUSY: /* dual port drive busy */ 942383Swnj /* 952383Swnj * We mark the device structure so that when an 962383Swnj * interrupt occurs we will know to restart the unit. 972383Swnj */ 982383Swnj mi->mi_tab.b_flags |= B_BUSY; 992383Swnj return; 1002383Swnj 1012383Swnj default: 1022383Swnj panic("mbustart"); 1032383Swnj } 1042403Skre } 1052383Swnj 1062383Swnj /* 1072383Swnj * Start an i/o operation on the massbus specified by the argument. 1082383Swnj * We peel the first operation off its queue and insure that the drive 1092383Swnj * is present and on-line. We then use the drivers start routine 1102383Swnj * (if any) to prepare the drive, setup the massbus map for the transfer 1112383Swnj * and start the transfer. 1122383Swnj */ 1132383Swnj mbstart(mhp) 1142383Swnj register struct mba_hd *mhp; 1152383Swnj { 1162383Swnj register struct mba_info *mi; 1172383Swnj struct buf *bp; 1182383Swnj register struct mba_regs *mbp; 1192383Swnj 1202383Swnj loop: 1212383Swnj /* 1222383Swnj * Look for an operation at the front of the queue. 1232383Swnj */ 124*2955Swnj if ((mi = mhp->mh_actf) == NULL) { 1252383Swnj return; 126*2955Swnj } 1272383Swnj if ((bp = mi->mi_tab.b_actf) == NULL) { 1282383Swnj mhp->mh_actf = mi->mi_forw; 1292383Swnj goto loop; 1302383Swnj } 1312383Swnj /* 1322383Swnj * If this device isn't present and on-line, then 1332383Swnj * we screwed up, and can't really do the operation. 1342383Swnj */ 1352383Swnj if ((mi->mi_drv->mbd_ds & (MBD_DPR|MBD_MOL)) != (MBD_DPR|MBD_MOL)) { 1362930Swnj printf("%c%d: not ready\n", mi->mi_name, dkunit(bp)); 1372383Swnj mi->mi_tab.b_actf = bp->av_forw; 1382893Swnj mi->mi_tab.b_errcnt = 0; 1392893Swnj mi->mi_tab.b_active = 0; 1402383Swnj bp->b_flags |= B_ERROR; 1412383Swnj iodone(bp); 1422383Swnj goto loop; 1432383Swnj } 1442383Swnj /* 1452383Swnj * We can do the operation; mark the massbus active 1462383Swnj * and let the device start routine setup any necessary 1472383Swnj * device state for the transfer (e.g. desired cylinder, etc 1482383Swnj * on disks). 1492383Swnj */ 1502383Swnj mhp->mh_active = 1; 1512884Swnj if (mi->mi_driver->md_start) 1522383Swnj (*mi->mi_driver->md_start)(mi); 1532383Swnj 1542383Swnj /* 1552383Swnj * Setup the massbus control and map registers and start 1562383Swnj * the transfer. 1572383Swnj */ 1582383Swnj mbp = mi->mi_mba; 1592383Swnj mbp->mba_sr = -1; /* conservative */ 1602383Swnj mbp->mba_var = mbasetup(mi); 1612383Swnj mbp->mba_bcr = -bp->b_bcount; 1622383Swnj mi->mi_drv->mbd_cs1 = 1632383Swnj (bp->b_flags & B_READ) ? MBD_RCOM|MBD_GO : MBD_WCOM|MBD_GO; 1642383Swnj if (mi->mi_dk >= 0) { 1652383Swnj dk_busy |= 1 << mi->mi_dk; 1662383Swnj dk_xfer[mi->mi_dk]++; 1672383Swnj dk_wds[mi->mi_dk] += bp->b_bcount >> 6; 1682383Swnj } 1692383Swnj } 1702383Swnj 1712383Swnj /* 1722383Swnj * Take an interrupt off of massbus mbanum, 1732383Swnj * and dispatch to drivers as appropriate. 1742383Swnj */ 1752383Swnj mbintr(mbanum) 1762383Swnj int mbanum; 1772383Swnj { 1782383Swnj register struct mba_hd *mhp = &mba_hd[mbanum]; 1792383Swnj register struct mba_regs *mbp = mhp->mh_mba; 1802383Swnj register struct mba_info *mi; 181420Sbill register struct buf *bp; 1822383Swnj register int drive; 183*2955Swnj int mbasr, as; 1842383Swnj 1852383Swnj /* 1862383Swnj * Read out the massbus status register 1872383Swnj * and attention status register and clear 1882383Swnj * the bits in same by writing them back. 1892383Swnj */ 190*2955Swnj mbasr = mbp->mba_sr; 191*2955Swnj mbp->mba_sr = mbasr; 1922884Swnj #if VAX750 193*2955Swnj if (mbasr&MBS_CBHUNG) { 1942930Swnj printf("mba%d: control bus hung\n", mbanum); 1952930Swnj panic("cbhung"); 1962930Swnj } 1972884Swnj #endif 1982383Swnj /* note: the mbd_as register is shared between drives */ 199*2955Swnj as = mbp->mba_drv[0].mbd_as & 0xff; 2002383Swnj mbp->mba_drv[0].mbd_as = as; 2012383Swnj 2022383Swnj /* 2032383Swnj * Disable interrupts from the massbus adapter 2042383Swnj * for the duration of the operation of the massbus 2052383Swnj * driver, so that spurious interrupts won't be generated. 2062383Swnj */ 2072383Swnj mbp->mba_cr &= ~MBAIE; 2082383Swnj 2092383Swnj /* 2102383Swnj * If the mba was active, process the data transfer 2112383Swnj * complete interrupt; otherwise just process units which 2122383Swnj * are now finished. 2132383Swnj */ 2142383Swnj if (mhp->mh_active) { 2152383Swnj /* 2162383Swnj * Clear attention status for drive whose data 2172383Swnj * transfer completed, and give the dtint driver 2182383Swnj * routine a chance to say what is next. 2192383Swnj */ 2202383Swnj mi = mhp->mh_actf; 2212383Swnj as &= ~(1 << mi->mi_drive); 2222383Swnj dk_busy &= ~(1 << mi->mi_dk); 2232383Swnj bp = mi->mi_tab.b_actf; 224*2955Swnj switch((*mi->mi_driver->md_dtint)(mi, mbasr)) { 2252383Swnj 2262383Swnj case MBD_DONE: /* all done, for better or worse */ 2272383Swnj /* 2282383Swnj * Flush request from drive queue. 2292383Swnj */ 2302383Swnj mi->mi_tab.b_errcnt = 0; 2312383Swnj mi->mi_tab.b_actf = bp->av_forw; 2322383Swnj iodone(bp); 2332383Swnj /* fall into... */ 2342383Swnj case MBD_RETRY: /* attempt the operation again */ 2352383Swnj /* 2362383Swnj * Dequeue data transfer from massbus queue; 2372383Swnj * if there is still a i/o request on the device 2382383Swnj * queue then start the next operation on the device. 2392383Swnj * (Common code for DONE and RETRY). 2402383Swnj */ 2412383Swnj mhp->mh_active = 0; 2422383Swnj mi->mi_tab.b_active = 0; 2432383Swnj mhp->mh_actf = mi->mi_forw; 2442383Swnj if (mi->mi_tab.b_actf) 2452383Swnj mbustart(mi); 2462383Swnj break; 2472383Swnj 2482383Swnj case MBD_RESTARTED: /* driver restarted op (ecc, e.g.) 2492383Swnj /* 2502893Swnj * Note that mhp->mh_active is still on. 2512383Swnj */ 2522383Swnj break; 2532383Swnj 2542383Swnj default: 2552884Swnj panic("mbintr"); 2562383Swnj } 2572383Swnj } 2582383Swnj /* 2592383Swnj * Service drives which require attention 2602383Swnj * after non-data-transfer operations. 2612383Swnj */ 262*2955Swnj while (drive = ffs(as)) { 263*2955Swnj drive--; /* was 1 origin */ 264*2955Swnj as &= ~(1 << drive); 265*2955Swnj /* 266*2955Swnj * driver has a handler for non-data transfer 267*2955Swnj * interrupts, give it a chance to tell us that 268*2955Swnj * the operation needs to be redone 269*2955Swnj */ 270*2955Swnj mi = mhp->mh_mbip[drive]; 271*2955Swnj if (mi == NULL) 272*2955Swnj continue; 273*2955Swnj if (mi->mi_driver->md_ndint) { 274*2955Swnj mi->mi_tab.b_active = 0; 275*2955Swnj switch ((*mi->mi_driver->md_ndint)(mi)) { 2762383Swnj 277*2955Swnj case MBN_DONE: 278*2955Swnj /* 279*2955Swnj * Non-data transfer interrupt 280*2955Swnj * completed i/o request's processing. 281*2955Swnj */ 282*2955Swnj mi->mi_tab.b_errcnt = 0; 283*2955Swnj mi->mi_tab.b_actf = bp->av_forw; 284*2955Swnj iodone(bp); 285*2955Swnj /* fall into... */ 286*2955Swnj case MBN_RETRY: 287*2955Swnj if (mi->mi_tab.b_actf) 288*2955Swnj mbustart(mi); 289*2955Swnj break; 2902383Swnj 291*2955Swnj default: 292*2955Swnj panic("mbintr"); 293*2955Swnj } 294*2955Swnj } else 295*2955Swnj mbustart(mi); 296*2955Swnj } 2972383Swnj /* 2982383Swnj * If there is an operation available and 2992383Swnj * the massbus isn't active, get it going. 3002383Swnj */ 3012383Swnj if (mhp->mh_actf && !mhp->mh_active) 3022383Swnj mbstart(mhp); 3032383Swnj mbp->mba_cr |= MBAIE; 3042383Swnj } 3052383Swnj 3062383Swnj /* 3072383Swnj * Setup the mapping registers for a transfer. 3082383Swnj */ 3092383Swnj mbasetup(mi) 3102383Swnj register struct mba_info *mi; 31128Sbill { 3122383Swnj register struct mba_regs *mbap = mi->mi_mba; 3132383Swnj struct buf *bp = mi->mi_tab.b_actf; 31428Sbill register int i; 31528Sbill int npf; 31628Sbill unsigned v; 31728Sbill register struct pte *pte, *io; 31828Sbill int o; 31928Sbill int vaddr; 32028Sbill struct proc *rp; 32128Sbill 3221412Sbill io = mbap->mba_map; 3231412Sbill v = btop(bp->b_un.b_addr); 3241412Sbill o = (int)bp->b_un.b_addr & PGOFSET; 3251412Sbill npf = btoc(bp->b_bcount + o); 3261412Sbill rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 3271412Sbill vaddr = o; 3281412Sbill if (bp->b_flags & B_UAREA) { 3291412Sbill for (i = 0; i < UPAGES; i++) { 3301412Sbill if (rp->p_addr[i].pg_pfnum == 0) 3311412Sbill panic("mba: zero upage"); 3321412Sbill *(int *)io++ = rp->p_addr[i].pg_pfnum | PG_V; 33328Sbill } 3341412Sbill } else if ((bp->b_flags & B_PHYS) == 0) { 3351412Sbill pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 3361412Sbill while (--npf >= 0) 3371412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3381412Sbill } else { 3391412Sbill if (bp->b_flags & B_PAGET) 3401412Sbill pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 3411412Sbill else 3421412Sbill pte = vtopte(rp, v); 3431412Sbill while (--npf >= 0) { 3441412Sbill if (pte->pg_pfnum == 0) 3451412Sbill panic("mba, zero entry"); 3461412Sbill *(int *)io++ = pte++->pg_pfnum | PG_V; 3471412Sbill } 34828Sbill } 3491412Sbill *(int *)io++ = 0; 3502383Swnj return (vaddr); 35128Sbill } 3522930Swnj 3532930Swnj mbainit(mp) 3542930Swnj struct mba_regs *mp; 3552930Swnj { 3562930Swnj 3572930Swnj mp->mba_cr = MBAINIT; 3582930Swnj mp->mba_cr = MBAIE; 3592930Swnj } 3602704Swnj #endif 361