1*3336Swnj /* htreg.h 4.1 81/03/21 */ 2*3336Swnj 3*3336Swnj struct htdevice 4*3336Swnj { 5*3336Swnj int htcs1; /* control status register */ 6*3336Swnj int htds; /* drive status register */ 7*3336Swnj int hter; /* error register */ 8*3336Swnj int htmr; /* maintenance register */ 9*3336Swnj int htas; /* attention status register */ 10*3336Swnj int htfc; /* frame counter */ 11*3336Swnj int htdt; /* drive type register */ 12*3336Swnj int htck; /* nrzi check (crc) error character */ 13*3336Swnj int htsn; /* serial number register */ 14*3336Swnj int httc; /* tape controll register */ 15*3336Swnj }; 16*3336Swnj 17*3336Swnj /* htcs1 */ 18*3336Swnj #define HT_GO 000001 /* go bit */ 19*3336Swnj #define HT_SENSE 000000 /* no operations (sense) */ 20*3336Swnj #define HT_REWOFFL 000002 /* rewind offline */ 21*3336Swnj #define HT_REW 000006 /* rewind */ 22*3336Swnj #define HT_DCLR 000010 /* drive clear */ 23*3336Swnj #define HT_RIP 000020 /* read in preset */ 24*3336Swnj #define HT_ERASE 000024 /* erase */ 25*3336Swnj #define HT_WEOF 000026 /* write tape mark */ 26*3336Swnj #define HT_SFORW 000030 /* space forward */ 27*3336Swnj #define HT_SREV 000032 /* space reverse */ 28*3336Swnj #define HT_WCHFWD 000050 /* write check forward */ 29*3336Swnj #define HT_WCHREV 000056 /* write check reverse */ 30*3336Swnj #define HT_WCOM 000060 /* write forward */ 31*3336Swnj #define HT_RCOM 000070 /* read forward */ 32*3336Swnj #define HT_RREV 000076 /* read reverse */ 33*3336Swnj 34*3336Swnj /* htds */ 35*3336Swnj #define HTDS_ATA 0100000 /* attention active */ 36*3336Swnj #define HTDS_ERR 0040000 /* composite error */ 37*3336Swnj #define HTDS_PIP 0020000 /* positioning in progress */ 38*3336Swnj #define HTDS_MOL 0010000 /* medium on line */ 39*3336Swnj #define HTDS_WRL 0004000 /* write lock */ 40*3336Swnj #define HTDS_EOT 0002000 /* end of tape */ 41*3336Swnj /* bit 9 is unused */ 42*3336Swnj #define HTDS_DPR 0000400 /* drive present (always 1) */ 43*3336Swnj #define HTDS_DRY 0000200 /* drive ready */ 44*3336Swnj #define HTDS_SSC 0000100 /* slave status change */ 45*3336Swnj #define HTDS_PES 0000040 /* phase-encoded status */ 46*3336Swnj #define HTDS_SDWN 0000020 /* settle down */ 47*3336Swnj #define HTDS_IDB 0000010 /* identification burst */ 48*3336Swnj #define HTDS_TM 0000004 /* tape mark */ 49*3336Swnj #define HTDS_BOT 0000002 /* beginning of tape */ 50*3336Swnj #define HTDS_SLA 0000001 /* slave attention */ 51*3336Swnj 52*3336Swnj #define HTDS_BITS \ 53*3336Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13EOT\11DPR\10DRY\ 54*3336Swnj \7SSC\6PES\5SDWN\4IDB\3TM\2BOT\1SLA" 55*3336Swnj 56*3336Swnj /* hter */ 57*3336Swnj #define HTER_CORCRC 0100000 /* correctible data or ecc */ 58*3336Swnj #define HTER_UNS 0040000 /* unsafe */ 59*3336Swnj #define HTER_OPI 0020000 /* operation incomplete */ 60*3336Swnj #define HTER_DTE 0010000 /* drive timing error */ 61*3336Swnj #define HTER_NEF 0004000 /* non-executable function */ 62*3336Swnj #define HTER_CSITM 0002000 /* correctable skew/illegal tape mark */ 63*3336Swnj #define HTER_FCE 0001000 /* frame count error */ 64*3336Swnj #define HTER_NSG 0000400 /* non-standard gap */ 65*3336Swnj #define HTER_PEFLRC 0000200 /* format error or lrc error */ 66*3336Swnj #define HTER_INCVPE 0000100 /* incorrectable data error or vertical 67*3336Swnj parity error */ 68*3336Swnj #define HTER_DPAR 0000040 /* data parity error */ 69*3336Swnj #define HTER_FMT 0000020 /* format error */ 70*3336Swnj #define HTER_CPAR 0000010 /* control bus parity error */ 71*3336Swnj #define HTER_RMR 0000004 /* register modification refused */ 72*3336Swnj #define HTER_ILR 0000002 /* illegal register */ 73*3336Swnj #define HTER_ILF 0000001 /* illegal function */ 74*3336Swnj 75*3336Swnj #define HTER_BITS \ 76*3336Swnj "\10\20CORCRC\17UNS\16OPI\15DTE\14NEF\13CSITM\12FCE\11NSG\10PEFLRC\ 77*3336Swnj \7INCVPE\6DPAR\5FMT\4CPAR\3RMR\2ILR\1ILF" 78*3336Swnj #define HTER_HARD \ 79*3336Swnj (HTER_UNS|HTER_OPI|HTER_NEF|HTER_DPAR|HTER_FMT|HTER_CPAR| \ 80*3336Swnj HTER_RMR|HTER_ILR|HTER_ILF) 81*3336Swnj 82*3336Swnj /* htdt */ 83*3336Swnj #define HTDT_NSA 0100000 /* not sector addressed; always 1 */ 84*3336Swnj #define HTDT_TAP 0040000 /* tape; always 1 */ 85*3336Swnj #define HTDT_MOH 0020000 /* moving head; always 0 */ 86*3336Swnj #define HTDT_7CH 0010000 /* 7 channel; always 0 */ 87*3336Swnj #define HTDT_DRQ 0004000 /* drive requested; always 0 */ 88*3336Swnj #define HTDT_SPR 0002000 /* slave present */ 89*3336Swnj /* bit 9 is spare */ 90*3336Swnj /* bits 8-0 are formatter/transport type */ 91*3336Swnj 92*3336Swnj /* httc */ 93*3336Swnj #define HTTC_ACCL 0100000 /* transport is not reading/writing */ 94*3336Swnj #define HTTC_FCS 0040000 /* frame count status */ 95*3336Swnj #define HTTC_SAC 0020000 /* slave address change */ 96*3336Swnj #define HTTC_EAODTE 0010000 /* enable abort on data xfer errors */ 97*3336Swnj /* bits 8-10 are density select */ 98*3336Swnj #define HTTC_800BPI 0001400 /* in bits 8-10, dens=1600 */ 99*3336Swnj #define HTTC_1600BPI 0002000 /* in bits 8-10, dens=800 */ 100*3336Swnj /* bits 4-7 are format select */ 101*3336Swnj #define HTTC_PDP11 0000300 /* in bits 4-7, pdp11 normal format */ 102*3336Swnj #define HTTC_EVEN 0000010 /* select even parity */ 103*3336Swnj /* bits 0 - 2 are slave select */ 104*3336Swnj 105*3336Swnj #define b_repcnt b_bcount 106*3336Swnj #define b_command b_resid 107