1*7739Sroot /* ht.c 4.26 82/08/13 */ 22961Swnj 32980Swnj #include "tu.h" 41563Sbill #if NHT > 0 522Sbill /* 62926Swnj * TM03/TU?? tape driver 73094Swnj * 83094Swnj * TODO: 93204Swnj * cleanup messages on errors 103094Swnj * test ioctl's 113094Swnj * see how many rewind interrups we get if we kick when not at BOT 123204Swnj * fixup rle error on block tape code 1322Sbill */ 1422Sbill #include "../h/param.h" 1522Sbill #include "../h/systm.h" 1622Sbill #include "../h/buf.h" 1722Sbill #include "../h/conf.h" 1822Sbill #include "../h/dir.h" 1922Sbill #include "../h/file.h" 2022Sbill #include "../h/user.h" 2122Sbill #include "../h/map.h" 22420Sbill #include "../h/pte.h" 232980Swnj #include "../h/mbareg.h" 242980Swnj #include "../h/mbavar.h" 257636Ssam #include "../h/ioctl.h" 262926Swnj #include "../h/mtio.h" 271917Swnj #include "../h/cmap.h" 282961Swnj #include "../h/cpu.h" 29*7739Sroot #include "../h/uio.h" 3022Sbill 312926Swnj #include "../h/htreg.h" 3222Sbill 332926Swnj struct buf rhtbuf[NHT]; 342926Swnj struct buf chtbuf[NHT]; 3522Sbill 362926Swnj short httypes[] = 373181Swnj { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 382980Swnj struct mba_device *htinfo[NHT]; 393103Swnj int htattach(), htslave(), htustart(), htndtint(), htdtint(); 402926Swnj struct mba_driver htdriver = 412980Swnj { htattach, htslave, htustart, 0, htdtint, htndtint, 422980Swnj httypes, "ht", "tu", htinfo }; 4322Sbill 442926Swnj #define MASKREG(r) ((r) & 0xffff) 4522Sbill 462926Swnj /* bits in minor device */ 472980Swnj #define TUUNIT(dev) (minor(dev)&03) 482926Swnj #define H_NOREWIND 04 492926Swnj #define H_1600BPI 08 5022Sbill 513094Swnj #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) 522980Swnj 532926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 542926Swnj 553094Swnj struct tu_softc { 562926Swnj char sc_openf; 572926Swnj char sc_flags; 582926Swnj daddr_t sc_blkno; 592926Swnj daddr_t sc_nxrec; 602926Swnj u_short sc_erreg; 612926Swnj u_short sc_dsreg; 622926Swnj short sc_resid; 632926Swnj short sc_dens; 642980Swnj struct mba_device *sc_mi; 652980Swnj int sc_slave; 663094Swnj } tu_softc[NTU]; 673094Swnj short tutoht[NTU]; 682926Swnj 692926Swnj /* 702926Swnj * Bits for sc_flags. 712926Swnj */ 722926Swnj #define H_WRITTEN 1 /* last operation was a write */ 732926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 742926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 7522Sbill 763204Swnj char hter_bits[] = HTER_BITS; 773204Swnj char htds_bits[] = HTDS_BITS; 783204Swnj 792926Swnj /*ARGSUSED*/ 802980Swnj htattach(mi) 812980Swnj struct mba_device *mi; 822926Swnj { 832926Swnj 842926Swnj } 852926Swnj 867430Skre htslave(mi, ms, sn) 872980Swnj struct mba_device *mi; 882980Swnj struct mba_slave *ms; 897430Skre int sn; 902980Swnj { 913094Swnj register struct tu_softc *sc = &tu_softc[ms->ms_unit]; 924756Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 932980Swnj 947430Skre htaddr->httc = sn; 954756Swnj if (htaddr->htdt & HTDT_SPR) { 964756Swnj sc->sc_mi = mi; 977430Skre sc->sc_slave = sn; 984756Swnj tutoht[ms->ms_unit] = mi->mi_unit; 994756Swnj return (1); 1004756Swnj } else 1014756Swnj return (0); 1022980Swnj } 1032980Swnj 10422Sbill htopen(dev, flag) 1052926Swnj dev_t dev; 1062926Swnj int flag; 10722Sbill { 1083094Swnj register int tuunit; 1092980Swnj register struct mba_device *mi; 1103094Swnj register struct tu_softc *sc; 1113203Swnj int olddens, dens; 11222Sbill 1133094Swnj tuunit = TUUNIT(dev); 1143094Swnj if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || 1152980Swnj (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 11622Sbill u.u_error = ENXIO; 11722Sbill return; 11822Sbill } 1193203Swnj olddens = sc->sc_dens; 1203204Swnj dens = sc->sc_dens = 1213094Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| 1223094Swnj HTTC_PDP11|sc->sc_slave; 1233203Swnj htcommand(dev, HT_SENSE, 1); 1243203Swnj sc->sc_dens = olddens; 1253707Sroot if ((sc->sc_dsreg & HTDS_MOL) == 0) { 1263717Sroot uprintf("tu%d: not online\n", tuunit); 1272926Swnj u.u_error = EIO; 1282926Swnj return; 1292926Swnj } 1303707Sroot if ((flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL)) { 1313717Sroot uprintf("tu%d: no write ring\n", tuunit); 1323707Sroot u.u_error = EIO; 1333707Sroot return; 1343707Sroot } 1353707Sroot if ((sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && 1363707Sroot dens != sc->sc_dens) { 1373717Sroot uprintf("tu%d: can't change density in mid-tape\n", tuunit); 1383707Sroot u.u_error = EIO; 1393707Sroot return; 1403707Sroot } 1412926Swnj sc->sc_openf = 1; 1422926Swnj sc->sc_blkno = (daddr_t)0; 1432926Swnj sc->sc_nxrec = INF; 1442926Swnj sc->sc_flags = 0; 1453094Swnj sc->sc_dens = dens; 14622Sbill } 14722Sbill 14822Sbill htclose(dev, flag) 1492926Swnj register dev_t dev; 1502926Swnj register flag; 15122Sbill { 1523094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 15322Sbill 1542926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1552926Swnj htcommand(dev, HT_WEOF, 1); 1562926Swnj htcommand(dev, HT_WEOF, 1); 1572926Swnj htcommand(dev, HT_SREV, 1); 15822Sbill } 1592926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1602926Swnj htcommand(dev, HT_REW, 0); 1612926Swnj sc->sc_openf = 0; 16222Sbill } 16322Sbill 1642926Swnj htcommand(dev, com, count) 1652926Swnj dev_t dev; 1662926Swnj int com, count; 16722Sbill { 16822Sbill register struct buf *bp; 1695436Sroot register int s; 17022Sbill 1712926Swnj bp = &chtbuf[HTUNIT(dev)]; 1725436Sroot s = spl5(); 1732926Swnj while (bp->b_flags&B_BUSY) { 1743157Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1752980Swnj break; 17622Sbill bp->b_flags |= B_WANTED; 17722Sbill sleep((caddr_t)bp, PRIBIO); 17822Sbill } 1792943Swnj bp->b_flags = B_BUSY|B_READ; 1805436Sroot splx(s); 18122Sbill bp->b_dev = dev; 1822926Swnj bp->b_command = com; 1832926Swnj bp->b_repcnt = count; 18422Sbill bp->b_blkno = 0; 18522Sbill htstrategy(bp); 1862926Swnj if (count == 0) 1872926Swnj return; 18822Sbill iowait(bp); 1892926Swnj if (bp->b_flags&B_WANTED) 19022Sbill wakeup((caddr_t)bp); 1912926Swnj bp->b_flags &= B_ERROR; 19222Sbill } 19322Sbill 19422Sbill htstrategy(bp) 1952926Swnj register struct buf *bp; 19622Sbill { 1973094Swnj register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; 1982926Swnj register struct buf *dp; 1995436Sroot register int s; 20022Sbill 20122Sbill bp->av_forw = NULL; 2022926Swnj dp = &mi->mi_tab; 2035436Sroot s = spl5(); 2042926Swnj if (dp->b_actf == NULL) 2052926Swnj dp->b_actf = bp; 20622Sbill else 2072926Swnj dp->b_actl->av_forw = bp; 2082926Swnj dp->b_actl = bp; 2092926Swnj if (dp->b_active == 0) 2102926Swnj mbustart(mi); 2115436Sroot splx(s); 21222Sbill } 21322Sbill 2142926Swnj htustart(mi) 2152980Swnj register struct mba_device *mi; 21622Sbill { 2172926Swnj register struct htdevice *htaddr = 2182926Swnj (struct htdevice *)mi->mi_drv; 2192926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2203094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; 22122Sbill daddr_t blkno; 22222Sbill 2232926Swnj htaddr->httc = sc->sc_dens; 2243181Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { 2253157Swnj htaddr->htcs1 = HT_SENSE|HT_GO; 2263157Swnj mbclrattn(mi); 2273157Swnj } 2282926Swnj sc->sc_dsreg = htaddr->htds; 2292926Swnj sc->sc_erreg = htaddr->hter; 2302926Swnj sc->sc_resid = htaddr->htfc; 2312926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 2322926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 2332926Swnj if (sc->sc_openf > 0) 2342926Swnj sc->sc_openf = -1; 2352926Swnj if (sc->sc_openf < 0) { 2362926Swnj bp->b_flags |= B_ERROR; 2372926Swnj return (MBU_NEXT); 2382926Swnj } 2393094Swnj if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { 2407379Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2412926Swnj bp->b_flags |= B_ERROR; 2422926Swnj bp->b_error = ENXIO; 2432961Swnj return (MBU_NEXT); 2443094Swnj } 2457379Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 2462926Swnj bp->b_flags&B_READ) { 2472926Swnj bp->b_resid = bp->b_bcount; 2482926Swnj clrbuf(bp); 2492961Swnj return (MBU_NEXT); 2503094Swnj } 2513094Swnj if ((bp->b_flags&B_READ)==0) 2527379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 2532926Swnj } else { 2542961Swnj if (bp->b_command == HT_SENSE) 2552926Swnj return (MBU_NEXT); 2562926Swnj if (bp->b_command == HT_REW) 2572926Swnj sc->sc_flags |= H_REWIND; 2582926Swnj else 2592926Swnj htaddr->htfc = -bp->b_bcount; 2602926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 2612926Swnj return (MBU_STARTED); 2622926Swnj } 2637379Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 2642926Swnj htaddr->htfc = -bp->b_bcount; 2652926Swnj if ((bp->b_flags&B_READ) == 0) { 2663094Swnj if (mi->mi_tab.b_errcnt) { 2673094Swnj if ((sc->sc_flags & H_ERASED) == 0) { 2682926Swnj sc->sc_flags |= H_ERASED; 2692926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2702926Swnj return (MBU_STARTED); 2712926Swnj } 2723094Swnj sc->sc_flags &= ~H_ERASED; 2733094Swnj } 2742926Swnj if (htaddr->htds & HTDS_EOT) { 2752926Swnj bp->b_resid = bp->b_bcount; 2766812Swnj bp->b_flags |= B_ERROR; 2772926Swnj return (MBU_NEXT); 2782926Swnj } 27922Sbill } 2802926Swnj return (MBU_DODATA); 28122Sbill } 2827379Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 2837379Ssam htaddr->htfc = blkno - bdbtofsb(bp->b_blkno); 2842926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 28522Sbill } else { 2867379Ssam htaddr->htfc = bdbtofsb(bp->b_blkno) - blkno; 2872926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 28822Sbill } 2892926Swnj return (MBU_STARTED); 29022Sbill } 29122Sbill 2923094Swnj htdtint(mi, mbsr) 2932980Swnj register struct mba_device *mi; 2943094Swnj int mbsr; 29522Sbill { 2962926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2972926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2983094Swnj register struct tu_softc *sc; 2992961Swnj int ds, er, mbs; 30022Sbill 3013094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3022926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 3032926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 3042926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 3053094Swnj mbs = mbsr; 3062926Swnj sc->sc_blkno++; 3072926Swnj if((bp->b_flags & B_READ) == 0) 3082926Swnj sc->sc_flags |= H_WRITTEN; 3093094Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { 3102926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3112961Swnj mbclrattn(mi); 3122961Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { 3132926Swnj er &= ~HTER_FCE; 3143094Swnj mbs &= ~(MBSR_DTABT|MBSR_MBEXC); 3154276Sroot } 3162926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 3172926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 3183094Swnj if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || 3192961Swnj er && ++mi->mi_tab.b_errcnt >= 7) { 3202926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3212926Swnj sc->sc_openf = -1; 3223157Swnj if ((er&HTER_HARD) == HTER_FCE && 3233157Swnj (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && 3243157Swnj (ds&HTDS_MOL)) 3253157Swnj goto noprint; 3263204Swnj printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", 3272980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3283094Swnj mbsr, mbsr_bits, 3293204Swnj sc->sc_erreg, hter_bits, 3303204Swnj sc->sc_dsreg, htds_bits); 3313157Swnj noprint: 33222Sbill bp->b_flags |= B_ERROR; 3332926Swnj return (MBD_DONE); 33422Sbill } 3352926Swnj if (er) 3362926Swnj return (MBD_RETRY); 33722Sbill } 3382926Swnj bp->b_resid = 0; 3392926Swnj if (bp->b_flags & B_READ) 3402926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 3412926Swnj bp->b_resid = bp->b_bcount; 3427379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 3432926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 3442926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 3452926Swnj return (MBD_DONE); 3462926Swnj } 34722Sbill 3482926Swnj htndtint(mi) 3492980Swnj register struct mba_device *mi; 3502926Swnj { 3512926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3522926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3533094Swnj register struct tu_softc *sc; 3542926Swnj int er, ds, fc; 35522Sbill 3563094Swnj ds = MASKREG(htaddr->htds); 3573094Swnj er = MASKREG(htaddr->hter); 3583094Swnj fc = MASKREG(htaddr->htfc); 3593094Swnj if (er) { 3602926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3612961Swnj mbclrattn(mi); 3622961Swnj } 3633094Swnj if (bp == 0) 3643094Swnj return (MBN_SKIP); 3653094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3663094Swnj sc->sc_dsreg = ds; 3673094Swnj sc->sc_erreg = er; 3683094Swnj sc->sc_resid = fc; 3693094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3703094Swnj switch (bp->b_command) { 3713094Swnj case HT_REWOFFL: 3722926Swnj /* offline is on purpose; don't do anything special */ 3732926Swnj ds |= HTDS_MOL; 3743094Swnj break; 3753094Swnj case HT_SREV: 3763094Swnj /* if backspace file hit bot, its not an error */ 3773094Swnj if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && 3783094Swnj bp->b_repcnt == INF) 3793094Swnj er &= ~HTER_NEF; 3803094Swnj break; 3813094Swnj } 3822926Swnj er &= ~HTER_FCE; 3832926Swnj if (er == 0) 3842926Swnj ds &= ~HTDS_ERR; 38522Sbill } 3862926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3872926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3882926Swnj sc->sc_openf = -1; 3893204Swnj printf("tu%d: hard error bn%d er=%b ds=%b\n", 3902980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3913204Swnj sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); 3922926Swnj bp->b_flags |= B_ERROR; 3932926Swnj return (MBN_DONE); 3942926Swnj } 3953094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3962926Swnj if (sc->sc_flags & H_REWIND) 3972926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3982926Swnj bp->b_resid = -sc->sc_resid; 3992926Swnj return (MBN_DONE); 4002926Swnj } 4012926Swnj if (ds & HTDS_TM) 4027379Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4037379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) - fc; 4042926Swnj sc->sc_blkno = sc->sc_nxrec; 4053094Swnj } else { 4067379Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno) + fc; 4072926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4082926Swnj } 4092926Swnj else 4107379Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 4112926Swnj return (MBN_RETRY); 41222Sbill } 41322Sbill 414*7739Sroot htread(dev, uio) 4152926Swnj dev_t dev; 416*7739Sroot struct uio *uio; 41722Sbill { 4182926Swnj 419*7739Sroot u.u_error = htphys(dev, uio); 4202926Swnj if (u.u_error) 4212926Swnj return; 422*7739Sroot physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys, uio); 42322Sbill } 42422Sbill 42522Sbill htwrite(dev) 42622Sbill { 4272926Swnj 428*7739Sroot htphys(dev, 0); 4292926Swnj if (u.u_error) 4302926Swnj return; 431*7739Sroot physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys, 0); 43222Sbill } 43322Sbill 434*7739Sroot htphys(dev, uio) 4352926Swnj dev_t dev; 436*7739Sroot struct uio *uio; 43722Sbill { 4383094Swnj register int htunit; 4393094Swnj register struct tu_softc *sc; 4403094Swnj register struct mba_device *mi; 44122Sbill daddr_t a; 44222Sbill 4433094Swnj htunit = HTUNIT(dev); 4443094Swnj if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) { 4452926Swnj u.u_error = ENXIO; 446*7739Sroot return (ENXIO); 44722Sbill } 448*7739Sroot if (uio) 449*7739Sroot a = uio->uio_offset >> 9; 450*7739Sroot else 451*7739Sroot a = u.u_offset >> 9; 4523094Swnj sc = &tu_softc[TUUNIT(dev)]; 4537379Ssam sc->sc_blkno = bdbtofsb(a); 4547379Ssam sc->sc_nxrec = bdbtofsb(a)+1; 455*7739Sroot return (0); 45622Sbill } 4571917Swnj 4582926Swnj /*ARGSUSED*/ 4597636Ssam htioctl(dev, cmd, data, flag) 4602926Swnj dev_t dev; 4612926Swnj int cmd; 4627636Ssam caddr_t data; 4632926Swnj int flag; 4642926Swnj { 4653094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 4663094Swnj register struct buf *bp = &chtbuf[HTUNIT(dev)]; 4672926Swnj register callcount; 4682926Swnj int fcount; 4697636Ssam struct mtop *mtop; 4707636Ssam struct mtget *mtget; 4712926Swnj /* we depend of the values and order of the MT codes here */ 4722926Swnj static htops[] = 4732926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4741917Swnj 4752926Swnj switch (cmd) { 4767636Ssam 4777636Ssam case MTIOCTOP: /* tape operation */ 4787636Ssam mtop = (struct mtop *)data; 4797636Ssam switch (mtop->mt_op) { 4807636Ssam 4812926Swnj case MTWEOF: 4827636Ssam callcount = mtop->mt_count; 4832926Swnj fcount = 1; 4842926Swnj break; 4857636Ssam 4862926Swnj case MTFSF: case MTBSF: 4877636Ssam callcount = mtop->mt_count; 4882926Swnj fcount = INF; 4892926Swnj break; 4907636Ssam 4912926Swnj case MTFSR: case MTBSR: 4922926Swnj callcount = 1; 4937636Ssam fcount = mtop->mt_count; 4942926Swnj break; 4957636Ssam 4962926Swnj case MTREW: case MTOFFL: 4972926Swnj callcount = 1; 4982926Swnj fcount = 1; 4992926Swnj break; 5007636Ssam 5012926Swnj default: 5022926Swnj u.u_error = ENXIO; 5032926Swnj return; 5042926Swnj } 5052926Swnj if (callcount <= 0 || fcount <= 0) { 5062926Swnj u.u_error = ENXIO; 5072926Swnj return; 5082926Swnj } 5092926Swnj while (--callcount >= 0) { 5107636Ssam htcommand(dev, htops[mtop->mt_op], fcount); 5117636Ssam if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) && 5122926Swnj bp->b_resid) { 5132926Swnj u.u_error = EIO; 5142926Swnj break; 5152926Swnj } 5163094Swnj if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) 5172926Swnj break; 5182926Swnj } 5192926Swnj geterror(bp); 5202926Swnj return; 5217636Ssam 5222926Swnj case MTIOCGET: 5237636Ssam mtget = (struct mtget *)data; 5247636Ssam mtget->mt_dsreg = sc->sc_dsreg; 5257636Ssam mtget->mt_erreg = sc->sc_erreg; 5267636Ssam mtget->mt_resid = sc->sc_resid; 5277636Ssam mtget->mt_type = MT_ISHT; 5282926Swnj return; 5297636Ssam 5302926Swnj default: 5312926Swnj u.u_error = ENXIO; 5322926Swnj } 5332926Swnj } 5342926Swnj 5351917Swnj #define DBSIZE 20 5361917Swnj 5372926Swnj htdump() 5381917Swnj { 5392980Swnj register struct mba_device *mi; 5402926Swnj register struct mba_regs *mp; 5412926Swnj register struct htdevice *htaddr; 5422926Swnj int blk, num; 5432926Swnj int start; 5441917Swnj 5452926Swnj start = 0; 5462926Swnj num = maxfree; 5472926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5482926Swnj if (htinfo[0] == 0) 5492926Swnj return (ENXIO); 5502980Swnj mi = phys(htinfo[0], struct mba_device *); 5512926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5523157Swnj mp->mba_cr = MBCR_IE; 5532926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 5542926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 5552926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 5561917Swnj while (num > 0) { 5571917Swnj blk = num > DBSIZE ? DBSIZE : num; 5582926Swnj htdwrite(start, blk, htaddr, mp); 5592926Swnj start += blk; 5601917Swnj num -= blk; 5611917Swnj } 5623157Swnj hteof(htaddr); 5633157Swnj hteof(htaddr); 5642926Swnj htwait(htaddr); 5653181Swnj if (htaddr->htds&HTDS_ERR) 5663157Swnj return (EIO); 5672926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5683103Swnj return (0); 5691917Swnj } 5701917Swnj 5712926Swnj htdwrite(dbuf, num, htaddr, mp) 5722926Swnj register dbuf, num; 5732926Swnj register struct htdevice *htaddr; 5742926Swnj struct mba_regs *mp; 5751917Swnj { 5762926Swnj register struct pte *io; 5771917Swnj register int i; 5781917Swnj 5792926Swnj htwait(htaddr); 5802926Swnj io = mp->mba_map; 5811917Swnj for (i = 0; i < num; i++) 5822926Swnj *(int *)io++ = dbuf++ | PG_V; 5832926Swnj htaddr->htfc = -(num*NBPG); 5842926Swnj mp->mba_sr = -1; 5852926Swnj mp->mba_bcr = -(num*NBPG); 5862926Swnj mp->mba_var = 0; 5872926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5881917Swnj } 5891917Swnj 5902926Swnj htwait(htaddr) 5912926Swnj struct htdevice *htaddr; 5921917Swnj { 5931917Swnj register s; 5941917Swnj 5951917Swnj do 5962926Swnj s = htaddr->htds; 5972926Swnj while ((s & HTDS_DRY) == 0); 5981917Swnj } 5991917Swnj 6002926Swnj hteof(htaddr) 6012926Swnj struct htdevice *htaddr; 6021917Swnj { 6031917Swnj 6042926Swnj htwait(htaddr); 6052926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 6061917Swnj } 6071563Sbill #endif 608