1*5436Sroot /* ht.c 4.21 82/01/17 */ 22961Swnj 32980Swnj #include "tu.h" 41563Sbill #if NHT > 0 522Sbill /* 62926Swnj * TM03/TU?? tape driver 73094Swnj * 83094Swnj * TODO: 93204Swnj * cleanup messages on errors 103094Swnj * test ioctl's 113094Swnj * see how many rewind interrups we get if we kick when not at BOT 123204Swnj * fixup rle error on block tape code 1322Sbill */ 1422Sbill #include "../h/param.h" 1522Sbill #include "../h/systm.h" 1622Sbill #include "../h/buf.h" 1722Sbill #include "../h/conf.h" 1822Sbill #include "../h/dir.h" 1922Sbill #include "../h/file.h" 2022Sbill #include "../h/user.h" 2122Sbill #include "../h/map.h" 22420Sbill #include "../h/pte.h" 232980Swnj #include "../h/mbareg.h" 242980Swnj #include "../h/mbavar.h" 252926Swnj #include "../h/mtio.h" 262926Swnj #include "../h/ioctl.h" 271917Swnj #include "../h/cmap.h" 282961Swnj #include "../h/cpu.h" 2922Sbill 302926Swnj #include "../h/htreg.h" 3122Sbill 322926Swnj struct buf rhtbuf[NHT]; 332926Swnj struct buf chtbuf[NHT]; 3422Sbill 352926Swnj short httypes[] = 363181Swnj { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 372980Swnj struct mba_device *htinfo[NHT]; 383103Swnj int htattach(), htslave(), htustart(), htndtint(), htdtint(); 392926Swnj struct mba_driver htdriver = 402980Swnj { htattach, htslave, htustart, 0, htdtint, htndtint, 412980Swnj httypes, "ht", "tu", htinfo }; 4222Sbill 432926Swnj #define MASKREG(r) ((r) & 0xffff) 4422Sbill 452926Swnj /* bits in minor device */ 462980Swnj #define TUUNIT(dev) (minor(dev)&03) 472926Swnj #define H_NOREWIND 04 482926Swnj #define H_1600BPI 08 4922Sbill 503094Swnj #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) 512980Swnj 522926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 532926Swnj 543094Swnj struct tu_softc { 552926Swnj char sc_openf; 562926Swnj char sc_flags; 572926Swnj daddr_t sc_blkno; 582926Swnj daddr_t sc_nxrec; 592926Swnj u_short sc_erreg; 602926Swnj u_short sc_dsreg; 612926Swnj short sc_resid; 622926Swnj short sc_dens; 632980Swnj struct mba_device *sc_mi; 642980Swnj int sc_slave; 653094Swnj } tu_softc[NTU]; 663094Swnj short tutoht[NTU]; 672926Swnj 682926Swnj /* 692926Swnj * Bits for sc_flags. 702926Swnj */ 712926Swnj #define H_WRITTEN 1 /* last operation was a write */ 722926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 732926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 7422Sbill 753204Swnj char hter_bits[] = HTER_BITS; 763204Swnj char htds_bits[] = HTDS_BITS; 773204Swnj 782926Swnj /*ARGSUSED*/ 792980Swnj htattach(mi) 802980Swnj struct mba_device *mi; 812926Swnj { 822926Swnj 832926Swnj } 842926Swnj 852980Swnj htslave(mi, ms) 862980Swnj struct mba_device *mi; 872980Swnj struct mba_slave *ms; 882980Swnj { 893094Swnj register struct tu_softc *sc = &tu_softc[ms->ms_unit]; 904756Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 912980Swnj 924756Swnj htaddr->httc = ms->ms_slave; 934756Swnj if (htaddr->htdt & HTDT_SPR) { 944756Swnj sc->sc_mi = mi; 954756Swnj sc->sc_slave = ms->ms_slave; 964756Swnj tutoht[ms->ms_unit] = mi->mi_unit; 974756Swnj return (1); 984756Swnj } else 994756Swnj return (0); 1002980Swnj } 1012980Swnj 10222Sbill htopen(dev, flag) 1032926Swnj dev_t dev; 1042926Swnj int flag; 10522Sbill { 1063094Swnj register int tuunit; 1072980Swnj register struct mba_device *mi; 1083094Swnj register struct tu_softc *sc; 1093203Swnj int olddens, dens; 11022Sbill 1113094Swnj tuunit = TUUNIT(dev); 1123094Swnj if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || 1132980Swnj (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 11422Sbill u.u_error = ENXIO; 11522Sbill return; 11622Sbill } 1173203Swnj olddens = sc->sc_dens; 1183204Swnj dens = sc->sc_dens = 1193094Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| 1203094Swnj HTTC_PDP11|sc->sc_slave; 1213203Swnj htcommand(dev, HT_SENSE, 1); 1223203Swnj sc->sc_dens = olddens; 1233707Sroot if ((sc->sc_dsreg & HTDS_MOL) == 0) { 1243717Sroot uprintf("tu%d: not online\n", tuunit); 1252926Swnj u.u_error = EIO; 1262926Swnj return; 1272926Swnj } 1283707Sroot if ((flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL)) { 1293717Sroot uprintf("tu%d: no write ring\n", tuunit); 1303707Sroot u.u_error = EIO; 1313707Sroot return; 1323707Sroot } 1333707Sroot if ((sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && 1343707Sroot dens != sc->sc_dens) { 1353717Sroot uprintf("tu%d: can't change density in mid-tape\n", tuunit); 1363707Sroot u.u_error = EIO; 1373707Sroot return; 1383707Sroot } 1392926Swnj sc->sc_openf = 1; 1402926Swnj sc->sc_blkno = (daddr_t)0; 1412926Swnj sc->sc_nxrec = INF; 1422926Swnj sc->sc_flags = 0; 1433094Swnj sc->sc_dens = dens; 14422Sbill } 14522Sbill 14622Sbill htclose(dev, flag) 1472926Swnj register dev_t dev; 1482926Swnj register flag; 14922Sbill { 1503094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 15122Sbill 1522926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1532926Swnj htcommand(dev, HT_WEOF, 1); 1542926Swnj htcommand(dev, HT_WEOF, 1); 1552926Swnj htcommand(dev, HT_SREV, 1); 15622Sbill } 1572926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1582926Swnj htcommand(dev, HT_REW, 0); 1592926Swnj sc->sc_openf = 0; 16022Sbill } 16122Sbill 1622926Swnj htcommand(dev, com, count) 1632926Swnj dev_t dev; 1642926Swnj int com, count; 16522Sbill { 16622Sbill register struct buf *bp; 167*5436Sroot register int s; 16822Sbill 1692926Swnj bp = &chtbuf[HTUNIT(dev)]; 170*5436Sroot s = spl5(); 1712926Swnj while (bp->b_flags&B_BUSY) { 1723157Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1732980Swnj break; 17422Sbill bp->b_flags |= B_WANTED; 17522Sbill sleep((caddr_t)bp, PRIBIO); 17622Sbill } 1772943Swnj bp->b_flags = B_BUSY|B_READ; 178*5436Sroot splx(s); 17922Sbill bp->b_dev = dev; 1802926Swnj bp->b_command = com; 1812926Swnj bp->b_repcnt = count; 18222Sbill bp->b_blkno = 0; 18322Sbill htstrategy(bp); 1842926Swnj if (count == 0) 1852926Swnj return; 18622Sbill iowait(bp); 1872926Swnj if (bp->b_flags&B_WANTED) 18822Sbill wakeup((caddr_t)bp); 1892926Swnj bp->b_flags &= B_ERROR; 19022Sbill } 19122Sbill 19222Sbill htstrategy(bp) 1932926Swnj register struct buf *bp; 19422Sbill { 1953094Swnj register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; 1962926Swnj register struct buf *dp; 197*5436Sroot register int s; 19822Sbill 19922Sbill bp->av_forw = NULL; 2002926Swnj dp = &mi->mi_tab; 201*5436Sroot s = spl5(); 2022926Swnj if (dp->b_actf == NULL) 2032926Swnj dp->b_actf = bp; 20422Sbill else 2052926Swnj dp->b_actl->av_forw = bp; 2062926Swnj dp->b_actl = bp; 2072926Swnj if (dp->b_active == 0) 2082926Swnj mbustart(mi); 209*5436Sroot splx(s); 21022Sbill } 21122Sbill 2122926Swnj htustart(mi) 2132980Swnj register struct mba_device *mi; 21422Sbill { 2152926Swnj register struct htdevice *htaddr = 2162926Swnj (struct htdevice *)mi->mi_drv; 2172926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2183094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; 21922Sbill daddr_t blkno; 22022Sbill 2212926Swnj htaddr->httc = sc->sc_dens; 2223181Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { 2233157Swnj htaddr->htcs1 = HT_SENSE|HT_GO; 2243157Swnj mbclrattn(mi); 2253157Swnj } 2262926Swnj sc->sc_dsreg = htaddr->htds; 2272926Swnj sc->sc_erreg = htaddr->hter; 2282926Swnj sc->sc_resid = htaddr->htfc; 2292926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 2302926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 2312926Swnj if (sc->sc_openf > 0) 2322926Swnj sc->sc_openf = -1; 2332926Swnj if (sc->sc_openf < 0) { 2342926Swnj bp->b_flags |= B_ERROR; 2352926Swnj return (MBU_NEXT); 2362926Swnj } 2373094Swnj if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { 2382926Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2392926Swnj bp->b_flags |= B_ERROR; 2402926Swnj bp->b_error = ENXIO; 2412961Swnj return (MBU_NEXT); 2423094Swnj } 2433094Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 2442926Swnj bp->b_flags&B_READ) { 2452926Swnj bp->b_resid = bp->b_bcount; 2462926Swnj clrbuf(bp); 2472961Swnj return (MBU_NEXT); 2483094Swnj } 2493094Swnj if ((bp->b_flags&B_READ)==0) 2502926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 2512926Swnj } else { 2522961Swnj if (bp->b_command == HT_SENSE) 2532926Swnj return (MBU_NEXT); 2542926Swnj if (bp->b_command == HT_REW) 2552926Swnj sc->sc_flags |= H_REWIND; 2562926Swnj else 2572926Swnj htaddr->htfc = -bp->b_bcount; 2582926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 2592926Swnj return (MBU_STARTED); 2602926Swnj } 2612926Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 2622926Swnj htaddr->htfc = -bp->b_bcount; 2632926Swnj if ((bp->b_flags&B_READ) == 0) { 2643094Swnj if (mi->mi_tab.b_errcnt) { 2653094Swnj if ((sc->sc_flags & H_ERASED) == 0) { 2662926Swnj sc->sc_flags |= H_ERASED; 2672926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2682926Swnj return (MBU_STARTED); 2692926Swnj } 2703094Swnj sc->sc_flags &= ~H_ERASED; 2713094Swnj } 2722926Swnj if (htaddr->htds & HTDS_EOT) { 2732926Swnj bp->b_resid = bp->b_bcount; 2742926Swnj return (MBU_NEXT); 2752926Swnj } 27622Sbill } 2772926Swnj return (MBU_DODATA); 27822Sbill } 2792926Swnj if (blkno < dbtofsb(bp->b_blkno)) { 2802926Swnj htaddr->htfc = blkno - dbtofsb(bp->b_blkno); 2812926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 28222Sbill } else { 2832926Swnj htaddr->htfc = dbtofsb(bp->b_blkno) - blkno; 2842926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 28522Sbill } 2862926Swnj return (MBU_STARTED); 28722Sbill } 28822Sbill 2893094Swnj htdtint(mi, mbsr) 2902980Swnj register struct mba_device *mi; 2913094Swnj int mbsr; 29222Sbill { 2932926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2942926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2953094Swnj register struct tu_softc *sc; 2962961Swnj int ds, er, mbs; 29722Sbill 2983094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 2992926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 3002926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 3012926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 3023094Swnj mbs = mbsr; 3032926Swnj sc->sc_blkno++; 3042926Swnj if((bp->b_flags & B_READ) == 0) 3052926Swnj sc->sc_flags |= H_WRITTEN; 3063094Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { 3072926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3082961Swnj mbclrattn(mi); 3092961Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { 3102926Swnj er &= ~HTER_FCE; 3113094Swnj mbs &= ~(MBSR_DTABT|MBSR_MBEXC); 3124276Sroot } 3132926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 3142926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 3153094Swnj if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || 3162961Swnj er && ++mi->mi_tab.b_errcnt >= 7) { 3172926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3182926Swnj sc->sc_openf = -1; 3193157Swnj if ((er&HTER_HARD) == HTER_FCE && 3203157Swnj (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && 3213157Swnj (ds&HTDS_MOL)) 3223157Swnj goto noprint; 3233204Swnj printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", 3242980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3253094Swnj mbsr, mbsr_bits, 3263204Swnj sc->sc_erreg, hter_bits, 3273204Swnj sc->sc_dsreg, htds_bits); 3283157Swnj noprint: 32922Sbill bp->b_flags |= B_ERROR; 3302926Swnj return (MBD_DONE); 33122Sbill } 3322926Swnj if (er) 3332926Swnj return (MBD_RETRY); 33422Sbill } 3352926Swnj bp->b_resid = 0; 3362926Swnj if (bp->b_flags & B_READ) 3372926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 3382926Swnj bp->b_resid = bp->b_bcount; 3392926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 3402926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 3412926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 3422926Swnj return (MBD_DONE); 3432926Swnj } 34422Sbill 3452926Swnj htndtint(mi) 3462980Swnj register struct mba_device *mi; 3472926Swnj { 3482926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3492926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3503094Swnj register struct tu_softc *sc; 3512926Swnj int er, ds, fc; 35222Sbill 3533094Swnj ds = MASKREG(htaddr->htds); 3543094Swnj er = MASKREG(htaddr->hter); 3553094Swnj fc = MASKREG(htaddr->htfc); 3563094Swnj if (er) { 3572926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3582961Swnj mbclrattn(mi); 3592961Swnj } 3603094Swnj if (bp == 0) 3613094Swnj return (MBN_SKIP); 3623094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3633094Swnj sc->sc_dsreg = ds; 3643094Swnj sc->sc_erreg = er; 3653094Swnj sc->sc_resid = fc; 3663094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3673094Swnj switch (bp->b_command) { 3683094Swnj case HT_REWOFFL: 3692926Swnj /* offline is on purpose; don't do anything special */ 3702926Swnj ds |= HTDS_MOL; 3713094Swnj break; 3723094Swnj case HT_SREV: 3733094Swnj /* if backspace file hit bot, its not an error */ 3743094Swnj if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && 3753094Swnj bp->b_repcnt == INF) 3763094Swnj er &= ~HTER_NEF; 3773094Swnj break; 3783094Swnj } 3792926Swnj er &= ~HTER_FCE; 3802926Swnj if (er == 0) 3812926Swnj ds &= ~HTDS_ERR; 38222Sbill } 3832926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3842926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3852926Swnj sc->sc_openf = -1; 3863204Swnj printf("tu%d: hard error bn%d er=%b ds=%b\n", 3872980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3883204Swnj sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); 3892926Swnj bp->b_flags |= B_ERROR; 3902926Swnj return (MBN_DONE); 3912926Swnj } 3923094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3932926Swnj if (sc->sc_flags & H_REWIND) 3942926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3952926Swnj bp->b_resid = -sc->sc_resid; 3962926Swnj return (MBN_DONE); 3972926Swnj } 3982926Swnj if (ds & HTDS_TM) 3993094Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 4002926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc; 4012926Swnj sc->sc_blkno = sc->sc_nxrec; 4023094Swnj } else { 4032926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) + fc; 4042926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4052926Swnj } 4062926Swnj else 4072926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 4082926Swnj return (MBN_RETRY); 40922Sbill } 41022Sbill 41122Sbill htread(dev) 4122926Swnj dev_t dev; 41322Sbill { 4142926Swnj 41522Sbill htphys(dev); 4162926Swnj if (u.u_error) 4172926Swnj return; 4182926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys); 41922Sbill } 42022Sbill 42122Sbill htwrite(dev) 42222Sbill { 4232926Swnj 42422Sbill htphys(dev); 4252926Swnj if (u.u_error) 4262926Swnj return; 4272926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys); 42822Sbill } 42922Sbill 43022Sbill htphys(dev) 4312926Swnj dev_t dev; 43222Sbill { 4333094Swnj register int htunit; 4343094Swnj register struct tu_softc *sc; 4353094Swnj register struct mba_device *mi; 43622Sbill daddr_t a; 43722Sbill 4383094Swnj htunit = HTUNIT(dev); 4393094Swnj if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) { 4402926Swnj u.u_error = ENXIO; 4412926Swnj return; 44222Sbill } 4432926Swnj a = u.u_offset >> 9; 4443094Swnj sc = &tu_softc[TUUNIT(dev)]; 4452926Swnj sc->sc_blkno = dbtofsb(a); 4462926Swnj sc->sc_nxrec = dbtofsb(a)+1; 44722Sbill } 4481917Swnj 4492926Swnj /*ARGSUSED*/ 4502926Swnj htioctl(dev, cmd, addr, flag) 4512926Swnj dev_t dev; 4522926Swnj int cmd; 4532926Swnj caddr_t addr; 4542926Swnj int flag; 4552926Swnj { 4563094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 4573094Swnj register struct buf *bp = &chtbuf[HTUNIT(dev)]; 4582926Swnj register callcount; 4592926Swnj int fcount; 4602926Swnj struct mtop mtop; 4612926Swnj struct mtget mtget; 4622926Swnj /* we depend of the values and order of the MT codes here */ 4632926Swnj static htops[] = 4642926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4651917Swnj 4662926Swnj switch (cmd) { 4672926Swnj case MTIOCTOP: /* tape operation */ 4682926Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 4692926Swnj u.u_error = EFAULT; 4702926Swnj return; 4712926Swnj } 4722926Swnj switch(mtop.mt_op) { 4732926Swnj case MTWEOF: 4742926Swnj callcount = mtop.mt_count; 4752926Swnj fcount = 1; 4762926Swnj break; 4772926Swnj case MTFSF: case MTBSF: 4782926Swnj callcount = mtop.mt_count; 4792926Swnj fcount = INF; 4802926Swnj break; 4812926Swnj case MTFSR: case MTBSR: 4822926Swnj callcount = 1; 4832926Swnj fcount = mtop.mt_count; 4842926Swnj break; 4852926Swnj case MTREW: case MTOFFL: 4862926Swnj callcount = 1; 4872926Swnj fcount = 1; 4882926Swnj break; 4892926Swnj default: 4902926Swnj u.u_error = ENXIO; 4912926Swnj return; 4922926Swnj } 4932926Swnj if (callcount <= 0 || fcount <= 0) { 4942926Swnj u.u_error = ENXIO; 4952926Swnj return; 4962926Swnj } 4972926Swnj while (--callcount >= 0) { 4982926Swnj htcommand(dev, htops[mtop.mt_op], fcount); 4992926Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 5002926Swnj bp->b_resid) { 5012926Swnj u.u_error = EIO; 5022926Swnj break; 5032926Swnj } 5043094Swnj if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) 5052926Swnj break; 5062926Swnj } 5072926Swnj geterror(bp); 5082926Swnj return; 5092926Swnj case MTIOCGET: 5102926Swnj mtget.mt_dsreg = sc->sc_dsreg; 5112926Swnj mtget.mt_erreg = sc->sc_erreg; 5122926Swnj mtget.mt_resid = sc->sc_resid; 5133480Stoy mtget.mt_type = MT_ISHT; 5142926Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 5152926Swnj u.u_error = EFAULT; 5162926Swnj return; 5172926Swnj default: 5182926Swnj u.u_error = ENXIO; 5192926Swnj } 5202926Swnj } 5212926Swnj 5221917Swnj #define DBSIZE 20 5231917Swnj 5242926Swnj htdump() 5251917Swnj { 5262980Swnj register struct mba_device *mi; 5272926Swnj register struct mba_regs *mp; 5282926Swnj register struct htdevice *htaddr; 5292926Swnj int blk, num; 5302926Swnj int start; 5311917Swnj 5322926Swnj start = 0; 5332926Swnj num = maxfree; 5342926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5352926Swnj if (htinfo[0] == 0) 5362926Swnj return (ENXIO); 5372980Swnj mi = phys(htinfo[0], struct mba_device *); 5382926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5393157Swnj mp->mba_cr = MBCR_IE; 5402926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 5412926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 5422926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 5431917Swnj while (num > 0) { 5441917Swnj blk = num > DBSIZE ? DBSIZE : num; 5452926Swnj htdwrite(start, blk, htaddr, mp); 5462926Swnj start += blk; 5471917Swnj num -= blk; 5481917Swnj } 5493157Swnj hteof(htaddr); 5503157Swnj hteof(htaddr); 5512926Swnj htwait(htaddr); 5523181Swnj if (htaddr->htds&HTDS_ERR) 5533157Swnj return (EIO); 5542926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5553103Swnj return (0); 5561917Swnj } 5571917Swnj 5582926Swnj htdwrite(dbuf, num, htaddr, mp) 5592926Swnj register dbuf, num; 5602926Swnj register struct htdevice *htaddr; 5612926Swnj struct mba_regs *mp; 5621917Swnj { 5632926Swnj register struct pte *io; 5641917Swnj register int i; 5651917Swnj 5662926Swnj htwait(htaddr); 5672926Swnj io = mp->mba_map; 5681917Swnj for (i = 0; i < num; i++) 5692926Swnj *(int *)io++ = dbuf++ | PG_V; 5702926Swnj htaddr->htfc = -(num*NBPG); 5712926Swnj mp->mba_sr = -1; 5722926Swnj mp->mba_bcr = -(num*NBPG); 5732926Swnj mp->mba_var = 0; 5742926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5751917Swnj } 5761917Swnj 5772926Swnj htwait(htaddr) 5782926Swnj struct htdevice *htaddr; 5791917Swnj { 5801917Swnj register s; 5811917Swnj 5821917Swnj do 5832926Swnj s = htaddr->htds; 5842926Swnj while ((s & HTDS_DRY) == 0); 5851917Swnj } 5861917Swnj 5872926Swnj hteof(htaddr) 5882926Swnj struct htdevice *htaddr; 5891917Swnj { 5901917Swnj 5912926Swnj htwait(htaddr); 5922926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 5931917Swnj } 5941563Sbill #endif 595