1*4276Sroot /* ht.c 4.19 81/08/31 */ 22961Swnj 32980Swnj #include "tu.h" 41563Sbill #if NHT > 0 522Sbill /* 62926Swnj * TM03/TU?? tape driver 73094Swnj * 83094Swnj * TODO: 93204Swnj * cleanup messages on errors 103094Swnj * test ioctl's 113094Swnj * see how many rewind interrups we get if we kick when not at BOT 123204Swnj * fixup rle error on block tape code 1322Sbill */ 1422Sbill #include "../h/param.h" 1522Sbill #include "../h/systm.h" 1622Sbill #include "../h/buf.h" 1722Sbill #include "../h/conf.h" 1822Sbill #include "../h/dir.h" 1922Sbill #include "../h/file.h" 2022Sbill #include "../h/user.h" 2122Sbill #include "../h/map.h" 22420Sbill #include "../h/pte.h" 232980Swnj #include "../h/mbareg.h" 242980Swnj #include "../h/mbavar.h" 252926Swnj #include "../h/mtio.h" 262926Swnj #include "../h/ioctl.h" 271917Swnj #include "../h/cmap.h" 282961Swnj #include "../h/cpu.h" 2922Sbill 302926Swnj #include "../h/htreg.h" 3122Sbill 322926Swnj struct buf rhtbuf[NHT]; 332926Swnj struct buf chtbuf[NHT]; 3422Sbill 352926Swnj short httypes[] = 363181Swnj { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 372980Swnj struct mba_device *htinfo[NHT]; 383103Swnj int htattach(), htslave(), htustart(), htndtint(), htdtint(); 392926Swnj struct mba_driver htdriver = 402980Swnj { htattach, htslave, htustart, 0, htdtint, htndtint, 412980Swnj httypes, "ht", "tu", htinfo }; 4222Sbill 432926Swnj #define MASKREG(r) ((r) & 0xffff) 4422Sbill 452926Swnj /* bits in minor device */ 462980Swnj #define TUUNIT(dev) (minor(dev)&03) 472926Swnj #define H_NOREWIND 04 482926Swnj #define H_1600BPI 08 4922Sbill 503094Swnj #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) 512980Swnj 522926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 532926Swnj 543094Swnj struct tu_softc { 552926Swnj char sc_openf; 562926Swnj char sc_flags; 572926Swnj daddr_t sc_blkno; 582926Swnj daddr_t sc_nxrec; 592926Swnj u_short sc_erreg; 602926Swnj u_short sc_dsreg; 612926Swnj short sc_resid; 622926Swnj short sc_dens; 632980Swnj struct mba_device *sc_mi; 642980Swnj int sc_slave; 653094Swnj } tu_softc[NTU]; 663094Swnj short tutoht[NTU]; 672926Swnj 682926Swnj /* 692926Swnj * Bits for sc_flags. 702926Swnj */ 712926Swnj #define H_WRITTEN 1 /* last operation was a write */ 722926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 732926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 7422Sbill 753204Swnj char hter_bits[] = HTER_BITS; 763204Swnj char htds_bits[] = HTDS_BITS; 773204Swnj 782926Swnj /*ARGSUSED*/ 792980Swnj htattach(mi) 802980Swnj struct mba_device *mi; 812926Swnj { 822926Swnj 832926Swnj } 842926Swnj 852980Swnj htslave(mi, ms) 862980Swnj struct mba_device *mi; 872980Swnj struct mba_slave *ms; 882980Swnj { 893094Swnj register struct tu_softc *sc = &tu_softc[ms->ms_unit]; 902980Swnj 912980Swnj sc->sc_mi = mi; 922980Swnj sc->sc_slave = ms->ms_slave; 933094Swnj tutoht[ms->ms_unit] = mi->mi_unit; 942980Swnj } 952980Swnj 9622Sbill htopen(dev, flag) 972926Swnj dev_t dev; 982926Swnj int flag; 9922Sbill { 1003094Swnj register int tuunit; 1012980Swnj register struct mba_device *mi; 1023094Swnj register struct tu_softc *sc; 1033203Swnj int olddens, dens; 10422Sbill 1053094Swnj tuunit = TUUNIT(dev); 1063094Swnj if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || 1072980Swnj (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 10822Sbill u.u_error = ENXIO; 10922Sbill return; 11022Sbill } 1113203Swnj olddens = sc->sc_dens; 1123204Swnj dens = sc->sc_dens = 1133094Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| 1143094Swnj HTTC_PDP11|sc->sc_slave; 1153203Swnj htcommand(dev, HT_SENSE, 1); 1163203Swnj sc->sc_dens = olddens; 1173707Sroot if ((sc->sc_dsreg & HTDS_MOL) == 0) { 1183717Sroot uprintf("tu%d: not online\n", tuunit); 1192926Swnj u.u_error = EIO; 1202926Swnj return; 1212926Swnj } 1223707Sroot if ((flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL)) { 1233717Sroot uprintf("tu%d: no write ring\n", tuunit); 1243707Sroot u.u_error = EIO; 1253707Sroot return; 1263707Sroot } 1273707Sroot if ((sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && 1283707Sroot dens != sc->sc_dens) { 1293717Sroot uprintf("tu%d: can't change density in mid-tape\n", tuunit); 1303707Sroot u.u_error = EIO; 1313707Sroot return; 1323707Sroot } 1332926Swnj sc->sc_openf = 1; 1342926Swnj sc->sc_blkno = (daddr_t)0; 1352926Swnj sc->sc_nxrec = INF; 1362926Swnj sc->sc_flags = 0; 1373094Swnj sc->sc_dens = dens; 13822Sbill } 13922Sbill 14022Sbill htclose(dev, flag) 1412926Swnj register dev_t dev; 1422926Swnj register flag; 14322Sbill { 1443094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 14522Sbill 1462926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1472926Swnj htcommand(dev, HT_WEOF, 1); 1482926Swnj htcommand(dev, HT_WEOF, 1); 1492926Swnj htcommand(dev, HT_SREV, 1); 15022Sbill } 1512926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1522926Swnj htcommand(dev, HT_REW, 0); 1532926Swnj sc->sc_openf = 0; 15422Sbill } 15522Sbill 1562926Swnj htcommand(dev, com, count) 1572926Swnj dev_t dev; 1582926Swnj int com, count; 15922Sbill { 16022Sbill register struct buf *bp; 16122Sbill 1622926Swnj bp = &chtbuf[HTUNIT(dev)]; 163128Sbill (void) spl5(); 1642926Swnj while (bp->b_flags&B_BUSY) { 1653157Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1662980Swnj break; 16722Sbill bp->b_flags |= B_WANTED; 16822Sbill sleep((caddr_t)bp, PRIBIO); 16922Sbill } 1702943Swnj bp->b_flags = B_BUSY|B_READ; 171128Sbill (void) spl0(); 17222Sbill bp->b_dev = dev; 1732926Swnj bp->b_command = com; 1742926Swnj bp->b_repcnt = count; 17522Sbill bp->b_blkno = 0; 17622Sbill htstrategy(bp); 1772926Swnj if (count == 0) 1782926Swnj return; 17922Sbill iowait(bp); 1802926Swnj if (bp->b_flags&B_WANTED) 18122Sbill wakeup((caddr_t)bp); 1822926Swnj bp->b_flags &= B_ERROR; 18322Sbill } 18422Sbill 18522Sbill htstrategy(bp) 1862926Swnj register struct buf *bp; 18722Sbill { 1883094Swnj register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; 1892926Swnj register struct buf *dp; 19022Sbill 19122Sbill bp->av_forw = NULL; 1922926Swnj dp = &mi->mi_tab; 193128Sbill (void) spl5(); 1942926Swnj if (dp->b_actf == NULL) 1952926Swnj dp->b_actf = bp; 19622Sbill else 1972926Swnj dp->b_actl->av_forw = bp; 1982926Swnj dp->b_actl = bp; 1992926Swnj if (dp->b_active == 0) 2002926Swnj mbustart(mi); 201128Sbill (void) spl0(); 20222Sbill } 20322Sbill 2042926Swnj htustart(mi) 2052980Swnj register struct mba_device *mi; 20622Sbill { 2072926Swnj register struct htdevice *htaddr = 2082926Swnj (struct htdevice *)mi->mi_drv; 2092926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2103094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; 21122Sbill daddr_t blkno; 21222Sbill 2132926Swnj htaddr->httc = sc->sc_dens; 2143181Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { 2153157Swnj htaddr->htcs1 = HT_SENSE|HT_GO; 2163157Swnj mbclrattn(mi); 2173157Swnj } 2182926Swnj sc->sc_dsreg = htaddr->htds; 2192926Swnj sc->sc_erreg = htaddr->hter; 2202926Swnj sc->sc_resid = htaddr->htfc; 2212926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 2222926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 2232926Swnj if (sc->sc_openf > 0) 2242926Swnj sc->sc_openf = -1; 2252926Swnj if (sc->sc_openf < 0) { 2262926Swnj bp->b_flags |= B_ERROR; 2272926Swnj return (MBU_NEXT); 2282926Swnj } 2293094Swnj if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { 2302926Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2312926Swnj bp->b_flags |= B_ERROR; 2322926Swnj bp->b_error = ENXIO; 2332961Swnj return (MBU_NEXT); 2343094Swnj } 2353094Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 2362926Swnj bp->b_flags&B_READ) { 2372926Swnj bp->b_resid = bp->b_bcount; 2382926Swnj clrbuf(bp); 2392961Swnj return (MBU_NEXT); 2403094Swnj } 2413094Swnj if ((bp->b_flags&B_READ)==0) 2422926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 2432926Swnj } else { 2442961Swnj if (bp->b_command == HT_SENSE) 2452926Swnj return (MBU_NEXT); 2462926Swnj if (bp->b_command == HT_REW) 2472926Swnj sc->sc_flags |= H_REWIND; 2482926Swnj else 2492926Swnj htaddr->htfc = -bp->b_bcount; 2502926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 2512926Swnj return (MBU_STARTED); 2522926Swnj } 2532926Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 2542926Swnj htaddr->htfc = -bp->b_bcount; 2552926Swnj if ((bp->b_flags&B_READ) == 0) { 2563094Swnj if (mi->mi_tab.b_errcnt) { 2573094Swnj if ((sc->sc_flags & H_ERASED) == 0) { 2582926Swnj sc->sc_flags |= H_ERASED; 2592926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2602926Swnj return (MBU_STARTED); 2612926Swnj } 2623094Swnj sc->sc_flags &= ~H_ERASED; 2633094Swnj } 2642926Swnj if (htaddr->htds & HTDS_EOT) { 2652926Swnj bp->b_resid = bp->b_bcount; 2662926Swnj return (MBU_NEXT); 2672926Swnj } 26822Sbill } 2692926Swnj return (MBU_DODATA); 27022Sbill } 2712926Swnj if (blkno < dbtofsb(bp->b_blkno)) { 2722926Swnj htaddr->htfc = blkno - dbtofsb(bp->b_blkno); 2732926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 27422Sbill } else { 2752926Swnj htaddr->htfc = dbtofsb(bp->b_blkno) - blkno; 2762926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 27722Sbill } 2782926Swnj return (MBU_STARTED); 27922Sbill } 28022Sbill 2813094Swnj htdtint(mi, mbsr) 2822980Swnj register struct mba_device *mi; 2833094Swnj int mbsr; 28422Sbill { 2852926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2862926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2873094Swnj register struct tu_softc *sc; 2882961Swnj int ds, er, mbs; 28922Sbill 2903094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 2912926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 2922926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 2932926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 2943094Swnj mbs = mbsr; 2952926Swnj sc->sc_blkno++; 2962926Swnj if((bp->b_flags & B_READ) == 0) 2972926Swnj sc->sc_flags |= H_WRITTEN; 2983094Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { 2992926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3002961Swnj mbclrattn(mi); 3012961Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { 3022926Swnj er &= ~HTER_FCE; 3033094Swnj mbs &= ~(MBSR_DTABT|MBSR_MBEXC); 304*4276Sroot } 3052926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 3062926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 3073094Swnj if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || 3082961Swnj er && ++mi->mi_tab.b_errcnt >= 7) { 3092926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3102926Swnj sc->sc_openf = -1; 3113157Swnj if ((er&HTER_HARD) == HTER_FCE && 3123157Swnj (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && 3133157Swnj (ds&HTDS_MOL)) 3143157Swnj goto noprint; 3153204Swnj printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", 3162980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3173094Swnj mbsr, mbsr_bits, 3183204Swnj sc->sc_erreg, hter_bits, 3193204Swnj sc->sc_dsreg, htds_bits); 3203157Swnj noprint: 32122Sbill bp->b_flags |= B_ERROR; 3222926Swnj return (MBD_DONE); 32322Sbill } 3242926Swnj if (er) 3252926Swnj return (MBD_RETRY); 32622Sbill } 3272926Swnj bp->b_resid = 0; 3282926Swnj if (bp->b_flags & B_READ) 3292926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 3302926Swnj bp->b_resid = bp->b_bcount; 3312926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 3322926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 3332926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 3342926Swnj return (MBD_DONE); 3352926Swnj } 33622Sbill 3372926Swnj htndtint(mi) 3382980Swnj register struct mba_device *mi; 3392926Swnj { 3402926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3412926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3423094Swnj register struct tu_softc *sc; 3432926Swnj int er, ds, fc; 34422Sbill 3453094Swnj ds = MASKREG(htaddr->htds); 3463094Swnj er = MASKREG(htaddr->hter); 3473094Swnj fc = MASKREG(htaddr->htfc); 3483094Swnj if (er) { 3492926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3502961Swnj mbclrattn(mi); 3512961Swnj } 3523094Swnj if (bp == 0) 3533094Swnj return (MBN_SKIP); 3543094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3553094Swnj sc->sc_dsreg = ds; 3563094Swnj sc->sc_erreg = er; 3573094Swnj sc->sc_resid = fc; 3583094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3593094Swnj switch (bp->b_command) { 3603094Swnj case HT_REWOFFL: 3612926Swnj /* offline is on purpose; don't do anything special */ 3622926Swnj ds |= HTDS_MOL; 3633094Swnj break; 3643094Swnj case HT_SREV: 3653094Swnj /* if backspace file hit bot, its not an error */ 3663094Swnj if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && 3673094Swnj bp->b_repcnt == INF) 3683094Swnj er &= ~HTER_NEF; 3693094Swnj break; 3703094Swnj } 3712926Swnj er &= ~HTER_FCE; 3722926Swnj if (er == 0) 3732926Swnj ds &= ~HTDS_ERR; 37422Sbill } 3752926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3762926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3772926Swnj sc->sc_openf = -1; 3783204Swnj printf("tu%d: hard error bn%d er=%b ds=%b\n", 3792980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3803204Swnj sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); 3812926Swnj bp->b_flags |= B_ERROR; 3822926Swnj return (MBN_DONE); 3832926Swnj } 3843094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3852926Swnj if (sc->sc_flags & H_REWIND) 3862926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3872926Swnj bp->b_resid = -sc->sc_resid; 3882926Swnj return (MBN_DONE); 3892926Swnj } 3902926Swnj if (ds & HTDS_TM) 3913094Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 3922926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc; 3932926Swnj sc->sc_blkno = sc->sc_nxrec; 3943094Swnj } else { 3952926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) + fc; 3962926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 3972926Swnj } 3982926Swnj else 3992926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 4002926Swnj return (MBN_RETRY); 40122Sbill } 40222Sbill 40322Sbill htread(dev) 4042926Swnj dev_t dev; 40522Sbill { 4062926Swnj 40722Sbill htphys(dev); 4082926Swnj if (u.u_error) 4092926Swnj return; 4102926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys); 41122Sbill } 41222Sbill 41322Sbill htwrite(dev) 41422Sbill { 4152926Swnj 41622Sbill htphys(dev); 4172926Swnj if (u.u_error) 4182926Swnj return; 4192926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys); 42022Sbill } 42122Sbill 42222Sbill htphys(dev) 4232926Swnj dev_t dev; 42422Sbill { 4253094Swnj register int htunit; 4263094Swnj register struct tu_softc *sc; 4273094Swnj register struct mba_device *mi; 42822Sbill daddr_t a; 42922Sbill 4303094Swnj htunit = HTUNIT(dev); 4313094Swnj if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) { 4322926Swnj u.u_error = ENXIO; 4332926Swnj return; 43422Sbill } 4352926Swnj a = u.u_offset >> 9; 4363094Swnj sc = &tu_softc[TUUNIT(dev)]; 4372926Swnj sc->sc_blkno = dbtofsb(a); 4382926Swnj sc->sc_nxrec = dbtofsb(a)+1; 43922Sbill } 4401917Swnj 4412926Swnj /*ARGSUSED*/ 4422926Swnj htioctl(dev, cmd, addr, flag) 4432926Swnj dev_t dev; 4442926Swnj int cmd; 4452926Swnj caddr_t addr; 4462926Swnj int flag; 4472926Swnj { 4483094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 4493094Swnj register struct buf *bp = &chtbuf[HTUNIT(dev)]; 4502926Swnj register callcount; 4512926Swnj int fcount; 4522926Swnj struct mtop mtop; 4532926Swnj struct mtget mtget; 4542926Swnj /* we depend of the values and order of the MT codes here */ 4552926Swnj static htops[] = 4562926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4571917Swnj 4582926Swnj switch (cmd) { 4592926Swnj case MTIOCTOP: /* tape operation */ 4602926Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 4612926Swnj u.u_error = EFAULT; 4622926Swnj return; 4632926Swnj } 4642926Swnj switch(mtop.mt_op) { 4652926Swnj case MTWEOF: 4662926Swnj callcount = mtop.mt_count; 4672926Swnj fcount = 1; 4682926Swnj break; 4692926Swnj case MTFSF: case MTBSF: 4702926Swnj callcount = mtop.mt_count; 4712926Swnj fcount = INF; 4722926Swnj break; 4732926Swnj case MTFSR: case MTBSR: 4742926Swnj callcount = 1; 4752926Swnj fcount = mtop.mt_count; 4762926Swnj break; 4772926Swnj case MTREW: case MTOFFL: 4782926Swnj callcount = 1; 4792926Swnj fcount = 1; 4802926Swnj break; 4812926Swnj default: 4822926Swnj u.u_error = ENXIO; 4832926Swnj return; 4842926Swnj } 4852926Swnj if (callcount <= 0 || fcount <= 0) { 4862926Swnj u.u_error = ENXIO; 4872926Swnj return; 4882926Swnj } 4892926Swnj while (--callcount >= 0) { 4902926Swnj htcommand(dev, htops[mtop.mt_op], fcount); 4912926Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 4922926Swnj bp->b_resid) { 4932926Swnj u.u_error = EIO; 4942926Swnj break; 4952926Swnj } 4963094Swnj if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) 4972926Swnj break; 4982926Swnj } 4992926Swnj geterror(bp); 5002926Swnj return; 5012926Swnj case MTIOCGET: 5022926Swnj mtget.mt_dsreg = sc->sc_dsreg; 5032926Swnj mtget.mt_erreg = sc->sc_erreg; 5042926Swnj mtget.mt_resid = sc->sc_resid; 5053480Stoy mtget.mt_type = MT_ISHT; 5062926Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 5072926Swnj u.u_error = EFAULT; 5082926Swnj return; 5092926Swnj default: 5102926Swnj u.u_error = ENXIO; 5112926Swnj } 5122926Swnj } 5132926Swnj 5141917Swnj #define DBSIZE 20 5151917Swnj 5162926Swnj htdump() 5171917Swnj { 5182980Swnj register struct mba_device *mi; 5192926Swnj register struct mba_regs *mp; 5202926Swnj register struct htdevice *htaddr; 5212926Swnj int blk, num; 5222926Swnj int start; 5231917Swnj 5242926Swnj start = 0; 5252926Swnj num = maxfree; 5262926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5272926Swnj if (htinfo[0] == 0) 5282926Swnj return (ENXIO); 5292980Swnj mi = phys(htinfo[0], struct mba_device *); 5302926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5313157Swnj mp->mba_cr = MBCR_IE; 5322926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 5332926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 5342926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 5351917Swnj while (num > 0) { 5361917Swnj blk = num > DBSIZE ? DBSIZE : num; 5372926Swnj htdwrite(start, blk, htaddr, mp); 5382926Swnj start += blk; 5391917Swnj num -= blk; 5401917Swnj } 5413157Swnj hteof(htaddr); 5423157Swnj hteof(htaddr); 5432926Swnj htwait(htaddr); 5443181Swnj if (htaddr->htds&HTDS_ERR) 5453157Swnj return (EIO); 5462926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5473103Swnj return (0); 5481917Swnj } 5491917Swnj 5502926Swnj htdwrite(dbuf, num, htaddr, mp) 5512926Swnj register dbuf, num; 5522926Swnj register struct htdevice *htaddr; 5532926Swnj struct mba_regs *mp; 5541917Swnj { 5552926Swnj register struct pte *io; 5561917Swnj register int i; 5571917Swnj 5582926Swnj htwait(htaddr); 5592926Swnj io = mp->mba_map; 5601917Swnj for (i = 0; i < num; i++) 5612926Swnj *(int *)io++ = dbuf++ | PG_V; 5622926Swnj htaddr->htfc = -(num*NBPG); 5632926Swnj mp->mba_sr = -1; 5642926Swnj mp->mba_bcr = -(num*NBPG); 5652926Swnj mp->mba_var = 0; 5662926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5671917Swnj } 5681917Swnj 5692926Swnj htwait(htaddr) 5702926Swnj struct htdevice *htaddr; 5711917Swnj { 5721917Swnj register s; 5731917Swnj 5741917Swnj do 5752926Swnj s = htaddr->htds; 5762926Swnj while ((s & HTDS_DRY) == 0); 5771917Swnj } 5781917Swnj 5792926Swnj hteof(htaddr) 5802926Swnj struct htdevice *htaddr; 5811917Swnj { 5821917Swnj 5832926Swnj htwait(htaddr); 5842926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 5851917Swnj } 5861563Sbill #endif 587