1*3480Stoy /* ht.c 4.16 81/04/03 */ 22961Swnj 32980Swnj #include "tu.h" 41563Sbill #if NHT > 0 522Sbill /* 62926Swnj * TM03/TU?? tape driver 73094Swnj * 83094Swnj * TODO: 93204Swnj * cleanup messages on errors 103094Swnj * test ioctl's 113094Swnj * see how many rewind interrups we get if we kick when not at BOT 123204Swnj * fixup rle error on block tape code 1322Sbill */ 1422Sbill #include "../h/param.h" 1522Sbill #include "../h/systm.h" 1622Sbill #include "../h/buf.h" 1722Sbill #include "../h/conf.h" 1822Sbill #include "../h/dir.h" 1922Sbill #include "../h/file.h" 2022Sbill #include "../h/user.h" 2122Sbill #include "../h/map.h" 22420Sbill #include "../h/pte.h" 232980Swnj #include "../h/mbareg.h" 242980Swnj #include "../h/mbavar.h" 252926Swnj #include "../h/mtio.h" 262926Swnj #include "../h/ioctl.h" 271917Swnj #include "../h/cmap.h" 282961Swnj #include "../h/cpu.h" 2922Sbill 302926Swnj #include "../h/htreg.h" 3122Sbill 322926Swnj struct buf rhtbuf[NHT]; 332926Swnj struct buf chtbuf[NHT]; 3422Sbill 352926Swnj short httypes[] = 363181Swnj { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 372980Swnj struct mba_device *htinfo[NHT]; 383103Swnj int htattach(), htslave(), htustart(), htndtint(), htdtint(); 392926Swnj struct mba_driver htdriver = 402980Swnj { htattach, htslave, htustart, 0, htdtint, htndtint, 412980Swnj httypes, "ht", "tu", htinfo }; 4222Sbill 432926Swnj #define MASKREG(r) ((r) & 0xffff) 4422Sbill 452926Swnj /* bits in minor device */ 462980Swnj #define TUUNIT(dev) (minor(dev)&03) 472926Swnj #define H_NOREWIND 04 482926Swnj #define H_1600BPI 08 4922Sbill 503094Swnj #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) 512980Swnj 522926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 532926Swnj 543094Swnj struct tu_softc { 552926Swnj char sc_openf; 562926Swnj char sc_flags; 572926Swnj daddr_t sc_blkno; 582926Swnj daddr_t sc_nxrec; 592926Swnj u_short sc_erreg; 602926Swnj u_short sc_dsreg; 612926Swnj short sc_resid; 622926Swnj short sc_dens; 632980Swnj struct mba_device *sc_mi; 642980Swnj int sc_slave; 653094Swnj } tu_softc[NTU]; 663094Swnj short tutoht[NTU]; 672926Swnj 682926Swnj /* 692926Swnj * Bits for sc_flags. 702926Swnj */ 712926Swnj #define H_WRITTEN 1 /* last operation was a write */ 722926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 732926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 7422Sbill 753204Swnj char hter_bits[] = HTER_BITS; 763204Swnj char htds_bits[] = HTDS_BITS; 773204Swnj 782926Swnj /*ARGSUSED*/ 792980Swnj htattach(mi) 802980Swnj struct mba_device *mi; 812926Swnj { 822926Swnj 832926Swnj } 842926Swnj 852980Swnj htslave(mi, ms) 862980Swnj struct mba_device *mi; 872980Swnj struct mba_slave *ms; 882980Swnj { 893094Swnj register struct tu_softc *sc = &tu_softc[ms->ms_unit]; 902980Swnj 912980Swnj sc->sc_mi = mi; 922980Swnj sc->sc_slave = ms->ms_slave; 933094Swnj tutoht[ms->ms_unit] = mi->mi_unit; 942980Swnj } 952980Swnj 9622Sbill htopen(dev, flag) 972926Swnj dev_t dev; 982926Swnj int flag; 9922Sbill { 1003094Swnj register int tuunit; 1012980Swnj register struct mba_device *mi; 1023094Swnj register struct tu_softc *sc; 1033203Swnj int olddens, dens; 10422Sbill 1053094Swnj tuunit = TUUNIT(dev); 1063094Swnj if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || 1072980Swnj (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) { 10822Sbill u.u_error = ENXIO; 10922Sbill return; 11022Sbill } 1113203Swnj olddens = sc->sc_dens; 1123204Swnj dens = sc->sc_dens = 1133094Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| 1143094Swnj HTTC_PDP11|sc->sc_slave; 1153203Swnj htcommand(dev, HT_SENSE, 1); 1163203Swnj sc->sc_dens = olddens; 1172926Swnj if ((sc->sc_dsreg & HTDS_MOL) == 0 || 1183157Swnj (flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL) || 1193094Swnj (sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && 1203157Swnj dens != sc->sc_dens) { 1212926Swnj u.u_error = EIO; 1222926Swnj return; 1232926Swnj } 1242926Swnj sc->sc_openf = 1; 1252926Swnj sc->sc_blkno = (daddr_t)0; 1262926Swnj sc->sc_nxrec = INF; 1272926Swnj sc->sc_flags = 0; 1283094Swnj sc->sc_dens = dens; 12922Sbill } 13022Sbill 13122Sbill htclose(dev, flag) 1322926Swnj register dev_t dev; 1332926Swnj register flag; 13422Sbill { 1353094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 13622Sbill 1372926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1382926Swnj htcommand(dev, HT_WEOF, 1); 1392926Swnj htcommand(dev, HT_WEOF, 1); 1402926Swnj htcommand(dev, HT_SREV, 1); 14122Sbill } 1422926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1432926Swnj htcommand(dev, HT_REW, 0); 1442926Swnj sc->sc_openf = 0; 14522Sbill } 14622Sbill 1472926Swnj htcommand(dev, com, count) 1482926Swnj dev_t dev; 1492926Swnj int com, count; 15022Sbill { 15122Sbill register struct buf *bp; 15222Sbill 1532926Swnj bp = &chtbuf[HTUNIT(dev)]; 154128Sbill (void) spl5(); 1552926Swnj while (bp->b_flags&B_BUSY) { 1563157Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1572980Swnj break; 15822Sbill bp->b_flags |= B_WANTED; 15922Sbill sleep((caddr_t)bp, PRIBIO); 16022Sbill } 1612943Swnj bp->b_flags = B_BUSY|B_READ; 162128Sbill (void) spl0(); 16322Sbill bp->b_dev = dev; 1642926Swnj bp->b_command = com; 1652926Swnj bp->b_repcnt = count; 16622Sbill bp->b_blkno = 0; 16722Sbill htstrategy(bp); 1682926Swnj if (count == 0) 1692926Swnj return; 17022Sbill iowait(bp); 1712926Swnj if (bp->b_flags&B_WANTED) 17222Sbill wakeup((caddr_t)bp); 1732926Swnj bp->b_flags &= B_ERROR; 17422Sbill } 17522Sbill 17622Sbill htstrategy(bp) 1772926Swnj register struct buf *bp; 17822Sbill { 1793094Swnj register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; 1802926Swnj register struct buf *dp; 18122Sbill 18222Sbill bp->av_forw = NULL; 1832926Swnj dp = &mi->mi_tab; 184128Sbill (void) spl5(); 1852926Swnj if (dp->b_actf == NULL) 1862926Swnj dp->b_actf = bp; 18722Sbill else 1882926Swnj dp->b_actl->av_forw = bp; 1892926Swnj dp->b_actl = bp; 1902926Swnj if (dp->b_active == 0) 1912926Swnj mbustart(mi); 192128Sbill (void) spl0(); 19322Sbill } 19422Sbill 1952926Swnj htustart(mi) 1962980Swnj register struct mba_device *mi; 19722Sbill { 1982926Swnj register struct htdevice *htaddr = 1992926Swnj (struct htdevice *)mi->mi_drv; 2002926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2013094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; 20222Sbill daddr_t blkno; 20322Sbill 2042926Swnj htaddr->httc = sc->sc_dens; 2053181Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { 2063157Swnj htaddr->htcs1 = HT_SENSE|HT_GO; 2073157Swnj mbclrattn(mi); 2083157Swnj } 2092926Swnj sc->sc_dsreg = htaddr->htds; 2102926Swnj sc->sc_erreg = htaddr->hter; 2112926Swnj sc->sc_resid = htaddr->htfc; 2122926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 2132926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 2142926Swnj if (sc->sc_openf > 0) 2152926Swnj sc->sc_openf = -1; 2162926Swnj if (sc->sc_openf < 0) { 2172926Swnj bp->b_flags |= B_ERROR; 2182926Swnj return (MBU_NEXT); 2192926Swnj } 2203094Swnj if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { 2212926Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2222926Swnj bp->b_flags |= B_ERROR; 2232926Swnj bp->b_error = ENXIO; 2242961Swnj return (MBU_NEXT); 2253094Swnj } 2263094Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 2272926Swnj bp->b_flags&B_READ) { 2282926Swnj bp->b_resid = bp->b_bcount; 2292926Swnj clrbuf(bp); 2302961Swnj return (MBU_NEXT); 2313094Swnj } 2323094Swnj if ((bp->b_flags&B_READ)==0) 2332926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 2342926Swnj } else { 2352961Swnj if (bp->b_command == HT_SENSE) 2362926Swnj return (MBU_NEXT); 2372926Swnj if (bp->b_command == HT_REW) 2382926Swnj sc->sc_flags |= H_REWIND; 2392926Swnj else 2402926Swnj htaddr->htfc = -bp->b_bcount; 2412926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 2422926Swnj return (MBU_STARTED); 2432926Swnj } 2442926Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 2452926Swnj htaddr->htfc = -bp->b_bcount; 2462926Swnj if ((bp->b_flags&B_READ) == 0) { 2473094Swnj if (mi->mi_tab.b_errcnt) { 2483094Swnj if ((sc->sc_flags & H_ERASED) == 0) { 2492926Swnj sc->sc_flags |= H_ERASED; 2502926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2512926Swnj return (MBU_STARTED); 2522926Swnj } 2533094Swnj sc->sc_flags &= ~H_ERASED; 2543094Swnj } 2552926Swnj if (htaddr->htds & HTDS_EOT) { 2562926Swnj bp->b_resid = bp->b_bcount; 2572926Swnj return (MBU_NEXT); 2582926Swnj } 25922Sbill } 2602926Swnj return (MBU_DODATA); 26122Sbill } 2622926Swnj if (blkno < dbtofsb(bp->b_blkno)) { 2632926Swnj htaddr->htfc = blkno - dbtofsb(bp->b_blkno); 2642926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 26522Sbill } else { 2662926Swnj htaddr->htfc = dbtofsb(bp->b_blkno) - blkno; 2672926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 26822Sbill } 2692926Swnj return (MBU_STARTED); 27022Sbill } 27122Sbill 2723094Swnj htdtint(mi, mbsr) 2732980Swnj register struct mba_device *mi; 2743094Swnj int mbsr; 27522Sbill { 2762926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2772926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2783094Swnj register struct tu_softc *sc; 2792961Swnj int ds, er, mbs; 28022Sbill 2813094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 2822926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 2832926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 2842926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 2853094Swnj mbs = mbsr; 2862926Swnj sc->sc_blkno++; 2872926Swnj if((bp->b_flags & B_READ) == 0) 2882926Swnj sc->sc_flags |= H_WRITTEN; 2893094Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { 2902926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 2912961Swnj mbclrattn(mi); 2922961Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { 2932926Swnj er &= ~HTER_FCE; 2943094Swnj mbs &= ~(MBSR_DTABT|MBSR_MBEXC); 2953157Swnj } else 2962926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 2972926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 2983094Swnj if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || 2992961Swnj er && ++mi->mi_tab.b_errcnt >= 7) { 3002926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3012926Swnj sc->sc_openf = -1; 3023157Swnj if ((er&HTER_HARD) == HTER_FCE && 3033157Swnj (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && 3043157Swnj (ds&HTDS_MOL)) 3053157Swnj goto noprint; 3063204Swnj printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", 3072980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3083094Swnj mbsr, mbsr_bits, 3093204Swnj sc->sc_erreg, hter_bits, 3103204Swnj sc->sc_dsreg, htds_bits); 3113157Swnj noprint: 31222Sbill bp->b_flags |= B_ERROR; 3132926Swnj return (MBD_DONE); 31422Sbill } 3152926Swnj if (er) 3162926Swnj return (MBD_RETRY); 31722Sbill } 3182926Swnj bp->b_resid = 0; 3192926Swnj if (bp->b_flags & B_READ) 3202926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 3212926Swnj bp->b_resid = bp->b_bcount; 3222926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 3232926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 3242926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 3252926Swnj return (MBD_DONE); 3262926Swnj } 32722Sbill 3282926Swnj htndtint(mi) 3292980Swnj register struct mba_device *mi; 3302926Swnj { 3312926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3322926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3333094Swnj register struct tu_softc *sc; 3342926Swnj int er, ds, fc; 33522Sbill 3363094Swnj ds = MASKREG(htaddr->htds); 3373094Swnj er = MASKREG(htaddr->hter); 3383094Swnj fc = MASKREG(htaddr->htfc); 3393094Swnj if (er) { 3402926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3412961Swnj mbclrattn(mi); 3422961Swnj } 3433094Swnj if (bp == 0) 3443094Swnj return (MBN_SKIP); 3453094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3463094Swnj sc->sc_dsreg = ds; 3473094Swnj sc->sc_erreg = er; 3483094Swnj sc->sc_resid = fc; 3493094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3503094Swnj switch (bp->b_command) { 3513094Swnj case HT_REWOFFL: 3522926Swnj /* offline is on purpose; don't do anything special */ 3532926Swnj ds |= HTDS_MOL; 3543094Swnj break; 3553094Swnj case HT_SREV: 3563094Swnj /* if backspace file hit bot, its not an error */ 3573094Swnj if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && 3583094Swnj bp->b_repcnt == INF) 3593094Swnj er &= ~HTER_NEF; 3603094Swnj break; 3613094Swnj } 3622926Swnj er &= ~HTER_FCE; 3632926Swnj if (er == 0) 3642926Swnj ds &= ~HTDS_ERR; 36522Sbill } 3662926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3672926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3682926Swnj sc->sc_openf = -1; 3693204Swnj printf("tu%d: hard error bn%d er=%b ds=%b\n", 3702980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3713204Swnj sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); 3722926Swnj bp->b_flags |= B_ERROR; 3732926Swnj return (MBN_DONE); 3742926Swnj } 3753094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3762926Swnj if (sc->sc_flags & H_REWIND) 3772926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3782926Swnj bp->b_resid = -sc->sc_resid; 3792926Swnj return (MBN_DONE); 3802926Swnj } 3812926Swnj if (ds & HTDS_TM) 3823094Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 3832926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc; 3842926Swnj sc->sc_blkno = sc->sc_nxrec; 3853094Swnj } else { 3862926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) + fc; 3872926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 3882926Swnj } 3892926Swnj else 3902926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 3912926Swnj return (MBN_RETRY); 39222Sbill } 39322Sbill 39422Sbill htread(dev) 3952926Swnj dev_t dev; 39622Sbill { 3972926Swnj 39822Sbill htphys(dev); 3992926Swnj if (u.u_error) 4002926Swnj return; 4012926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys); 40222Sbill } 40322Sbill 40422Sbill htwrite(dev) 40522Sbill { 4062926Swnj 40722Sbill htphys(dev); 4082926Swnj if (u.u_error) 4092926Swnj return; 4102926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys); 41122Sbill } 41222Sbill 41322Sbill htphys(dev) 4142926Swnj dev_t dev; 41522Sbill { 4163094Swnj register int htunit; 4173094Swnj register struct tu_softc *sc; 4183094Swnj register struct mba_device *mi; 41922Sbill daddr_t a; 42022Sbill 4213094Swnj htunit = HTUNIT(dev); 4223094Swnj if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) { 4232926Swnj u.u_error = ENXIO; 4242926Swnj return; 42522Sbill } 4262926Swnj a = u.u_offset >> 9; 4273094Swnj sc = &tu_softc[TUUNIT(dev)]; 4282926Swnj sc->sc_blkno = dbtofsb(a); 4292926Swnj sc->sc_nxrec = dbtofsb(a)+1; 43022Sbill } 4311917Swnj 4322926Swnj /*ARGSUSED*/ 4332926Swnj htioctl(dev, cmd, addr, flag) 4342926Swnj dev_t dev; 4352926Swnj int cmd; 4362926Swnj caddr_t addr; 4372926Swnj int flag; 4382926Swnj { 4393094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 4403094Swnj register struct buf *bp = &chtbuf[HTUNIT(dev)]; 4412926Swnj register callcount; 4422926Swnj int fcount; 4432926Swnj struct mtop mtop; 4442926Swnj struct mtget mtget; 4452926Swnj /* we depend of the values and order of the MT codes here */ 4462926Swnj static htops[] = 4472926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4481917Swnj 4492926Swnj switch (cmd) { 4502926Swnj case MTIOCTOP: /* tape operation */ 4512926Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 4522926Swnj u.u_error = EFAULT; 4532926Swnj return; 4542926Swnj } 4552926Swnj switch(mtop.mt_op) { 4562926Swnj case MTWEOF: 4572926Swnj callcount = mtop.mt_count; 4582926Swnj fcount = 1; 4592926Swnj break; 4602926Swnj case MTFSF: case MTBSF: 4612926Swnj callcount = mtop.mt_count; 4622926Swnj fcount = INF; 4632926Swnj break; 4642926Swnj case MTFSR: case MTBSR: 4652926Swnj callcount = 1; 4662926Swnj fcount = mtop.mt_count; 4672926Swnj break; 4682926Swnj case MTREW: case MTOFFL: 4692926Swnj callcount = 1; 4702926Swnj fcount = 1; 4712926Swnj break; 4722926Swnj default: 4732926Swnj u.u_error = ENXIO; 4742926Swnj return; 4752926Swnj } 4762926Swnj if (callcount <= 0 || fcount <= 0) { 4772926Swnj u.u_error = ENXIO; 4782926Swnj return; 4792926Swnj } 4802926Swnj while (--callcount >= 0) { 4812926Swnj htcommand(dev, htops[mtop.mt_op], fcount); 4822926Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 4832926Swnj bp->b_resid) { 4842926Swnj u.u_error = EIO; 4852926Swnj break; 4862926Swnj } 4873094Swnj if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) 4882926Swnj break; 4892926Swnj } 4902926Swnj geterror(bp); 4912926Swnj return; 4922926Swnj case MTIOCGET: 4932926Swnj mtget.mt_dsreg = sc->sc_dsreg; 4942926Swnj mtget.mt_erreg = sc->sc_erreg; 4952926Swnj mtget.mt_resid = sc->sc_resid; 496*3480Stoy mtget.mt_type = MT_ISHT; 4972926Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 4982926Swnj u.u_error = EFAULT; 4992926Swnj return; 5002926Swnj default: 5012926Swnj u.u_error = ENXIO; 5022926Swnj } 5032926Swnj } 5042926Swnj 5051917Swnj #define DBSIZE 20 5061917Swnj 5072926Swnj htdump() 5081917Swnj { 5092980Swnj register struct mba_device *mi; 5102926Swnj register struct mba_regs *mp; 5112926Swnj register struct htdevice *htaddr; 5122926Swnj int blk, num; 5132926Swnj int start; 5141917Swnj 5152926Swnj start = 0; 5162926Swnj num = maxfree; 5172926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5182926Swnj if (htinfo[0] == 0) 5192926Swnj return (ENXIO); 5202980Swnj mi = phys(htinfo[0], struct mba_device *); 5212926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5223157Swnj mp->mba_cr = MBCR_IE; 5232926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 5242926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 5252926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 5261917Swnj while (num > 0) { 5271917Swnj blk = num > DBSIZE ? DBSIZE : num; 5282926Swnj htdwrite(start, blk, htaddr, mp); 5292926Swnj start += blk; 5301917Swnj num -= blk; 5311917Swnj } 5323157Swnj hteof(htaddr); 5333157Swnj hteof(htaddr); 5342926Swnj htwait(htaddr); 5353181Swnj if (htaddr->htds&HTDS_ERR) 5363157Swnj return (EIO); 5372926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5383103Swnj return (0); 5391917Swnj } 5401917Swnj 5412926Swnj htdwrite(dbuf, num, htaddr, mp) 5422926Swnj register dbuf, num; 5432926Swnj register struct htdevice *htaddr; 5442926Swnj struct mba_regs *mp; 5451917Swnj { 5462926Swnj register struct pte *io; 5471917Swnj register int i; 5481917Swnj 5492926Swnj htwait(htaddr); 5502926Swnj io = mp->mba_map; 5511917Swnj for (i = 0; i < num; i++) 5522926Swnj *(int *)io++ = dbuf++ | PG_V; 5532926Swnj htaddr->htfc = -(num*NBPG); 5542926Swnj mp->mba_sr = -1; 5552926Swnj mp->mba_bcr = -(num*NBPG); 5562926Swnj mp->mba_var = 0; 5572926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5581917Swnj } 5591917Swnj 5602926Swnj htwait(htaddr) 5612926Swnj struct htdevice *htaddr; 5621917Swnj { 5631917Swnj register s; 5641917Swnj 5651917Swnj do 5662926Swnj s = htaddr->htds; 5672926Swnj while ((s & HTDS_DRY) == 0); 5681917Swnj } 5691917Swnj 5702926Swnj hteof(htaddr) 5712926Swnj struct htdevice *htaddr; 5721917Swnj { 5731917Swnj 5742926Swnj htwait(htaddr); 5752926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 5761917Swnj } 5771563Sbill #endif 578