11936Swnj #include "ht.h" 21563Sbill #if NHT > 0 322Sbill /* 42926Swnj * TM03/TU?? tape driver 522Sbill */ 622Sbill #include "../h/param.h" 722Sbill #include "../h/systm.h" 822Sbill #include "../h/buf.h" 922Sbill #include "../h/conf.h" 1022Sbill #include "../h/dir.h" 1122Sbill #include "../h/file.h" 1222Sbill #include "../h/user.h" 1322Sbill #include "../h/map.h" 14420Sbill #include "../h/pte.h" 1522Sbill #include "../h/mba.h" 162926Swnj #include "../h/mtio.h" 172926Swnj #include "../h/ioctl.h" 181917Swnj #include "../h/cmap.h" 1922Sbill 202926Swnj #include "../h/htreg.h" 2122Sbill 222926Swnj struct buf rhtbuf[NHT]; 232926Swnj struct buf chtbuf[NHT]; 2422Sbill 252926Swnj short httypes[] = 262926Swnj { MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 272926Swnj struct mba_info *htinfo[NHT]; 282926Swnj int htdkinit(), htustart(), htndtint(), htdtint(); 292926Swnj struct mba_driver htdriver = 302926Swnj { htdkinit, htustart, 0, htdtint, htndtint, httypes, htinfo }; 3122Sbill 322926Swnj #define MASKREG(r) ((r) & 0xffff) 3322Sbill 342926Swnj /* bits in minor device */ 352926Swnj #define HTUNIT(dev) (minor(dev)&03) 362926Swnj #define H_NOREWIND 04 372926Swnj #define H_1600BPI 08 3822Sbill 392926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 402926Swnj 412926Swnj struct ht_softc { 422926Swnj char sc_openf; 432926Swnj char sc_flags; 442926Swnj daddr_t sc_blkno; 452926Swnj daddr_t sc_nxrec; 462926Swnj u_short sc_erreg; 472926Swnj u_short sc_dsreg; 482926Swnj short sc_resid; 492926Swnj short sc_dens; 502926Swnj } ht_softc[NHT]; 512926Swnj 522926Swnj /* 532926Swnj * Bits for sc_flags. 542926Swnj */ 552926Swnj #define H_WRITTEN 1 /* last operation was a write */ 562926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 572926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 5822Sbill 592926Swnj /*ARGSUSED*/ 602926Swnj htdkinit(mi) 612926Swnj struct mba_info *mi; 622926Swnj { 632926Swnj 642926Swnj } 652926Swnj 6622Sbill htopen(dev, flag) 672926Swnj dev_t dev; 682926Swnj int flag; 6922Sbill { 702926Swnj register int unit; 712926Swnj register struct mba_info *mi; 722926Swnj register struct ht_softc *sc; 7322Sbill 742926Swnj unit = HTUNIT(dev); 752926Swnj if (unit >= NHT || (sc = &ht_softc[unit])->sc_openf || 762926Swnj (mi = htinfo[unit]) == 0 || mi->mi_alive == 0) { 7722Sbill u.u_error = ENXIO; 7822Sbill return; 7922Sbill } 802926Swnj /* 812926Swnj * The NOP below serves two purposes: 822926Swnj * 1. To get a recent copy of the status registers. 832926Swnj * 2. To ensure that any outstanding rewinds are truly finished 842926Swnj */ 852926Swnj htcommand(dev, HT_SENSE, 1); 862926Swnj if ((sc->sc_dsreg & HTDS_MOL) == 0 || 872926Swnj (flag & (FREAD|FWRITE)) == FWRITE && sc->sc_dsreg&HTDS_WRL) { 882926Swnj u.u_error = EIO; 892926Swnj return; 902926Swnj } 912926Swnj sc->sc_dens = 92*2943Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)|HTTC_PDP11|mi->mi_slave; 93*2943Swnj printf("dens %o\n", sc->sc_dens); 942926Swnj sc->sc_openf = 1; 952926Swnj sc->sc_blkno = (daddr_t)0; 962926Swnj sc->sc_nxrec = INF; 972926Swnj sc->sc_flags = 0; 9822Sbill } 9922Sbill 10022Sbill htclose(dev, flag) 1012926Swnj register dev_t dev; 1022926Swnj register flag; 10322Sbill { 1042926Swnj register struct ht_softc *sc = &ht_softc[HTUNIT(dev)]; 10522Sbill 1062926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1072926Swnj htcommand(dev, HT_WEOF, 1); 1082926Swnj htcommand(dev, HT_WEOF, 1); 1092926Swnj htcommand(dev, HT_SREV, 1); 11022Sbill } 1112926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1122926Swnj /* 0 as third arg means don't wait */ 1132926Swnj htcommand(dev, HT_REW, 0); 1142926Swnj sc->sc_openf = 0; 11522Sbill } 11622Sbill 1172926Swnj /* 1182926Swnj * Do a non-data-transfer command. 1192926Swnj * 1202926Swnj * N.B.: Count should be zero ONLY for rewind during close. 1212926Swnj */ 1222926Swnj htcommand(dev, com, count) 1232926Swnj dev_t dev; 1242926Swnj int com, count; 12522Sbill { 12622Sbill register struct buf *bp; 12722Sbill 1282926Swnj bp = &chtbuf[HTUNIT(dev)]; 129128Sbill (void) spl5(); 1302926Swnj while (bp->b_flags&B_BUSY) { 13122Sbill bp->b_flags |= B_WANTED; 13222Sbill sleep((caddr_t)bp, PRIBIO); 13322Sbill } 134*2943Swnj bp->b_flags = B_BUSY|B_READ; 135128Sbill (void) spl0(); 13622Sbill bp->b_dev = dev; 1372926Swnj bp->b_command = com; 1382926Swnj bp->b_repcnt = count; 13922Sbill bp->b_blkno = 0; 14022Sbill htstrategy(bp); 1412926Swnj if (count == 0) 1422926Swnj return; 14322Sbill iowait(bp); 1442926Swnj if (bp->b_flags&B_WANTED) 14522Sbill wakeup((caddr_t)bp); 1462926Swnj bp->b_flags &= B_ERROR; 14722Sbill } 14822Sbill 14922Sbill htstrategy(bp) 1502926Swnj register struct buf *bp; 15122Sbill { 1522926Swnj register int unit = HTUNIT(bp->b_dev); 153*2943Swnj register struct mba_info *mi = htinfo[unit]; 1542926Swnj register struct buf *dp; 1552926Swnj register struct ht_softc *sc = &ht_softc[unit]; 15622Sbill 15722Sbill bp->av_forw = NULL; 1582926Swnj dp = &mi->mi_tab; 159128Sbill (void) spl5(); 1602926Swnj if (dp->b_actf == NULL) 1612926Swnj dp->b_actf = bp; 16222Sbill else 1632926Swnj dp->b_actl->av_forw = bp; 1642926Swnj dp->b_actl = bp; 1652926Swnj if (dp->b_active == 0) 1662926Swnj mbustart(mi); 167128Sbill (void) spl0(); 16822Sbill } 16922Sbill 1702926Swnj htustart(mi) 1712926Swnj register struct mba_info *mi; 17222Sbill { 1732926Swnj register struct htdevice *htaddr = 1742926Swnj (struct htdevice *)mi->mi_drv; 1752926Swnj register struct buf *bp = mi->mi_tab.b_actf; 1762926Swnj int unit = HTUNIT(bp->b_dev); 1772926Swnj register struct ht_softc *sc = &ht_softc[unit]; 17822Sbill daddr_t blkno; 17922Sbill 1802926Swnj htaddr->httc = sc->sc_dens; 1812926Swnj sc->sc_dsreg = htaddr->htds; 1822926Swnj sc->sc_erreg = htaddr->hter; 1832926Swnj sc->sc_resid = htaddr->htfc; 1842926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 1852926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 1862926Swnj if (sc->sc_openf > 0) 1872926Swnj sc->sc_openf = -1; 1882926Swnj if (sc->sc_openf < 0) { 1892926Swnj bp->b_flags |= B_ERROR; 1902926Swnj return (MBU_NEXT); 1912926Swnj } 1922926Swnj if (bp != &chtbuf[unit]) { 1932926Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 1942926Swnj bp->b_flags |= B_ERROR; 1952926Swnj bp->b_error = ENXIO; 19622Sbill goto next; 1972926Swnj } else if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && 1982926Swnj bp->b_flags&B_READ) { 1992926Swnj bp->b_resid = bp->b_bcount; 2002926Swnj clrbuf(bp); 2012926Swnj goto next; 2022926Swnj } else if ((bp->b_flags&B_READ)==0) 2032926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) + 1; 2042926Swnj } else { 205*2943Swnj if (bp->b_command == HT_SENSE) { 206*2943Swnj T(10)("sense complete\n"); 2072926Swnj return (MBU_NEXT); 208*2943Swnj } 2092926Swnj if (bp->b_command == HT_REW) 2102926Swnj sc->sc_flags |= H_REWIND; 2112926Swnj else 2122926Swnj htaddr->htfc = -bp->b_bcount; 2132926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 214*2943Swnj T(10)("started cmd %d\n", bp->b_command); 2152926Swnj return (MBU_STARTED); 2162926Swnj } 2172926Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 2182926Swnj htaddr->htfc = -bp->b_bcount; 2192926Swnj if ((bp->b_flags&B_READ) == 0) { 2202926Swnj if (mi->mi_tab.b_errcnt) 2212926Swnj if (sc->sc_flags & H_ERASED) 2222926Swnj sc->sc_flags &= ~H_ERASED; 2232926Swnj else { 2242926Swnj sc->sc_flags |= H_ERASED; 2252926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2262926Swnj return (MBU_STARTED); 2272926Swnj } 2282926Swnj if (htaddr->htds & HTDS_EOT) { 2292926Swnj bp->b_resid = bp->b_bcount; 2302926Swnj return (MBU_NEXT); 2312926Swnj } 23222Sbill } 2332926Swnj return (MBU_DODATA); 23422Sbill } 2352926Swnj if (blkno < dbtofsb(bp->b_blkno)) { 2362926Swnj htaddr->htfc = blkno - dbtofsb(bp->b_blkno); 237*2943Swnj T(10)("spacing fwd %d\n", MASKREG(htaddr)->htfc); 2382926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 23922Sbill } else { 2402926Swnj htaddr->htfc = dbtofsb(bp->b_blkno) - blkno; 241*2943Swnj T(10)("spacing back %d\n", MASKREG(htaddr)->htfc); 2422926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 24322Sbill } 2442926Swnj return (MBU_STARTED); 2452926Swnj next: 24622Sbill iodone(bp); 2472926Swnj return (MBU_NEXT); 24822Sbill } 24922Sbill 2502926Swnj /* 2512926Swnj * data transfer interrupt - must be read or write 2522926Swnj */ 25322Sbill /*ARGSUSED*/ 2542926Swnj htdtint(mi, mbasr) 2552926Swnj register struct mba_info *mi; 2562926Swnj int mbasr; 25722Sbill { 2582926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2592926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2602926Swnj register struct ht_softc *sc; 2612926Swnj int ds, er; 26222Sbill 2632926Swnj sc = &ht_softc[HTUNIT(bp->b_dev)]; 2642926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 2652926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 2662926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 2672926Swnj sc->sc_blkno++; 2682926Swnj if((bp->b_flags & B_READ) == 0) 2692926Swnj sc->sc_flags |= H_WRITTEN; 2702926Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || 2712926Swnj mbasr & MBAEBITS) { 2722926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 2732926Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) 2742926Swnj er &= ~HTER_FCE; 2752926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 2762926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 2772926Swnj if (er&HTER_HARD || 2782926Swnj mbasr&MBAEBITS || (ds&HTDS_MOL) == 0 || 2792926Swnj sc->sc_erreg && ++mi->mi_tab.b_errcnt >= 7) { 2802926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 2812926Swnj sc->sc_openf = -1; 2822926Swnj printf("ht%d: hard error bn%d mbasr=%b er=%b\n", 2832926Swnj HTUNIT(bp->b_dev), bp->b_blkno, 2842926Swnj mbasr, mbasr_bits, 2852926Swnj MASKREG(htaddr->hter), HTER_BITS); 28622Sbill bp->b_flags |= B_ERROR; 2872926Swnj return (MBD_DONE); 28822Sbill } 2892926Swnj if (er) 2902926Swnj return (MBD_RETRY); 29122Sbill } 2922926Swnj bp->b_resid = 0; 2932926Swnj if (bp->b_flags & B_READ) 2942926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 2952926Swnj bp->b_resid = bp->b_bcount; 2962926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 2972926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 2982926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 2992926Swnj return (MBD_DONE); 3002926Swnj } 30122Sbill 3022926Swnj /* 3032926Swnj * non-data-transfer interrupt 3042926Swnj */ 3052926Swnj htndtint(mi) 3062926Swnj register struct mba_info *mi; 3072926Swnj { 3082926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3092926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3102926Swnj register struct ht_softc *sc; 3112926Swnj int er, ds, fc; 31222Sbill 3132926Swnj sc = &ht_softc[HTUNIT(bp->b_dev)]; 3142926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 3152926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 3162926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 3172926Swnj if (sc->sc_erreg) 3182926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3192926Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3202926Swnj if (bp->b_command == HT_REWOFFL) 3212926Swnj /* offline is on purpose; don't do anything special */ 3222926Swnj ds |= HTDS_MOL; 3232926Swnj else if (bp->b_resid == HT_SREV && 3242926Swnj er == (HTER_NEF|HTER_FCE) && 3252926Swnj ds&HTDS_BOT && bp->b_bcount == INF) 3262926Swnj er &= ~HTER_NEF; 3272926Swnj er &= ~HTER_FCE; 3282926Swnj if (er == 0) 3292926Swnj ds &= ~HTDS_ERR; 33022Sbill } 3312926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3322926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3332926Swnj sc->sc_openf = -1; 3342926Swnj printf("ht%d: hard error bn%d er=%b ds=%b\n", 3352926Swnj HTUNIT(bp->b_dev), bp->b_blkno, 3362926Swnj sc->sc_erreg, HTER_BITS, sc->sc_dsreg, HTDS_BITS); 3372926Swnj bp->b_flags |= B_ERROR; 3382926Swnj return (MBN_DONE); 3392926Swnj } 3402926Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3412926Swnj if (sc->sc_flags & H_REWIND) 3422926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3432926Swnj bp->b_resid = -sc->sc_resid; 3442926Swnj return (MBN_DONE); 3452926Swnj } 3462926Swnj if (ds & HTDS_TM) 3472926Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) {/* reversing */ 3482926Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno) - fc; 3492926Swnj sc->sc_blkno = sc->sc_nxrec; 3502926Swnj } else { /* spacing forward */ 3512926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno) + fc; 3522926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 3532926Swnj } 3542926Swnj else 3552926Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 3562926Swnj return (MBN_RETRY); 35722Sbill } 35822Sbill 35922Sbill htread(dev) 3602926Swnj dev_t dev; 36122Sbill { 3622926Swnj 36322Sbill htphys(dev); 3642926Swnj if (u.u_error) 3652926Swnj return; 3662926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys); 36722Sbill } 36822Sbill 36922Sbill htwrite(dev) 37022Sbill { 3712926Swnj 37222Sbill htphys(dev); 3732926Swnj if (u.u_error) 3742926Swnj return; 3752926Swnj physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys); 37622Sbill } 37722Sbill 37822Sbill htphys(dev) 3792926Swnj dev_t dev; 38022Sbill { 3812926Swnj register int unit; 3822926Swnj register struct ht_softc *sc; 38322Sbill daddr_t a; 38422Sbill 3852926Swnj unit = HTUNIT(dev); 3862926Swnj if (unit >= NHT) { 3872926Swnj u.u_error = ENXIO; 3882926Swnj return; 38922Sbill } 3902926Swnj a = u.u_offset >> 9; 3912926Swnj sc = &ht_softc[unit]; 3922926Swnj sc->sc_blkno = dbtofsb(a); 3932926Swnj sc->sc_nxrec = dbtofsb(a)+1; 39422Sbill } 3951917Swnj 3962926Swnj /*ARGSUSED*/ 3972926Swnj htioctl(dev, cmd, addr, flag) 3982926Swnj dev_t dev; 3992926Swnj int cmd; 4002926Swnj caddr_t addr; 4012926Swnj int flag; 4022926Swnj { 4032926Swnj register unit = HTUNIT(dev); 4042926Swnj register struct ht_softc *sc = &ht_softc[unit]; 4052926Swnj register struct buf *bp = &chtbuf[unit]; 4062926Swnj register callcount; 4072926Swnj int fcount; 4082926Swnj struct mtop mtop; 4092926Swnj struct mtget mtget; 4102926Swnj /* we depend of the values and order of the MT codes here */ 4112926Swnj static htops[] = 4122926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4131917Swnj 4142926Swnj switch (cmd) { 4152926Swnj case MTIOCTOP: /* tape operation */ 4162926Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 4172926Swnj u.u_error = EFAULT; 4182926Swnj return; 4192926Swnj } 4202926Swnj switch(mtop.mt_op) { 4212926Swnj case MTWEOF: 4222926Swnj callcount = mtop.mt_count; 4232926Swnj fcount = 1; 4242926Swnj break; 4252926Swnj case MTFSF: case MTBSF: 4262926Swnj callcount = mtop.mt_count; 4272926Swnj fcount = INF; 4282926Swnj break; 4292926Swnj case MTFSR: case MTBSR: 4302926Swnj callcount = 1; 4312926Swnj fcount = mtop.mt_count; 4322926Swnj break; 4332926Swnj case MTREW: case MTOFFL: 4342926Swnj callcount = 1; 4352926Swnj fcount = 1; 4362926Swnj break; 4372926Swnj default: 4382926Swnj u.u_error = ENXIO; 4392926Swnj return; 4402926Swnj } 4412926Swnj if (callcount <= 0 || fcount <= 0) { 4422926Swnj u.u_error = ENXIO; 4432926Swnj return; 4442926Swnj } 4452926Swnj while (--callcount >= 0) { 4462926Swnj htcommand(dev, htops[mtop.mt_op], fcount); 4472926Swnj if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && 4482926Swnj bp->b_resid) { 4492926Swnj u.u_error = EIO; 4502926Swnj break; 4512926Swnj } 4522926Swnj if ((chtbuf[HTUNIT(bp->b_dev)].b_flags&B_ERROR) || 4532926Swnj sc->sc_dsreg&HTDS_BOT) 4542926Swnj break; 4552926Swnj } 4562926Swnj geterror(bp); 4572926Swnj return; 4582926Swnj case MTIOCGET: 4592926Swnj mtget.mt_dsreg = sc->sc_dsreg; 4602926Swnj mtget.mt_erreg = sc->sc_erreg; 4612926Swnj mtget.mt_resid = sc->sc_resid; 4622926Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 4632926Swnj u.u_error = EFAULT; 4642926Swnj return; 4652926Swnj default: 4662926Swnj u.u_error = ENXIO; 4672926Swnj } 4682926Swnj } 4692926Swnj 4701917Swnj #define DBSIZE 20 4711917Swnj 4722926Swnj htdump() 4731917Swnj { 4742926Swnj register struct mba_info *mi; 4752926Swnj register struct mba_regs *mp; 4762926Swnj register struct htdevice *htaddr; 4772926Swnj int blk, num; 4782926Swnj int start; 4791917Swnj 4802926Swnj start = 0; 4812926Swnj num = maxfree; 4822926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 4832926Swnj if (htinfo[0] == 0) 4842926Swnj return (ENXIO); 4852926Swnj mi = phys(htinfo[0], struct mba_info *); 4862926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 4872926Swnj #if VAX780 4882926Swnj mbainit(mp); 4892926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 4902926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 4912926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 4921917Swnj while (num > 0) { 4931917Swnj blk = num > DBSIZE ? DBSIZE : num; 4942926Swnj htdwrite(start, blk, htaddr, mp); 4952926Swnj start += blk; 4961917Swnj num -= blk; 4971917Swnj } 4982926Swnj htwait(htaddr); 4992926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5002926Swnj hteof(htaddr); 5012926Swnj hteof(htaddr); 5021917Swnj } 5031917Swnj 5042926Swnj htdwrite(dbuf, num, htaddr, mp) 5052926Swnj register dbuf, num; 5062926Swnj register struct htdevice *htaddr; 5072926Swnj struct mba_regs *mp; 5081917Swnj { 5092926Swnj register struct pte *io; 5101917Swnj register int i; 5111917Swnj 5122926Swnj htwait(htaddr); 5132926Swnj io = mp->mba_map; 5141917Swnj for (i = 0; i < num; i++) 5152926Swnj *(int *)io++ = dbuf++ | PG_V; 5162926Swnj htaddr->htfc = -(num*NBPG); 5172926Swnj mp->mba_sr = -1; 5182926Swnj mp->mba_bcr = -(num*NBPG); 5192926Swnj mp->mba_var = 0; 5202926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5211917Swnj } 5221917Swnj 5232926Swnj htwait(htaddr) 5242926Swnj struct htdevice *htaddr; 5251917Swnj { 5261917Swnj register s; 5271917Swnj 5281917Swnj do 5292926Swnj s = htaddr->htds; 5302926Swnj while ((s & HTDS_DRY) == 0); 5311917Swnj } 5321917Swnj 5332926Swnj hteof(htaddr) 5342926Swnj struct htdevice *htaddr; 5351917Swnj { 5361917Swnj 5372926Swnj htwait(htaddr); 5382926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 5391917Swnj } 5401563Sbill #endif 541