1*17118Sbloom /* ht.c 6.3 84/08/29 */ 22961Swnj 32980Swnj #include "tu.h" 41563Sbill #if NHT > 0 522Sbill /* 62926Swnj * TM03/TU?? tape driver 73094Swnj * 83094Swnj * TODO: 93204Swnj * cleanup messages on errors 103094Swnj * test ioctl's 113094Swnj * see how many rewind interrups we get if we kick when not at BOT 123204Swnj * fixup rle error on block tape code 1322Sbill */ 149787Ssam #include "../machine/pte.h" 159787Ssam 16*17118Sbloom #include "param.h" 17*17118Sbloom #include "systm.h" 18*17118Sbloom #include "buf.h" 19*17118Sbloom #include "conf.h" 20*17118Sbloom #include "dir.h" 21*17118Sbloom #include "file.h" 22*17118Sbloom #include "user.h" 23*17118Sbloom #include "map.h" 24*17118Sbloom #include "ioctl.h" 25*17118Sbloom #include "mtio.h" 26*17118Sbloom #include "cmap.h" 27*17118Sbloom #include "uio.h" 2822Sbill 298469Sroot #include "../vax/cpu.h" 30*17118Sbloom #include "mbareg.h" 31*17118Sbloom #include "mbavar.h" 32*17118Sbloom #include "htreg.h" 3322Sbill 342926Swnj struct buf rhtbuf[NHT]; 352926Swnj struct buf chtbuf[NHT]; 3622Sbill 372926Swnj short httypes[] = 383181Swnj { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; 392980Swnj struct mba_device *htinfo[NHT]; 403103Swnj int htattach(), htslave(), htustart(), htndtint(), htdtint(); 412926Swnj struct mba_driver htdriver = 422980Swnj { htattach, htslave, htustart, 0, htdtint, htndtint, 432980Swnj httypes, "ht", "tu", htinfo }; 4422Sbill 452926Swnj #define MASKREG(r) ((r) & 0xffff) 4622Sbill 472926Swnj /* bits in minor device */ 482980Swnj #define TUUNIT(dev) (minor(dev)&03) 492926Swnj #define H_NOREWIND 04 502926Swnj #define H_1600BPI 08 5122Sbill 523094Swnj #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) 532980Swnj 542926Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 552926Swnj 563094Swnj struct tu_softc { 572926Swnj char sc_openf; 582926Swnj char sc_flags; 592926Swnj daddr_t sc_blkno; 602926Swnj daddr_t sc_nxrec; 612926Swnj u_short sc_erreg; 622926Swnj u_short sc_dsreg; 632926Swnj short sc_resid; 642926Swnj short sc_dens; 652980Swnj struct mba_device *sc_mi; 662980Swnj int sc_slave; 673094Swnj } tu_softc[NTU]; 683094Swnj short tutoht[NTU]; 692926Swnj 702926Swnj /* 712926Swnj * Bits for sc_flags. 722926Swnj */ 732926Swnj #define H_WRITTEN 1 /* last operation was a write */ 742926Swnj #define H_ERASED 2 /* last write retry was an erase gap */ 752926Swnj #define H_REWIND 4 /* last unit start was a rewind */ 7622Sbill 773204Swnj char hter_bits[] = HTER_BITS; 783204Swnj char htds_bits[] = HTDS_BITS; 793204Swnj 802926Swnj /*ARGSUSED*/ 812980Swnj htattach(mi) 822980Swnj struct mba_device *mi; 832926Swnj { 842926Swnj 852926Swnj } 862926Swnj 877430Skre htslave(mi, ms, sn) 882980Swnj struct mba_device *mi; 892980Swnj struct mba_slave *ms; 907430Skre int sn; 912980Swnj { 923094Swnj register struct tu_softc *sc = &tu_softc[ms->ms_unit]; 934756Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 942980Swnj 957430Skre htaddr->httc = sn; 964756Swnj if (htaddr->htdt & HTDT_SPR) { 974756Swnj sc->sc_mi = mi; 987430Skre sc->sc_slave = sn; 994756Swnj tutoht[ms->ms_unit] = mi->mi_unit; 1004756Swnj return (1); 1014756Swnj } else 1024756Swnj return (0); 1032980Swnj } 1042980Swnj 10522Sbill htopen(dev, flag) 1062926Swnj dev_t dev; 1072926Swnj int flag; 10822Sbill { 1093094Swnj register int tuunit; 1102980Swnj register struct mba_device *mi; 1113094Swnj register struct tu_softc *sc; 1123203Swnj int olddens, dens; 11322Sbill 1143094Swnj tuunit = TUUNIT(dev); 1153094Swnj if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || 1168580Sroot (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) 1178580Sroot return (ENXIO); 1183203Swnj olddens = sc->sc_dens; 1193204Swnj dens = sc->sc_dens = 1203094Swnj ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| 1213094Swnj HTTC_PDP11|sc->sc_slave; 1223203Swnj htcommand(dev, HT_SENSE, 1); 1233203Swnj sc->sc_dens = olddens; 1243707Sroot if ((sc->sc_dsreg & HTDS_MOL) == 0) { 1253717Sroot uprintf("tu%d: not online\n", tuunit); 1268580Sroot return (EIO); 1272926Swnj } 1283707Sroot if ((flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL)) { 1293717Sroot uprintf("tu%d: no write ring\n", tuunit); 1308580Sroot return (EIO); 1313707Sroot } 1323707Sroot if ((sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && 1333707Sroot dens != sc->sc_dens) { 1343717Sroot uprintf("tu%d: can't change density in mid-tape\n", tuunit); 1358580Sroot return (EIO); 1363707Sroot } 1372926Swnj sc->sc_openf = 1; 1382926Swnj sc->sc_blkno = (daddr_t)0; 1392926Swnj sc->sc_nxrec = INF; 1402926Swnj sc->sc_flags = 0; 1413094Swnj sc->sc_dens = dens; 1428580Sroot return (0); 14322Sbill } 14422Sbill 14522Sbill htclose(dev, flag) 1462926Swnj register dev_t dev; 1472926Swnj register flag; 14822Sbill { 1493094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 15022Sbill 1512926Swnj if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { 1522926Swnj htcommand(dev, HT_WEOF, 1); 1532926Swnj htcommand(dev, HT_WEOF, 1); 1542926Swnj htcommand(dev, HT_SREV, 1); 15522Sbill } 1562926Swnj if ((minor(dev)&H_NOREWIND) == 0) 1572926Swnj htcommand(dev, HT_REW, 0); 1582926Swnj sc->sc_openf = 0; 15922Sbill } 16022Sbill 1612926Swnj htcommand(dev, com, count) 1622926Swnj dev_t dev; 1632926Swnj int com, count; 16422Sbill { 16522Sbill register struct buf *bp; 1665436Sroot register int s; 16722Sbill 1682926Swnj bp = &chtbuf[HTUNIT(dev)]; 1695436Sroot s = spl5(); 1702926Swnj while (bp->b_flags&B_BUSY) { 1713157Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 1722980Swnj break; 17322Sbill bp->b_flags |= B_WANTED; 17422Sbill sleep((caddr_t)bp, PRIBIO); 17522Sbill } 1762943Swnj bp->b_flags = B_BUSY|B_READ; 1775436Sroot splx(s); 17822Sbill bp->b_dev = dev; 1792926Swnj bp->b_command = com; 1802926Swnj bp->b_repcnt = count; 18122Sbill bp->b_blkno = 0; 18222Sbill htstrategy(bp); 1832926Swnj if (count == 0) 1842926Swnj return; 18522Sbill iowait(bp); 1862926Swnj if (bp->b_flags&B_WANTED) 18722Sbill wakeup((caddr_t)bp); 1882926Swnj bp->b_flags &= B_ERROR; 18922Sbill } 19022Sbill 19122Sbill htstrategy(bp) 1922926Swnj register struct buf *bp; 19322Sbill { 1943094Swnj register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; 1952926Swnj register struct buf *dp; 1965436Sroot register int s; 19722Sbill 19822Sbill bp->av_forw = NULL; 1992926Swnj dp = &mi->mi_tab; 2005436Sroot s = spl5(); 2012926Swnj if (dp->b_actf == NULL) 2022926Swnj dp->b_actf = bp; 20322Sbill else 2042926Swnj dp->b_actl->av_forw = bp; 2052926Swnj dp->b_actl = bp; 2062926Swnj if (dp->b_active == 0) 2072926Swnj mbustart(mi); 2085436Sroot splx(s); 20922Sbill } 21022Sbill 2112926Swnj htustart(mi) 2122980Swnj register struct mba_device *mi; 21322Sbill { 2142926Swnj register struct htdevice *htaddr = 2152926Swnj (struct htdevice *)mi->mi_drv; 2162926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2173094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; 21822Sbill daddr_t blkno; 21922Sbill 2202926Swnj htaddr->httc = sc->sc_dens; 22115108Skarels #ifdef notdef 22215108Skarels /* unneeded, may hang controller */ 2233181Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { 2243157Swnj htaddr->htcs1 = HT_SENSE|HT_GO; 2253157Swnj mbclrattn(mi); 2263157Swnj } 22715108Skarels #endif 2282926Swnj sc->sc_dsreg = htaddr->htds; 2292926Swnj sc->sc_erreg = htaddr->hter; 2302926Swnj sc->sc_resid = htaddr->htfc; 2312926Swnj sc->sc_flags &= ~(H_WRITTEN|H_REWIND); 2322926Swnj if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) 2332926Swnj if (sc->sc_openf > 0) 2342926Swnj sc->sc_openf = -1; 2352926Swnj if (sc->sc_openf < 0) { 2362926Swnj bp->b_flags |= B_ERROR; 2372926Swnj return (MBU_NEXT); 2382926Swnj } 2393094Swnj if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { 2407379Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 2412926Swnj bp->b_flags |= B_ERROR; 2422926Swnj bp->b_error = ENXIO; 2432961Swnj return (MBU_NEXT); 2443094Swnj } 2457379Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 2462926Swnj bp->b_flags&B_READ) { 2472926Swnj bp->b_resid = bp->b_bcount; 2482926Swnj clrbuf(bp); 2492961Swnj return (MBU_NEXT); 2503094Swnj } 2513094Swnj if ((bp->b_flags&B_READ)==0) 2527379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 2532926Swnj } else { 2542961Swnj if (bp->b_command == HT_SENSE) 2552926Swnj return (MBU_NEXT); 2562926Swnj if (bp->b_command == HT_REW) 2572926Swnj sc->sc_flags |= H_REWIND; 2582926Swnj else 2592926Swnj htaddr->htfc = -bp->b_bcount; 2602926Swnj htaddr->htcs1 = bp->b_command|HT_GO; 2612926Swnj return (MBU_STARTED); 2622926Swnj } 2637379Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 2642926Swnj htaddr->htfc = -bp->b_bcount; 2652926Swnj if ((bp->b_flags&B_READ) == 0) { 2663094Swnj if (mi->mi_tab.b_errcnt) { 2673094Swnj if ((sc->sc_flags & H_ERASED) == 0) { 2682926Swnj sc->sc_flags |= H_ERASED; 2692926Swnj htaddr->htcs1 = HT_ERASE | HT_GO; 2702926Swnj return (MBU_STARTED); 2712926Swnj } 2723094Swnj sc->sc_flags &= ~H_ERASED; 2733094Swnj } 2742926Swnj if (htaddr->htds & HTDS_EOT) { 2752926Swnj bp->b_resid = bp->b_bcount; 2766812Swnj bp->b_flags |= B_ERROR; 2772926Swnj return (MBU_NEXT); 2782926Swnj } 27922Sbill } 2802926Swnj return (MBU_DODATA); 28122Sbill } 2827379Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 2837379Ssam htaddr->htfc = blkno - bdbtofsb(bp->b_blkno); 2842926Swnj htaddr->htcs1 = HT_SFORW|HT_GO; 28522Sbill } else { 2867379Ssam htaddr->htfc = bdbtofsb(bp->b_blkno) - blkno; 2872926Swnj htaddr->htcs1 = HT_SREV|HT_GO; 28822Sbill } 2892926Swnj return (MBU_STARTED); 29022Sbill } 29122Sbill 2923094Swnj htdtint(mi, mbsr) 2932980Swnj register struct mba_device *mi; 2943094Swnj int mbsr; 29522Sbill { 2962926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 2972926Swnj register struct buf *bp = mi->mi_tab.b_actf; 2983094Swnj register struct tu_softc *sc; 2992961Swnj int ds, er, mbs; 30022Sbill 3013094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3022926Swnj ds = sc->sc_dsreg = MASKREG(htaddr->htds); 3032926Swnj er = sc->sc_erreg = MASKREG(htaddr->hter); 3042926Swnj sc->sc_resid = MASKREG(htaddr->htfc); 3053094Swnj mbs = mbsr; 3062926Swnj sc->sc_blkno++; 3072926Swnj if((bp->b_flags & B_READ) == 0) 3082926Swnj sc->sc_flags |= H_WRITTEN; 3093094Swnj if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { 3102926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3112961Swnj mbclrattn(mi); 3122961Swnj if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { 3132926Swnj er &= ~HTER_FCE; 3143094Swnj mbs &= ~(MBSR_DTABT|MBSR_MBEXC); 3154276Sroot } 3162926Swnj if (bp->b_flags & B_READ && ds & HTDS_PES) 3172926Swnj er &= ~(HTER_CSITM|HTER_CORCRC); 3183094Swnj if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || 3192961Swnj er && ++mi->mi_tab.b_errcnt >= 7) { 3202926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3212926Swnj sc->sc_openf = -1; 3223157Swnj if ((er&HTER_HARD) == HTER_FCE && 3233157Swnj (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && 3243157Swnj (ds&HTDS_MOL)) 3253157Swnj goto noprint; 3263204Swnj printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", 3272980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3283094Swnj mbsr, mbsr_bits, 3293204Swnj sc->sc_erreg, hter_bits, 3303204Swnj sc->sc_dsreg, htds_bits); 3313157Swnj noprint: 33222Sbill bp->b_flags |= B_ERROR; 3332926Swnj return (MBD_DONE); 33422Sbill } 3352926Swnj if (er) 3362926Swnj return (MBD_RETRY); 33722Sbill } 3382926Swnj bp->b_resid = 0; 3392926Swnj if (bp->b_flags & B_READ) 3402926Swnj if (ds&HTDS_TM) { /* must be a read, right? */ 3412926Swnj bp->b_resid = bp->b_bcount; 3427379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 3432926Swnj } else if(bp->b_bcount > MASKREG(htaddr->htfc)) 3442926Swnj bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); 3452926Swnj return (MBD_DONE); 3462926Swnj } 34722Sbill 3482926Swnj htndtint(mi) 3492980Swnj register struct mba_device *mi; 3502926Swnj { 3512926Swnj register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; 3522926Swnj register struct buf *bp = mi->mi_tab.b_actf; 3533094Swnj register struct tu_softc *sc; 3542926Swnj int er, ds, fc; 35522Sbill 3563094Swnj ds = MASKREG(htaddr->htds); 3573094Swnj er = MASKREG(htaddr->hter); 3583094Swnj fc = MASKREG(htaddr->htfc); 3593094Swnj if (er) { 3602926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 3612961Swnj mbclrattn(mi); 3622961Swnj } 3633094Swnj if (bp == 0) 3643094Swnj return (MBN_SKIP); 3653094Swnj sc = &tu_softc[TUUNIT(bp->b_dev)]; 3663094Swnj sc->sc_dsreg = ds; 3673094Swnj sc->sc_erreg = er; 3683094Swnj sc->sc_resid = fc; 3693094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3703094Swnj switch (bp->b_command) { 3713094Swnj case HT_REWOFFL: 3722926Swnj /* offline is on purpose; don't do anything special */ 3732926Swnj ds |= HTDS_MOL; 3743094Swnj break; 3753094Swnj case HT_SREV: 3763094Swnj /* if backspace file hit bot, its not an error */ 3773094Swnj if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && 3783094Swnj bp->b_repcnt == INF) 3793094Swnj er &= ~HTER_NEF; 3803094Swnj break; 3813094Swnj } 3822926Swnj er &= ~HTER_FCE; 3832926Swnj if (er == 0) 3842926Swnj ds &= ~HTDS_ERR; 38522Sbill } 3862926Swnj if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { 3872926Swnj if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) 3882926Swnj sc->sc_openf = -1; 3893204Swnj printf("tu%d: hard error bn%d er=%b ds=%b\n", 3902980Swnj TUUNIT(bp->b_dev), bp->b_blkno, 3913204Swnj sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); 3922926Swnj bp->b_flags |= B_ERROR; 3932926Swnj return (MBN_DONE); 3942926Swnj } 3953094Swnj if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { 3962926Swnj if (sc->sc_flags & H_REWIND) 3972926Swnj return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); 3982926Swnj bp->b_resid = -sc->sc_resid; 3992926Swnj return (MBN_DONE); 4002926Swnj } 4012926Swnj if (ds & HTDS_TM) 4027379Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4037379Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno) - fc; 4042926Swnj sc->sc_blkno = sc->sc_nxrec; 4053094Swnj } else { 4067379Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno) + fc; 4072926Swnj sc->sc_nxrec = sc->sc_blkno - 1; 4082926Swnj } 4092926Swnj else 4107379Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 4112926Swnj return (MBN_RETRY); 41222Sbill } 41322Sbill 4147739Sroot htread(dev, uio) 4152926Swnj dev_t dev; 4167739Sroot struct uio *uio; 41722Sbill { 4188157Sroot int errno; 4192926Swnj 4208157Sroot errno = htphys(dev, uio); 4218157Sroot if (errno) 4228157Sroot return (errno); 4238157Sroot return (physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys, uio)); 42422Sbill } 42522Sbill 4268605Sroot htwrite(dev, uio) 4278605Sroot dev_t dev; 4288688Sroot struct uio *uio; 42922Sbill { 4308157Sroot int errno; 4312926Swnj 4328157Sroot errno = htphys(dev, uio); 4338157Sroot if (errno) 4348157Sroot return (errno); 4358157Sroot return (physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys, uio)); 43622Sbill } 43722Sbill 4387739Sroot htphys(dev, uio) 4392926Swnj dev_t dev; 4407739Sroot struct uio *uio; 44122Sbill { 4423094Swnj register int htunit; 4433094Swnj register struct tu_softc *sc; 4443094Swnj register struct mba_device *mi; 44522Sbill daddr_t a; 44622Sbill 4473094Swnj htunit = HTUNIT(dev); 4487832Sroot if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) 4497739Sroot return (ENXIO); 4507832Sroot a = uio->uio_offset >> 9; 4513094Swnj sc = &tu_softc[TUUNIT(dev)]; 4527379Ssam sc->sc_blkno = bdbtofsb(a); 4537379Ssam sc->sc_nxrec = bdbtofsb(a)+1; 4547739Sroot return (0); 45522Sbill } 4561917Swnj 4572926Swnj /*ARGSUSED*/ 4587636Ssam htioctl(dev, cmd, data, flag) 4592926Swnj dev_t dev; 4602926Swnj int cmd; 4617636Ssam caddr_t data; 4622926Swnj int flag; 4632926Swnj { 4643094Swnj register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; 4653094Swnj register struct buf *bp = &chtbuf[HTUNIT(dev)]; 4662926Swnj register callcount; 4672926Swnj int fcount; 4687636Ssam struct mtop *mtop; 4697636Ssam struct mtget *mtget; 4702926Swnj /* we depend of the values and order of the MT codes here */ 4712926Swnj static htops[] = 4722926Swnj {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; 4731917Swnj 4742926Swnj switch (cmd) { 4757636Ssam 4767636Ssam case MTIOCTOP: /* tape operation */ 4777636Ssam mtop = (struct mtop *)data; 4787636Ssam switch (mtop->mt_op) { 4797636Ssam 4802926Swnj case MTWEOF: 4817636Ssam callcount = mtop->mt_count; 4822926Swnj fcount = 1; 4832926Swnj break; 4847636Ssam 4852926Swnj case MTFSF: case MTBSF: 4867636Ssam callcount = mtop->mt_count; 4872926Swnj fcount = INF; 4882926Swnj break; 4897636Ssam 4902926Swnj case MTFSR: case MTBSR: 4912926Swnj callcount = 1; 4927636Ssam fcount = mtop->mt_count; 4932926Swnj break; 4947636Ssam 4952926Swnj case MTREW: case MTOFFL: 4962926Swnj callcount = 1; 4972926Swnj fcount = 1; 4982926Swnj break; 4997636Ssam 5002926Swnj default: 5018580Sroot return (ENXIO); 5022926Swnj } 5038580Sroot if (callcount <= 0 || fcount <= 0) 5048580Sroot return (EINVAL); 5052926Swnj while (--callcount >= 0) { 5067636Ssam htcommand(dev, htops[mtop->mt_op], fcount); 5077636Ssam if ((mtop->mt_op == MTFSR || mtop->mt_op == MTBSR) && 5088580Sroot bp->b_resid) 5098580Sroot return (EIO); 5103094Swnj if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) 5112926Swnj break; 5122926Swnj } 5138711Sroot return (geterror(bp)); 5147636Ssam 5152926Swnj case MTIOCGET: 5167636Ssam mtget = (struct mtget *)data; 5177636Ssam mtget->mt_dsreg = sc->sc_dsreg; 5187636Ssam mtget->mt_erreg = sc->sc_erreg; 5197636Ssam mtget->mt_resid = sc->sc_resid; 5207636Ssam mtget->mt_type = MT_ISHT; 5218580Sroot break; 5227636Ssam 5232926Swnj default: 5248580Sroot return (ENXIO); 5252926Swnj } 5268580Sroot return (0); 5272926Swnj } 5282926Swnj 5291917Swnj #define DBSIZE 20 5301917Swnj 5312926Swnj htdump() 5321917Swnj { 5332980Swnj register struct mba_device *mi; 5342926Swnj register struct mba_regs *mp; 5352926Swnj register struct htdevice *htaddr; 5362926Swnj int blk, num; 5372926Swnj int start; 5381917Swnj 5392926Swnj start = 0; 5402926Swnj num = maxfree; 5412926Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 5422926Swnj if (htinfo[0] == 0) 5432926Swnj return (ENXIO); 5442980Swnj mi = phys(htinfo[0], struct mba_device *); 5452926Swnj mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; 5463157Swnj mp->mba_cr = MBCR_IE; 5472926Swnj htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; 5482926Swnj htaddr->httc = HTTC_PDP11|HTTC_1600BPI; 5492926Swnj htaddr->htcs1 = HT_DCLR|HT_GO; 5501917Swnj while (num > 0) { 5511917Swnj blk = num > DBSIZE ? DBSIZE : num; 5522926Swnj htdwrite(start, blk, htaddr, mp); 5532926Swnj start += blk; 5541917Swnj num -= blk; 5551917Swnj } 5563157Swnj hteof(htaddr); 5573157Swnj hteof(htaddr); 5582926Swnj htwait(htaddr); 5593181Swnj if (htaddr->htds&HTDS_ERR) 5603157Swnj return (EIO); 5612926Swnj htaddr->htcs1 = HT_REW|HT_GO; 5623103Swnj return (0); 5631917Swnj } 5641917Swnj 5652926Swnj htdwrite(dbuf, num, htaddr, mp) 5662926Swnj register dbuf, num; 5672926Swnj register struct htdevice *htaddr; 5682926Swnj struct mba_regs *mp; 5691917Swnj { 5702926Swnj register struct pte *io; 5711917Swnj register int i; 5721917Swnj 5732926Swnj htwait(htaddr); 5742926Swnj io = mp->mba_map; 5751917Swnj for (i = 0; i < num; i++) 5762926Swnj *(int *)io++ = dbuf++ | PG_V; 5772926Swnj htaddr->htfc = -(num*NBPG); 5782926Swnj mp->mba_sr = -1; 5792926Swnj mp->mba_bcr = -(num*NBPG); 5802926Swnj mp->mba_var = 0; 5812926Swnj htaddr->htcs1 = HT_WCOM|HT_GO; 5821917Swnj } 5831917Swnj 5842926Swnj htwait(htaddr) 5852926Swnj struct htdevice *htaddr; 5861917Swnj { 5871917Swnj register s; 5881917Swnj 5891917Swnj do 5902926Swnj s = htaddr->htds; 5912926Swnj while ((s & HTDS_DRY) == 0); 5921917Swnj } 5931917Swnj 5942926Swnj hteof(htaddr) 5952926Swnj struct htdevice *htaddr; 5961917Swnj { 5971917Swnj 5982926Swnj htwait(htaddr); 5992926Swnj htaddr->htcs1 = HT_WEOF|HT_GO; 6001917Swnj } 6011563Sbill #endif 602