1*6881Ssam /* hpreg.h 4.11 82/05/20 */ 22551Swnj 32635Swnj struct hpdevice 42551Swnj { 52635Swnj int hpcs1; /* control and status register 1 */ 62635Swnj int hpds; /* drive status */ 72635Swnj int hper1; /* error register 1 */ 82635Swnj int hpmr; /* maintenance */ 92635Swnj int hpas; /* attention summary */ 102635Swnj int hpda; /* desired address register */ 112635Swnj int hpdt; /* drive type */ 122635Swnj int hpla; /* look ahead */ 132551Swnj int hpsn; /* serial number */ 142635Swnj int hpof; /* offset register */ 152635Swnj int hpdc; /* desired cylinder address register */ 162635Swnj int hpcc; /* current cylinder */ 17*6881Ssam #define hphr hpcc /* holding register */ 183291Swnj /* on an rp drive, mr2 is called er2 and er2 is called er3 */ 193291Swnj /* we use rm terminology here */ 203291Swnj int hpmr2; /* maintenance register 2 */ 212635Swnj int hper2; /* error register 2 */ 222635Swnj int hpec1; /* burst error bit position */ 232635Swnj int hpec2; /* burst error bit pattern */ 242551Swnj }; 252551Swnj 262635Swnj /* hpcs1 */ 272635Swnj #define HP_SC 0100000 /* special condition */ 282635Swnj #define HP_TRE 0040000 /* transfer error */ 292635Swnj #define HP_DVA 0004000 /* drive available */ 302635Swnj #define HP_RDY 0000200 /* controller ready */ 312635Swnj #define HP_IE 0000100 /* interrupt enable */ 322635Swnj /* bits 5-1 are the command */ 332635Swnj #define HP_GO 0000001 342551Swnj 352635Swnj /* commands */ 362635Swnj #define HP_NOP 000 /* no operation */ 372635Swnj #define HP_UNLOAD 002 /* offline drive */ 382635Swnj #define HP_SEEK 004 /* seek */ 392635Swnj #define HP_RECAL 006 /* recalibrate */ 402635Swnj #define HP_DCLR 010 /* drive clear */ 412635Swnj #define HP_RELEASE 012 /* release */ 422635Swnj #define HP_OFFSET 014 /* offset */ 432635Swnj #define HP_RTC 016 /* return to centerline */ 442635Swnj #define HP_PRESET 020 /* read-in preset */ 452635Swnj #define HP_PACK 022 /* pack acknowledge */ 462635Swnj #define HP_SEARCH 030 /* search */ 472635Swnj #define HP_DIAGNOSE 034 /* diagnose drive */ 482635Swnj #define HP_WCDATA 050 /* write check data */ 492635Swnj #define HP_WCHDR 052 /* write check header and data */ 502635Swnj #define HP_WCOM 060 /* write data */ 512635Swnj #define HP_WHDR 062 /* write header */ 522635Swnj #define HP_WTRACKD 064 /* write track descriptor */ 532635Swnj #define HP_RCOM 070 /* read data */ 542635Swnj #define HP_RHDR 072 /* read header and data */ 552635Swnj #define HP_RTRACKD 074 /* read track descriptor */ 562635Swnj 572635Swnj /* hpds */ 583097Swnj #define HPDS_ATA 0100000 /* attention active */ 593097Swnj #define HPDS_ERR 0040000 /* composite drive error */ 603097Swnj #define HPDS_PIP 0020000 /* positioning in progress */ 613097Swnj #define HPDS_MOL 0010000 /* medium on line */ 623097Swnj #define HPDS_WRL 0004000 /* write locked */ 633097Swnj #define HPDS_LST 0002000 /* last sector transferred */ 643097Swnj #define HPDS_PGM 0001000 /* programmable */ 653097Swnj #define HPDS_DPR 0000400 /* drive present */ 663097Swnj #define HPDS_DRY 0000200 /* drive ready */ 673097Swnj #define HPDS_VV 0000100 /* volume valid */ 682635Swnj /* bits 1-5 are spare */ 693097Swnj #define HPDS_OM 0000001 /* offset mode */ 702635Swnj 713097Swnj #define HPDS_DREADY (HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV) 722686Swnj #define HPDS_BITS \ 732686Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM" 742686Swnj 752635Swnj /* hper1 */ 763097Swnj #define HPER1_DCK 0100000 /* data check */ 773097Swnj #define HPER1_UNS 0040000 /* drive unsafe */ 783097Swnj #define HPER1_OPI 0020000 /* operation incomplete */ 793097Swnj #define HPER1_DTE 0010000 /* drive timing error */ 803097Swnj #define HPER1_WLE 0004000 /* write lock error */ 813097Swnj #define HPER1_IAE 0002000 /* invalid address error */ 823097Swnj #define HPER1_AOE 0001000 /* address overflow error */ 833097Swnj #define HPER1_HCRC 0000400 /* header crc error */ 843097Swnj #define HPER1_HCE 0000200 /* header compare error */ 853097Swnj #define HPER1_ECH 0000100 /* ecc hard error */ 863097Swnj #define HPER1_WCF 0000040 /* write clock fail */ 873097Swnj #define HPER1_FER 0000020 /* format error */ 883097Swnj #define HPER1_PAR 0000010 /* parity error */ 893097Swnj #define HPER1_RMR 0000004 /* register modification refused */ 903097Swnj #define HPER1_ILR 0000002 /* illegal register */ 913097Swnj #define HPER1_ILF 0000001 /* illegal function */ 922635Swnj 932686Swnj #define HPER1_BITS \ 942686Swnj "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\ 952686Swnj \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF" 963097Swnj #define HPER1_HARD \ 973912Swnj (HPER1_WLE|HPER1_IAE|HPER1_AOE|\ 983097Swnj HPER1_FER|HPER1_RMR|HPER1_ILR|HPER1_ILF) 992635Swnj 1002635Swnj /* hper2 */ 1013097Swnj #define HPER2_BSE 0100000 /* bad sector error */ 1023097Swnj #define HPER2_SKI 0040000 /* seek incomplete */ 1033097Swnj #define HPER2_OPE 0020000 /* operator plug error */ 1043097Swnj #define HPER2_IVC 0010000 /* invalid command */ 1053097Swnj #define HPER2_LSC 0004000 /* loss of system clock */ 1063097Swnj #define HPER2_LBC 0002000 /* loss of bit check */ 1073097Swnj #define HPER2_DVC 0000200 /* device check */ 1083147Swnj #define HPER2_SSE 0000040 /* skip sector error (rm80) */ 1093097Swnj #define HPER2_DPE 0000010 /* data parity error */ 1102635Swnj 1112686Swnj #define HPER2_BITS \ 1123097Swnj "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\10DVC\5SSE\4DPE" 1134277Sroot #define HPER2_HARD (HPER2_OPE) 1142635Swnj 1152635Swnj /* hpof */ 1163097Swnj #define HPOF_CMO 0100000 /* command modifier */ 1173097Swnj #define HPOF_MTD 0040000 /* move track descriptor */ 1183097Swnj #define HPOF_FMT22 0010000 /* 16 bit format */ 1193097Swnj #define HPOF_ECI 0004000 /* ecc inhibit */ 1203097Swnj #define HPOF_HCI 0002000 /* header compare inhibit */ 1213097Swnj #define HPOF_SSEI 0001000 /* skip sector inhibit */ 1222635Swnj 1233097Swnj #define HPOF_P400 020 /* +400 uinches */ 1243097Swnj #define HPOF_M400 0220 /* -400 uinches */ 1253097Swnj #define HPOF_P800 040 /* +800 uinches */ 1263097Swnj #define HPOF_M800 0240 /* -800 uinches */ 1273097Swnj #define HPOF_P1200 060 /* +1200 uinches */ 1283097Swnj #define HPOF_M1200 0260 /* -1200 uinches */ 1295728Sroot 130*6881Ssam /* hphr (alias hpcc) commands */ 131*6881Ssam #define HPHR_MAXCYL 0x8017 /* maximum cylinder address */ 132*6881Ssam #define HPHR_MAXTRAK 0x8018 /* maximum track address */ 133*6881Ssam #define HPHR_MAXSECT 0x8019 /* maximum sector address */ 134*6881Ssam #define HPHR_FMTENABLE 0xffff /* enable format command in cs1 */ 135*6881Ssam 1365728Sroot /* hpmr */ 1375728Sroot #define HPMR_SZ 0174000 /* ML11 system size */ 1385728Sroot #define HPMR_ARRTYP 0002000 /* ML11 array type */ 1395728Sroot #define HPMR_TRT 0001400 /* ML11 transfer rate */ 140*6881Ssam 141*6881Ssam /* 142*6881Ssam * Systems Industries kludge: use value in 143*6881Ssam * the serial # register to figure out real drive type. 144*6881Ssam */ 145*6881Ssam #define SIMB_MB 0xff00 /* model byte value */ 146*6881Ssam #define SIMB_S6 0x2000 /* switch s6 */ 147*6881Ssam #define SIMB_LU 0x0007 /* logical unit (should = drive #) */ 148*6881Ssam 149*6881Ssam #define SI9775D 0x0700 /* 9775 direct */ 150*6881Ssam #define SI9775M 0x0e00 /* 9775 mapped */ 151*6881Ssam #define SI9730D 0x0b00 /* 9730 direct */ 152*6881Ssam #define SI9730M 0x0d00 /* 9730 mapped */ 153*6881Ssam #define SI9766 0x0300 /* 9766 */ 154*6881Ssam #define SI9762 0x0100 /* 9762 */ 155*6881Ssam 156*6881Ssam #define SIRM03 0x8000 /* RM03 indication */ 157*6881Ssam #define SIRM05 0x0000 /* RM05 pseudo-indication */ 158