xref: /csrg-svn/sys/vax/mba/hpreg.h (revision 3291)
1*3291Swnj /*	hpreg.h	4.7	81/03/17	*/
22551Swnj 
32635Swnj struct hpdevice
42551Swnj {
52635Swnj 	int	hpcs1;		/* control and status register 1 */
62635Swnj 	int	hpds;		/* drive status */
72635Swnj 	int	hper1;		/* error register 1 */
82635Swnj 	int	hpmr;		/* maintenance */
92635Swnj 	int	hpas;		/* attention summary */
102635Swnj 	int	hpda;		/* desired address register */
112635Swnj 	int	hpdt;		/* drive type */
122635Swnj 	int	hpla;		/* look ahead */
132551Swnj 	int	hpsn;		/* serial number */
142635Swnj 	int	hpof;		/* offset register */
152635Swnj 	int	hpdc;		/* desired cylinder address register */
162635Swnj 	int	hpcc;		/* current cylinder */
17*3291Swnj /* on an rp drive, mr2 is called er2 and er2 is called er3 */
18*3291Swnj /* we use rm terminology here */
19*3291Swnj 	int	hpmr2;		/* maintenance register 2 */
202635Swnj 	int	hper2;		/* error register 2 */
212635Swnj 	int	hpec1;		/* burst error bit position */
222635Swnj 	int	hpec2;		/* burst error bit pattern */
232551Swnj };
242551Swnj 
252635Swnj /* hpcs1 */
262635Swnj #define	HP_SC	0100000		/* special condition */
272635Swnj #define	HP_TRE	0040000		/* transfer error */
282635Swnj #define	HP_DVA	0004000		/* drive available */
292635Swnj #define	HP_RDY	0000200		/* controller ready */
302635Swnj #define	HP_IE	0000100		/* interrupt enable */
312635Swnj /* bits 5-1 are the command */
322635Swnj #define	HP_GO	0000001
332551Swnj 
342635Swnj /* commands */
352635Swnj #define	HP_NOP		000		/* no operation */
362635Swnj #define	HP_UNLOAD	002		/* offline drive */
372635Swnj #define	HP_SEEK		004		/* seek */
382635Swnj #define	HP_RECAL	006		/* recalibrate */
392635Swnj #define	HP_DCLR		010		/* drive clear */
402635Swnj #define	HP_RELEASE	012		/* release */
412635Swnj #define	HP_OFFSET	014		/* offset */
422635Swnj #define	HP_RTC		016		/* return to centerline */
432635Swnj #define	HP_PRESET	020		/* read-in preset */
442635Swnj #define	HP_PACK		022		/* pack acknowledge */
452635Swnj #define	HP_SEARCH	030		/* search */
462635Swnj #define	HP_DIAGNOSE	034		/* diagnose drive */
472635Swnj #define	HP_WCDATA	050		/* write check data */
482635Swnj #define	HP_WCHDR	052		/* write check header and data */
492635Swnj #define	HP_WCOM		060		/* write data */
502635Swnj #define	HP_WHDR		062		/* write header */
512635Swnj #define	HP_WTRACKD	064		/* write track descriptor */
522635Swnj #define	HP_RCOM		070		/* read data */
532635Swnj #define	HP_RHDR		072		/* read header and data */
542635Swnj #define	HP_RTRACKD	074		/* read track descriptor */
552635Swnj 
562635Swnj /* hpds */
573097Swnj #define	HPDS_ATA	0100000		/* attention active */
583097Swnj #define	HPDS_ERR	0040000		/* composite drive error */
593097Swnj #define	HPDS_PIP	0020000		/* positioning in progress */
603097Swnj #define	HPDS_MOL	0010000		/* medium on line */
613097Swnj #define	HPDS_WRL	0004000		/* write locked */
623097Swnj #define	HPDS_LST	0002000		/* last sector transferred */
633097Swnj #define	HPDS_PGM	0001000		/* programmable */
643097Swnj #define	HPDS_DPR	0000400		/* drive present */
653097Swnj #define	HPDS_DRY	0000200		/* drive ready */
663097Swnj #define	HPDS_VV		0000100		/* volume valid */
672635Swnj /* bits 1-5 are spare */
683097Swnj #define	HPDS_OM		0000001		/* offset mode */
692635Swnj 
703097Swnj #define	HPDS_DREADY	(HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV)
712686Swnj #define	HPDS_BITS \
722686Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM"
732686Swnj 
742635Swnj /* hper1 */
753097Swnj #define	HPER1_DCK	0100000		/* data check */
763097Swnj #define	HPER1_UNS	0040000		/* drive unsafe */
773097Swnj #define	HPER1_OPI	0020000		/* operation incomplete */
783097Swnj #define	HPER1_DTE	0010000		/* drive timing error */
793097Swnj #define	HPER1_WLE	0004000		/* write lock error */
803097Swnj #define	HPER1_IAE	0002000		/* invalid address error */
813097Swnj #define	HPER1_AOE	0001000		/* address overflow error */
823097Swnj #define	HPER1_HCRC	0000400		/* header crc error */
833097Swnj #define	HPER1_HCE	0000200		/* header compare error */
843097Swnj #define	HPER1_ECH	0000100		/* ecc hard error */
853097Swnj #define HPER1_WCF	0000040		/* write clock fail */
863097Swnj #define	HPER1_FER	0000020		/* format error */
873097Swnj #define	HPER1_PAR	0000010		/* parity error */
883097Swnj #define	HPER1_RMR	0000004		/* register modification refused */
893097Swnj #define	HPER1_ILR	0000002		/* illegal register */
903097Swnj #define	HPER1_ILF	0000001		/* illegal function */
912635Swnj 
922686Swnj #define	HPER1_BITS \
932686Swnj "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\
942686Swnj \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF"
953097Swnj #define	HPER1_HARD    \
963097Swnj 	(HPER1_UNS|HPER1_WLE|HPER1_IAE|HPER1_AOE|\
973097Swnj 	 HPER1_FER|HPER1_RMR|HPER1_ILR|HPER1_ILF)
982635Swnj 
992635Swnj /* hper2 */
1003097Swnj #define	HPER2_BSE	0100000		/* bad sector error */
1013097Swnj #define	HPER2_SKI	0040000		/* seek incomplete */
1023097Swnj #define	HPER2_OPE	0020000		/* operator plug error */
1033097Swnj #define	HPER2_IVC	0010000		/* invalid command */
1043097Swnj #define	HPER2_LSC	0004000		/* loss of system clock */
1053097Swnj #define	HPER2_LBC	0002000		/* loss of bit check */
1063097Swnj #define	HPER2_DVC	0000200		/* device check */
1073147Swnj #define	HPER2_SSE	0000040		/* skip sector error (rm80) */
1083097Swnj #define	HPER2_DPE	0000010		/* data parity error */
1092635Swnj 
1102686Swnj #define	HPER2_BITS \
1113097Swnj "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\10DVC\5SSE\4DPE"
1123097Swnj #define	HPER2_HARD    (HPER2_BSE|HPER2_OPE)
1132635Swnj 
1142635Swnj /* hpof */
1153097Swnj #define	HPOF_CMO	0100000		/* command modifier */
1163097Swnj #define	HPOF_MTD	0040000		/* move track descriptor */
1173097Swnj #define	HPOF_FMT22	0010000		/* 16 bit format */
1183097Swnj #define	HPOF_ECI	0004000		/* ecc inhibit */
1193097Swnj #define	HPOF_HCI	0002000		/* header compare inhibit */
1203097Swnj #define	HPOF_SSEI	0001000		/* skip sector inhibit */
1212635Swnj 
1223097Swnj #define	HPOF_P400	020		/*  +400 uinches */
1233097Swnj #define	HPOF_M400	0220		/*  -400 uinches */
1243097Swnj #define	HPOF_P800	040		/*  +800 uinches */
1253097Swnj #define	HPOF_M800	0240		/*  -800 uinches */
1263097Swnj #define	HPOF_P1200	060		/* +1200 uinches */
1273097Swnj #define	HPOF_M1200	0260		/* -1200 uinches */
128