1*3147Swnj /* hpreg.h 4.6 81/03/09 */ 22551Swnj 32635Swnj struct hpdevice 42551Swnj { 52635Swnj int hpcs1; /* control and status register 1 */ 62635Swnj int hpds; /* drive status */ 72635Swnj int hper1; /* error register 1 */ 82635Swnj int hpmr; /* maintenance */ 92635Swnj int hpas; /* attention summary */ 102635Swnj int hpda; /* desired address register */ 112635Swnj int hpdt; /* drive type */ 122635Swnj int hpla; /* look ahead */ 132551Swnj int hpsn; /* serial number */ 142635Swnj int hpof; /* offset register */ 152635Swnj int hpdc; /* desired cylinder address register */ 162635Swnj int hpcc; /* current cylinder */ 172635Swnj int hper2; /* error register 2 */ 182635Swnj int hper3; /* error register 3 */ 192635Swnj int hpec1; /* burst error bit position */ 202635Swnj int hpec2; /* burst error bit pattern */ 212551Swnj }; 222551Swnj 232635Swnj /* hpcs1 */ 242635Swnj #define HP_SC 0100000 /* special condition */ 252635Swnj #define HP_TRE 0040000 /* transfer error */ 262635Swnj #define HP_DVA 0004000 /* drive available */ 272635Swnj #define HP_RDY 0000200 /* controller ready */ 282635Swnj #define HP_IE 0000100 /* interrupt enable */ 292635Swnj /* bits 5-1 are the command */ 302635Swnj #define HP_GO 0000001 312551Swnj 322635Swnj /* commands */ 332635Swnj #define HP_NOP 000 /* no operation */ 342635Swnj #define HP_UNLOAD 002 /* offline drive */ 352635Swnj #define HP_SEEK 004 /* seek */ 362635Swnj #define HP_RECAL 006 /* recalibrate */ 372635Swnj #define HP_DCLR 010 /* drive clear */ 382635Swnj #define HP_RELEASE 012 /* release */ 392635Swnj #define HP_OFFSET 014 /* offset */ 402635Swnj #define HP_RTC 016 /* return to centerline */ 412635Swnj #define HP_PRESET 020 /* read-in preset */ 422635Swnj #define HP_PACK 022 /* pack acknowledge */ 432635Swnj #define HP_SEARCH 030 /* search */ 442635Swnj #define HP_DIAGNOSE 034 /* diagnose drive */ 452635Swnj #define HP_WCDATA 050 /* write check data */ 462635Swnj #define HP_WCHDR 052 /* write check header and data */ 472635Swnj #define HP_WCOM 060 /* write data */ 482635Swnj #define HP_WHDR 062 /* write header */ 492635Swnj #define HP_WTRACKD 064 /* write track descriptor */ 502635Swnj #define HP_RCOM 070 /* read data */ 512635Swnj #define HP_RHDR 072 /* read header and data */ 522635Swnj #define HP_RTRACKD 074 /* read track descriptor */ 532635Swnj 542635Swnj /* hpds */ 553097Swnj #define HPDS_ATA 0100000 /* attention active */ 563097Swnj #define HPDS_ERR 0040000 /* composite drive error */ 573097Swnj #define HPDS_PIP 0020000 /* positioning in progress */ 583097Swnj #define HPDS_MOL 0010000 /* medium on line */ 593097Swnj #define HPDS_WRL 0004000 /* write locked */ 603097Swnj #define HPDS_LST 0002000 /* last sector transferred */ 613097Swnj #define HPDS_PGM 0001000 /* programmable */ 623097Swnj #define HPDS_DPR 0000400 /* drive present */ 633097Swnj #define HPDS_DRY 0000200 /* drive ready */ 643097Swnj #define HPDS_VV 0000100 /* volume valid */ 652635Swnj /* bits 1-5 are spare */ 663097Swnj #define HPDS_OM 0000001 /* offset mode */ 672635Swnj 683097Swnj #define HPDS_DREADY (HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV) 692686Swnj #define HPDS_BITS \ 702686Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM" 712686Swnj 722635Swnj /* hper1 */ 733097Swnj #define HPER1_DCK 0100000 /* data check */ 743097Swnj #define HPER1_UNS 0040000 /* drive unsafe */ 753097Swnj #define HPER1_OPI 0020000 /* operation incomplete */ 763097Swnj #define HPER1_DTE 0010000 /* drive timing error */ 773097Swnj #define HPER1_WLE 0004000 /* write lock error */ 783097Swnj #define HPER1_IAE 0002000 /* invalid address error */ 793097Swnj #define HPER1_AOE 0001000 /* address overflow error */ 803097Swnj #define HPER1_HCRC 0000400 /* header crc error */ 813097Swnj #define HPER1_HCE 0000200 /* header compare error */ 823097Swnj #define HPER1_ECH 0000100 /* ecc hard error */ 833097Swnj #define HPER1_WCF 0000040 /* write clock fail */ 843097Swnj #define HPER1_FER 0000020 /* format error */ 853097Swnj #define HPER1_PAR 0000010 /* parity error */ 863097Swnj #define HPER1_RMR 0000004 /* register modification refused */ 873097Swnj #define HPER1_ILR 0000002 /* illegal register */ 883097Swnj #define HPER1_ILF 0000001 /* illegal function */ 892635Swnj 902686Swnj #define HPER1_BITS \ 912686Swnj "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\ 922686Swnj \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF" 933097Swnj #define HPER1_HARD \ 943097Swnj (HPER1_UNS|HPER1_WLE|HPER1_IAE|HPER1_AOE|\ 953097Swnj HPER1_FER|HPER1_RMR|HPER1_ILR|HPER1_ILF) 962635Swnj 972635Swnj /* hper2 */ 983097Swnj #define HPER2_BSE 0100000 /* bad sector error */ 993097Swnj #define HPER2_SKI 0040000 /* seek incomplete */ 1003097Swnj #define HPER2_OPE 0020000 /* operator plug error */ 1013097Swnj #define HPER2_IVC 0010000 /* invalid command */ 1023097Swnj #define HPER2_LSC 0004000 /* loss of system clock */ 1033097Swnj #define HPER2_LBC 0002000 /* loss of bit check */ 1043097Swnj #define HPER2_DVC 0000200 /* device check */ 105*3147Swnj #define HPER2_SSE 0000040 /* skip sector error (rm80) */ 1063097Swnj #define HPER2_DPE 0000010 /* data parity error */ 1072635Swnj 1082686Swnj #define HPER2_BITS \ 1093097Swnj "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\10DVC\5SSE\4DPE" 1103097Swnj #define HPER2_HARD (HPER2_BSE|HPER2_OPE) 1112635Swnj 1122635Swnj /* hpof */ 1133097Swnj #define HPOF_CMO 0100000 /* command modifier */ 1143097Swnj #define HPOF_MTD 0040000 /* move track descriptor */ 1153097Swnj #define HPOF_FMT22 0010000 /* 16 bit format */ 1163097Swnj #define HPOF_ECI 0004000 /* ecc inhibit */ 1173097Swnj #define HPOF_HCI 0002000 /* header compare inhibit */ 1183097Swnj #define HPOF_SSEI 0001000 /* skip sector inhibit */ 1192635Swnj 1203097Swnj #define HPOF_P400 020 /* +400 uinches */ 1213097Swnj #define HPOF_M400 0220 /* -400 uinches */ 1223097Swnj #define HPOF_P800 040 /* +800 uinches */ 1233097Swnj #define HPOF_M800 0240 /* -800 uinches */ 1243097Swnj #define HPOF_P1200 060 /* +1200 uinches */ 1253097Swnj #define HPOF_M1200 0260 /* -1200 uinches */ 126