1*2551Swnj /* hpreg.h 4.1 81/02/19 */ 2*2551Swnj 3*2551Swnj struct device 4*2551Swnj { 5*2551Swnj int hpcs1; /* control and Status register 1 */ 6*2551Swnj int hpds; /* Drive Status */ 7*2551Swnj int hper1; /* Error register 1 */ 8*2551Swnj int hpmr; /* Maintenance */ 9*2551Swnj int hpas; /* Attention Summary */ 10*2551Swnj int hpda; /* Desired address register */ 11*2551Swnj int hpdt; /* Drive type */ 12*2551Swnj int hpla; /* Look ahead */ 13*2551Swnj int hpsn; /* serial number */ 14*2551Swnj int hpof; /* Offset register */ 15*2551Swnj int hpdc; /* Desired Cylinder address register */ 16*2551Swnj int hpcc; /* Current Cylinder */ 17*2551Swnj int hper2; /* Error register 2 */ 18*2551Swnj int hper3; /* Error register 3 */ 19*2551Swnj int hpec1; /* Burst error bit position */ 20*2551Swnj int hpec2; /* Burst error bit pattern */ 21*2551Swnj }; 22*2551Swnj 23*2551Swnj #define GO 01 24*2551Swnj #define PRESET 020 25*2551Swnj #define RTC 016 26*2551Swnj #define OFFSET 014 27*2551Swnj #define SEEK 04 28*2551Swnj #define SEARCH 030 29*2551Swnj #define RECAL 06 30*2551Swnj #define DCLR 010 31*2551Swnj #define WCOM 060 32*2551Swnj #define RCOM 070 33*2551Swnj #define RELEASE 012 34*2551Swnj 35*2551Swnj #define DVA 04000 36*2551Swnj #define IE 0100 37*2551Swnj #define PIP 020000 38*2551Swnj #define DRY 0200 39*2551Swnj #define ERR 040000 40*2551Swnj #define TRE 040000 41*2551Swnj #define DCK 0100000 42*2551Swnj #define WLE 04000 43*2551Swnj #define ECH 0100 44*2551Swnj #define VV 0100 45*2551Swnj #define DPR 0400 46*2551Swnj #define MOL 010000 47*2551Swnj #define FMT22 010000 48*2551Swnj #define P400 020 49*2551Swnj #define M400 0220 50*2551Swnj #define P800 040 51*2551Swnj #define M800 0240 52*2551Swnj #define P1200 060 53*2551Swnj #define M1200 0260 54