xref: /csrg-svn/sys/vax/mba/hpreg.h (revision 23309)
1*23309Smckusick /*
2*23309Smckusick  * Copyright (c) 1982 Regents of the University of California.
3*23309Smckusick  * All rights reserved.  The Berkeley software License Agreement
4*23309Smckusick  * specifies the terms and conditions for redistribution.
5*23309Smckusick  *
6*23309Smckusick  *	@(#)hpreg.h	6.2 (Berkeley) 06/08/85
7*23309Smckusick  */
82551Swnj 
92635Swnj struct hpdevice
102551Swnj {
112635Swnj 	int	hpcs1;		/* control and status register 1 */
122635Swnj 	int	hpds;		/* drive status */
132635Swnj 	int	hper1;		/* error register 1 */
142635Swnj 	int	hpmr;		/* maintenance */
152635Swnj 	int	hpas;		/* attention summary */
162635Swnj 	int	hpda;		/* desired address register */
172635Swnj 	int	hpdt;		/* drive type */
182635Swnj 	int	hpla;		/* look ahead */
192551Swnj 	int	hpsn;		/* serial number */
202635Swnj 	int	hpof;		/* offset register */
212635Swnj 	int	hpdc;		/* desired cylinder address register */
222635Swnj 	int	hpcc;		/* current cylinder */
236881Ssam #define	hphr	hpcc		/* holding register */
243291Swnj /* on an rp drive, mr2 is called er2 and er2 is called er3 */
253291Swnj /* we use rm terminology here */
263291Swnj 	int	hpmr2;		/* maintenance register 2 */
272635Swnj 	int	hper2;		/* error register 2 */
282635Swnj 	int	hpec1;		/* burst error bit position */
292635Swnj 	int	hpec2;		/* burst error bit pattern */
302551Swnj };
312551Swnj 
322635Swnj /* hpcs1 */
332635Swnj #define	HP_SC	0100000		/* special condition */
342635Swnj #define	HP_TRE	0040000		/* transfer error */
352635Swnj #define	HP_DVA	0004000		/* drive available */
362635Swnj #define	HP_RDY	0000200		/* controller ready */
372635Swnj #define	HP_IE	0000100		/* interrupt enable */
382635Swnj /* bits 5-1 are the command */
392635Swnj #define	HP_GO	0000001
402551Swnj 
412635Swnj /* commands */
422635Swnj #define	HP_NOP		000		/* no operation */
432635Swnj #define	HP_UNLOAD	002		/* offline drive */
442635Swnj #define	HP_SEEK		004		/* seek */
452635Swnj #define	HP_RECAL	006		/* recalibrate */
462635Swnj #define	HP_DCLR		010		/* drive clear */
472635Swnj #define	HP_RELEASE	012		/* release */
482635Swnj #define	HP_OFFSET	014		/* offset */
492635Swnj #define	HP_RTC		016		/* return to centerline */
502635Swnj #define	HP_PRESET	020		/* read-in preset */
512635Swnj #define	HP_PACK		022		/* pack acknowledge */
522635Swnj #define	HP_SEARCH	030		/* search */
532635Swnj #define	HP_DIAGNOSE	034		/* diagnose drive */
542635Swnj #define	HP_WCDATA	050		/* write check data */
552635Swnj #define	HP_WCHDR	052		/* write check header and data */
562635Swnj #define	HP_WCOM		060		/* write data */
572635Swnj #define	HP_WHDR		062		/* write header */
582635Swnj #define	HP_WTRACKD	064		/* write track descriptor */
592635Swnj #define	HP_RCOM		070		/* read data */
602635Swnj #define	HP_RHDR		072		/* read header and data */
612635Swnj #define	HP_RTRACKD	074		/* read track descriptor */
622635Swnj 
632635Swnj /* hpds */
643097Swnj #define	HPDS_ATA	0100000		/* attention active */
653097Swnj #define	HPDS_ERR	0040000		/* composite drive error */
663097Swnj #define	HPDS_PIP	0020000		/* positioning in progress */
673097Swnj #define	HPDS_MOL	0010000		/* medium on line */
683097Swnj #define	HPDS_WRL	0004000		/* write locked */
693097Swnj #define	HPDS_LST	0002000		/* last sector transferred */
703097Swnj #define	HPDS_PGM	0001000		/* programmable */
713097Swnj #define	HPDS_DPR	0000400		/* drive present */
723097Swnj #define	HPDS_DRY	0000200		/* drive ready */
733097Swnj #define	HPDS_VV		0000100		/* volume valid */
742635Swnj /* bits 1-5 are spare */
753097Swnj #define	HPDS_OM		0000001		/* offset mode */
762635Swnj 
773097Swnj #define	HPDS_DREADY	(HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV)
782686Swnj #define	HPDS_BITS \
792686Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM"
802686Swnj 
812635Swnj /* hper1 */
823097Swnj #define	HPER1_DCK	0100000		/* data check */
833097Swnj #define	HPER1_UNS	0040000		/* drive unsafe */
843097Swnj #define	HPER1_OPI	0020000		/* operation incomplete */
853097Swnj #define	HPER1_DTE	0010000		/* drive timing error */
863097Swnj #define	HPER1_WLE	0004000		/* write lock error */
873097Swnj #define	HPER1_IAE	0002000		/* invalid address error */
883097Swnj #define	HPER1_AOE	0001000		/* address overflow error */
893097Swnj #define	HPER1_HCRC	0000400		/* header crc error */
903097Swnj #define	HPER1_HCE	0000200		/* header compare error */
913097Swnj #define	HPER1_ECH	0000100		/* ecc hard error */
923097Swnj #define HPER1_WCF	0000040		/* write clock fail */
933097Swnj #define	HPER1_FER	0000020		/* format error */
943097Swnj #define	HPER1_PAR	0000010		/* parity error */
953097Swnj #define	HPER1_RMR	0000004		/* register modification refused */
963097Swnj #define	HPER1_ILR	0000002		/* illegal register */
973097Swnj #define	HPER1_ILF	0000001		/* illegal function */
982635Swnj 
992686Swnj #define	HPER1_BITS \
1002686Swnj "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\
1012686Swnj \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF"
1023097Swnj #define	HPER1_HARD    \
1033912Swnj 	(HPER1_WLE|HPER1_IAE|HPER1_AOE|\
1043097Swnj 	 HPER1_FER|HPER1_RMR|HPER1_ILR|HPER1_ILF)
1052635Swnj 
1062635Swnj /* hper2 */
1073097Swnj #define	HPER2_BSE	0100000		/* bad sector error */
1083097Swnj #define	HPER2_SKI	0040000		/* seek incomplete */
1093097Swnj #define	HPER2_OPE	0020000		/* operator plug error */
1103097Swnj #define	HPER2_IVC	0010000		/* invalid command */
1113097Swnj #define	HPER2_LSC	0004000		/* loss of system clock */
1123097Swnj #define	HPER2_LBC	0002000		/* loss of bit check */
1133097Swnj #define	HPER2_DVC	0000200		/* device check */
1143147Swnj #define	HPER2_SSE	0000040		/* skip sector error (rm80) */
1153097Swnj #define	HPER2_DPE	0000010		/* data parity error */
1162635Swnj 
1172686Swnj #define	HPER2_BITS \
11810625Shelge "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\10DVC\6SSE\4DPE"
1194277Sroot #define	HPER2_HARD    (HPER2_OPE)
1202635Swnj 
1212635Swnj /* hpof */
1223097Swnj #define	HPOF_CMO	0100000		/* command modifier */
1233097Swnj #define	HPOF_MTD	0040000		/* move track descriptor */
1243097Swnj #define	HPOF_FMT22	0010000		/* 16 bit format */
1253097Swnj #define	HPOF_ECI	0004000		/* ecc inhibit */
1263097Swnj #define	HPOF_HCI	0002000		/* header compare inhibit */
1273097Swnj #define	HPOF_SSEI	0001000		/* skip sector inhibit */
1282635Swnj 
1293097Swnj #define	HPOF_P400	020		/*  +400 uinches */
1303097Swnj #define	HPOF_M400	0220		/*  -400 uinches */
1313097Swnj #define	HPOF_P800	040		/*  +800 uinches */
1323097Swnj #define	HPOF_M800	0240		/*  -800 uinches */
1333097Swnj #define	HPOF_P1200	060		/* +1200 uinches */
1343097Swnj #define	HPOF_M1200	0260		/* -1200 uinches */
1355728Sroot 
1366881Ssam /* hphr (alias hpcc) commands */
1376881Ssam #define	HPHR_MAXCYL	0x8017		/* maximum cylinder address */
1386881Ssam #define	HPHR_MAXTRAK	0x8018		/* maximum track address */
1396881Ssam #define	HPHR_MAXSECT	0x8019		/* maximum sector address */
1406881Ssam #define	HPHR_FMTENABLE	0xffff		/* enable format command in cs1 */
1416881Ssam 
1425728Sroot /* hpmr */
1435728Sroot #define	HPMR_SZ		0174000		/* ML11 system size */
1445728Sroot #define	HPMR_ARRTYP	0002000		/* ML11 array type */
1455728Sroot #define	HPMR_TRT	0001400		/* ML11 transfer rate */
1466881Ssam 
1476881Ssam /*
1486881Ssam  * Systems Industries kludge: use value in
1496881Ssam  * the serial # register to figure out real drive type.
1506881Ssam  */
1516881Ssam #define	SIMB_MB	0xff00		/* model byte value */
1526881Ssam #define	SIMB_S6	0x2000		/* switch s6 */
1536881Ssam #define	SIMB_LU	0x0007		/* logical unit (should = drive #) */
1546881Ssam 
1556881Ssam #define	SI9775D	0x0700		/* 9775 direct */
1566881Ssam #define	SI9775M	0x0e00		/* 9775 mapped */
1576881Ssam #define	SI9730D	0x0b00		/* 9730 direct */
1586881Ssam #define	SI9730M	0x0d00		/* 9730 mapped */
1596881Ssam #define	SI9766	0x0300		/* 9766 */
1606881Ssam #define	SI9762	0x0100		/* 9762 */
16111124Ssam #define	SICAPD	0x0500		/* Capricorn direct */
16211124Ssam #define	SICAPN	0x0400		/* Capricorn mapped */
16311124Ssam #define	SI9751D	0x0f00		/* Eagle direct */
1646881Ssam 
1656881Ssam #define	SIRM03	0x8000		/* RM03 indication */
1666881Ssam #define	SIRM05	0x0000		/* RM05 pseudo-indication */
167